Abstract: The formation of microelectronic structures in trenches and vias of an integrated circuit wafer are described using nanocrystal solutions. A nanocrystal solution is applied to flood the wafer surface. The solvent penetrates the trench recesses within the wafer surface. In the process, nanocrystals dissolved or suspended in the solution are carried into these regions. The solvent volatilizes more quickly from the wafer plateaus as compared to the recesses causing the nanocrystals to become concentrated in the shrinking solvent pools within the recesses. The nanocrystals become stranded in the dry trenches. Heating the wafer to a temperature sufficient to sinter or melt the nanocrystals results in the formation of bulk polycrystalline domains. Heating is also carried out concurrently with nanocrystals solution deposition. Copper nanocrystals of less than about 5 nanometers are particularly well suited for formation of interconnects at temperatures of less than 350 degrees Celsius.

Abstract: The effective area of a MIM capacitor is increased by forming a lower electrode that includes hemispherical grain lumps. The hemispherical grain lumps are formed by heat-treating a metal layer in an oxygen and/or nitrogen atmosphere, thus oxidizing the surface of the metal layer or growing the crystal grains of the metal layer. The MIM capacitor may be formed of Pt, Ru, Rh, Os, Ir, or Pd, and the hemispherical grain lumps may be formed of Pt, Ru, Rh, Os, Ir, or Pd. Since the metal layer is primarily heat-treated during the formation of the lower electrode, it is possible to reduce the degree to which the surface morphology of the lower electrode is rapidly changed due to a heat treatment subsequent to forming a dielectric layer and an upper electrode.

Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.

Abstract: In a deposition method according to the present invention, a substrate (10) is first arranged in a processing vessel to carry out a heat-up step. Then, Si-containing gas, such as SiH4 gas, is supplied into the processing vessel to carry out an initiation step serving as a pretreating step on the substrate (ST2). Then, a deposition gas is supplied into the processing vessel to carry out a deposition step (ST3). By carrying out the initiation step (ST2) by setting the partial pressure of the Si-containing gas to be not less than 50 Pa (not less than 100 Pa when the heat-up step is not carried out), it is possible to stably produce a film having a good surface condition.

Abstract: A technique for forming a high surface area electrode or storage node for a capacitor and devices formed thereby, including depositing a first layer of conductive material on a substrate, such that a discontinuous layer is formed. A second conductive material layer is deposited over the discontinuous first conductive material layer, such that the second conductive material layer grows or accumulates on the discontinuous first conductive material layer at a faster rate than on the exposed areas of the substrate in the discontinuous first conductive material layer to form a rough conductive material layer.

Abstract: A plurality of successive layers are firmly adhered to one another and to a wafer surface and an electrical component or sub-assembly even when the wafer surface is not even and the layers are bent. The wafer surface is initially cleaned by an ion bombardment of an inert gas (e.g. argon) on the wafer surface in an RF discharge at a relatively high gas pressure. The wafer surface is then provided with a microscopic roughness by applying a low power so that the inert gas (e.g. argon) ions do not have sufficient energy to etch the surface. A layer of chromium is then sputter deposited on the wafer surface as by a DC magnetron with an intrinsic tensile stress and low gas entrapment by passing a minimal amount of the inert gas through the magnetron and by applying no RF bias to the wafer. The chromium layer is atomically bonded to the microscopically rough wafer surface.

Abstract: A semiconductor device includes a MOS transistor, interlayer dielectric film, first and second high-dielectric-constant films, and first and second conductive films. The MOS transistor is formed on a semiconductor substrate. The interlayer dielectric film is formed on the semiconductor substrate so as to cover the MOS transistor. The first high-dielectric-constant film is formed on the interlayer dielectric film and has an opening portion that reaches the interlayer dielectric film. The first conductive film contains a metal element and is formed to be partially embedded in the opening portion. The second high-dielectric-constant film is formed on the first conductive film. The second conductive film is formed on the second high-dielectric-constant film.

Abstract: The present invention provides methods of forming in situ doped rugged silicon and semiconductor devices incorporating conductive rugged silicon. In one aspect, the methods involve forming a layer of amorphous silicon on a substrate at a substantially constant deposition temperature; and converting the layer of amorphous silicon into hemispherical grain silicon by subjecting the layer of amorphous silicon to substantially the deposition temperature while varying pressure.

Abstract: Methods for forming elements having a predetermined shape and for assembling the elements. In one example of a method, each of the elements includes a functional component which is disposed on a first face of a first substrate. A layer representing a first portion of the first substrate at a second face of the first substrate is removed, leaving a second portion of the first substrate on the first substrate. The second portion is etched through a first patterned mask on a surface of the second portion. The plurality of elements is then released from the first substrate. The plurality of elements may then be combined with a fluid to form a slurry. In another example of a method, the first face is etched vertically in regions adjacent to the edges of the plurality of elements, and regions below the first face are etched laterally, and then the plurality of elements are released from the substrate.

Abstract: An integrated circuit contactor includes a base of an insulating material, the base being elastically deformable. A plurality of pads of a first conductive material are bonded to the base at positions corresponding to positions of terminals on an integrated circuit. A plurality of contacts of a second conductive material are bonded to the plurality of pads, respectively, the terminals of the integrated circuit being electrically connected to the contacts only when a pressure is exerted onto the contacts by the terminals of the integrated circuit, each contact having a projecting edge with a roughness produced by pulling a wire of the second conductive material apart from a corresponding one of the plurality of pads after the wire is bonded to the corresponding pad.

Abstract: Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.

Abstract: A method of fabricating a semiconductor capacitor is disclosed. An impurity layer is formed on a semiconductor substrate. An interlayer insulating film is disposed on an upper surface of the impurity layer and the semiconductor substrate. A contact hole is selectively etched through the interlayer insulating film to the impurity layer. A conductive plug is formed in the contact hole. A metal film pattern having an irregular surface area is disposed on the conductive plug. A dielectric substance film is located directly on the irregular surface of the metal film pattern. A metal electrode is formed on the dielectric substance film.

Abstract: The present invention provides a method of preparing a surface of a silicon wafer for formation of HSG structures. The method contemplates providing a wafer having at least one HSG template comprising polysilicon formed in BPSG, the HSG template being covered by silicon dioxide. The wafer is treated with a cleaning agent to clean the surface of the wafer. Next, the wafer is treated with a conditioning agent. The conditioning agent removes native oxide from the HSG template without excessively etching structural BPSG. Preferably, the conditioning agent also removes a thin layer of polysilicon on the HSG template. The wafer is then transferred to a process chamber for HSG formation.

Abstract: Method and apparatus for an on-chip decoupling capacitor. The capacitor includes a bottom electrode that consist of nanostructures deposited over a planarized metal, a dielectric material deposited over the nanostructures, and a top electrode deposited over the dielectric material. The shape of the bottom electrode is tunable by modulating the diameter and/or the length of the nanostructures to produce an increase in capacitance without increasing the footprint of the on-chip decoupling capacitor.

Abstract: Methods are disclosed for manufacturing semiconductor device dies and for removing material from the bottom side of the wafer dies, wherein a contoured surface is provided on the die bottom, such as through an etching process. In addition, methods are disclosed for securing a semiconductor device to a surface. Semiconductor wafers and die are also disclosed having contoured bottom surfaces.

Abstract: A method of fabricating a capacitor of a DRAM cell. First, an insulating layer is formed on the semiconductor substrate at the top portion of the trench. Afterward, a seed layer on the ringed insulating layer and the semiconductor substrate at the bottom portion of the trench. A photoresist is coated in the trench at the bottom portion. Next, the seed layer is partially removed to expose the ringed insulating layer while the photoresist is used as the shield. The photoresist is then removed to expose the remaining seed layer at the bottom portion. A hemispherical silicon grain layer is deposited from the remaining seed layer on the semiconductor substrate. Ions are doped the hemispherical silicon grain layer and the semiconductor substrate so as to create a doped area to serve as the lower electrode of the capacitor.

Abstract: A bond pad is formed by first providing a planarized combination of copper and silicon oxide features in a bond pad region. The silicon oxide features are etched back to provide a plurality recesses in the copper in the bond pad region. A corrosion barrier is formed over the copper and the silicon oxide features in the recesses. Probing of the wafer is done by directly applying the probe to the copper. A wire bond is directly attached to the copper. The presence of the features improves probe performance because the probe is likely to slip. Also the probe is prevented from penetrating all the way through the copper because the recessed features are present. With the recesses in the copper, the wire bond more readily breaks down and penetrates the corrosion barrier and is also less likely to slip on the bond pad.

Abstract: A method for forming a gate electrode of a semiconductor device, which improves thermal stability of a tungsten/polysilicon structure. The method for forming a gate electrode of a semiconductor device includes: sequentially forming a first insulating film, a polysilicon layer and a tungsten layer on a semiconductor substrate; adding oxygen to the tungsten layer; forming a second insulating film on the tungsten layer to which oxygen is added; and selectively removing the second insulating film, the tungsten layer, the polysilicon layer and the first insulating film to form a gate electrode.

Abstract: A method of improving adhesion of a surface including the following steps. A structure having an upper surface is provided. A composite anchor layer is formed over the upper surface of the structure. The composite anchor layer including at least an upper anchor sub-layer and a lower anchor sub-layer. The upper anchor sub-layer is patterned to form a dense pattern of upper sub-anchors. The lower anchor sub-layer is then patterned using the upper sub-anchors as masks to form lower sub-anchors. The respective upper sub-anchors and lower sub-anchors form a dense pattern of anchors whereby the dense pattern of anchors over the upper surface improve the adhesion of the surface.

Abstract: Some of the members constituting a semiconductor element are formed from &agr;-Si and an HSG forming process is implemented to form hemispherical polysilicon grains at some of the members formed from &agr;-Si. Thus, a semiconductor device that is achieved without requiring a great number of manufacturing steps such as film formation and etching, facilitates control of the individual steps and assures reliable electrical connection between the members and a method of manufacturing such a semiconductor device are provided.

Abstract: A semiconductor device which has trenches for raising the reliability thereof and a method for manufacturing such device. An electrode pad, and a protective film and an interlayer film which comprise an opening on top of this electrode pad, are formed on a substrate. A rewiring pattern which is in contact with the electrode pad at this opening is formed on top of the interlayer film. In addition, a trench is formed, by means of etching, in the region on this interlayer film where said rewiring pattern is not formed. A bump is formed on top of said rewiring pattern. The rewiring pattern and the trench are covered by means of a sealing film. The sealing film exposes the upper end of the bump. An external terminal is formed on the upper end of this bump. The trenches make the contact area between the covering film and the sealing film larger and therefore increase the adhesion between the covering film and the sealing film.

Abstract: A method of forming metal thin film of a memory device includes the steps of forming a metal layer on a semiconductor substrate, forming uniform grains on a surface of the metal layer, and forming a dielectric layer on the metal layer.

Abstract: A method of producing a semiconductor memory having a memory cell structure in which a storage node, which consists of a capacitor electrode film having a rugged surface formed inside holes of an interlayer insulating film that is deposited on a substrate, constitutes a capacitor together with a cell plate through a dielectric film.

Abstract: A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.

Abstract: A method for fabricating deep-submicron DRAMs containing a deep trench capacitor with enlarged sidewall surface for improved storage capacitance. It includes the main steps of: (a) forming a silicon substrate having a (110) crystalline plane and a (111) crystalline plane; (b) forming a vertically extending deep trench into a crystalline silicon substrate; (c) filling the deep trench with a first dielectric material to form a first dielectric filler layer; (d) etching back the first dielectric filler layer to a first depth; (e) forming a dielectric collar from a second dielectric material which hangs on the sidewall of the deep trench extending from the opening of the trench to the first depth; (f) removing the first dielectric filler layer with a selective etching process; and (g) under a carefully timed exposure, using an isotropic etching solution which has high etching rate in the (110) plane and low etching rate in the (111) plane to form a roughened surface on the bottom surface of the deep trench.

Abstract: An electrode pad PAD, which is a layer 11 substantially made of aluminum to be connected to an internal conductive region, is formed on an interlayer insulation film 10 made of an SiO2 layer or the like so as to be exposed in an opening portion of a passivation film 12 as the uppermost layer. For example, a bonding wire not shown in the drawing is connected to the electrode pad PAD. The exposed surface of the electrode pad PAD comprises a rough surface R roughened by means of an etching solution. Thereby, the surface of the electrode pad PAD has a substantially constant roughness, which increases the contact area for the bonding wire not shown in the drawing.

Abstract: A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process.

Abstract: Implemented are a semiconductor device comprising a trench type capacitor having such a structure that a soft error tolerance is excellent, a contact resistance between an electrode and a metal wiring has a small value, a fringe capacitance on an end is reduced and area penalty is not increased, and a method for manufacturing the semiconductor device. The trench type capacitor is formed to have a bottom face in a BOX layer (2) without penetrating the BOX layer (2). Moreover, an end of the capacitor, that is, each of ends of a first electrode (6), a dielectric film (7) and a second electrode (8) is flattened. An insulating film (16) and a side wall (9) are formed to cover the ends of the first electrode (6), the dielectric film (7) and the second electrode (8). Furthermore, a contact plug (10) for connecting the second electrode (8) to a metal wiring (14a) provided as an upper layer is buried in a region surrounded by the side wall (9).

Abstract: A microstructure comprises a conductive layer of aluminum, copper or alloys thereof on a substrate wherein the layer comprises metal grains at least about 0.1 microns and barrier material deposited in the grainboundaries of the surface of the metal is provided along with a method for its fabrication.

Abstract: Disclosed herein is a method of manufacturing a semiconductor capacitor. In the semiconductor capacitor manufacturing method, an amorphous film composed of non-doped silicon is formed. The amorphous film is changed to a lower film having projections and depressions defined in the surface thereof by heat treatment. An amorphous film composed of impurity-doped silicon is formed over the surface of the lower film. Further, the amorphous film composed of the impurity-doped silicon is changed to an upper film having projections and depressions defined in the surface thereof by heat treatment with the projections and depressions provided over the surface of the lower film as a basis. The semiconductor capacitor is equipped with an electrode having the lower film and the upper film.

Abstract: There are contained the steps of forming an undoped or low impurity concentration amorphous silicon film to project from an upper surface of a first insulating film, introducing selectively impurity into an uppermost surface of the amorphous silicon film to form the uppermost surface of the amorphous silicon film as a high concentration impurity region, forming hemispherical grained silicon on the uppermost surface of the amorphous silicon film at a first density and on a side surface at a second density higher than the first density by exposing the amorphous silicon film to a silicon compound gas and then annealing the amorphous silicon film in a low pressure atmosphere, and introducing the impurity into the hemispherical grained silicon and the amorphous silicon film. Accordingly, a semiconductor device having a capacitor, in which a cylindrical storage electrode from an upper surface of which silicon projections are difficult to come off is formed, can be provided.

Abstract: An HSG-Si layer is formed on a wafer under a uniform temperature condition. An apparatus for forming the HSG-Si layer includes a housing forming a process chamber, a first heater on which the wafer is positioned fixed in place at the bottom of the process chamber, a second heater at the top of the process chamber, and a thermal insulator which prevents the heat generated by the first heater from being transferred to the outside of the process chamber. A temperature control system regulates the temperature of the heaters. A method of forming the HSG layer includes steps of placing the wafer on the first heater, using the heaters to remove moisture from the wafer, injecting a source gas of the HSG-Si toward the upper surface of the wafer to form amorphous silicon on the wafer, and annealing the wafer for a predetermined period of time to transform the amorphous silicon into an HSG-Si layer.

Abstract: A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying low temperature silicidation metal to interact to form the self-aligned low temperature metal silicide gate. A precursor having a temporary gate is used to form the self-aligned low temperature silicide gate. The remaining portions of the low temperature silicidation metal is removed by manipulating the etch selectivity between the low temperature silicidation metal and the self-aligned low temperature metal silicide gate.

Abstract: Surface mount device packages with increased mounting strength and a method therefor. In one embodiment, an, electronic device is made up of a device package and one or more electrically conductive terminals. For surface mounting, the device terminals are each provided with a mounting surface which is bonded using a conductive adhesive to a corresponding contact pad on a circuit board. The terminals are further provided with at least one groove across the mounting surface. When conductive adhesive is used to mount the device on a circuit board, this groove serves to form the conductive adhesive into a ridge or “dam” over the contact pad. This provides increased mounting strength which may eliminate the need for additional adhesive material to provide side reinforcement of the device, and thereby allow an increase in the packing density of devices on the circuit board.

Abstract: In one embodiment, the present invention relates to a method of processing a semiconductor substrate, involving the steps of providing the semiconductor substrate having an upper surface; roughening the upper surface of the semiconductor substrate so that the upper surface of the semiconductor substrate has an Rtm of about 10 Å or more; and depositing an ultra-thin photoresist on the upper surface of the semiconductor substrate, the ultra-thin photoresist having a thickness of about 2,000 Å or less.

Abstract: Methods for forming elements having a predetermined shape and for assembling the elements. In one example of a method, each of the elements includes a functional component which is disposed on a first face of a first substrate. A layer representing a first portion of the first substrate at a second face of the first substrate is removed, leaving a second portion of the first substrate on the first substrate. The second portion is etched through a first patterned mask on a surface of the second portion. The plurality of elements is then released from the first substrate. The plurality of elements may then be combined with a fluid to form a slurry. In another example of a method, the first face is etched vertically in regions adjacent to the edges of the plurality of elements, and regions below the first face are etched laterally, and then the plurality of elements are released from the substrate.

Abstract: A thin film capacitor is provided with a thin film protection element to protect the capacitor from damage that can result due to the occurrence of an electrostatic discharge event. The thin film capacitor includes two conductive film portions forming capacitor plates and a dielectric film forming the capacitor dielectric. The protection element may take the form of a thin film diode or a series of thin film diodes connected electrically in parallel with the thin film capacitor. The whole device can be fabricated using a stoichiometric silicon nitride layer to produce the capacitor dielectric and a non-stoichiometric silicon rich silicon nitride layer to provide the diode semiconductor material. One diode is formed by one capacitor plate, the semiconductor layer and an upper diode contact.

Abstract: The invention relates to a method for fabricating a microtechnical structure (28) having a depression (25), which has a high aspect ratio. In order to achieve a good filling behavior, it is proposed to increase the quantity of the passivating particles which are present in the reactor and passivate the surface of the structure (28) against further addition of the filling material (30). With suitable process control, the additional passivation has an effect essentially only on the side walls (27) of the depression (25).

Abstract: In a fabrication method for forming an electrical interconnection of CVD tungsten film, a via hole is formed in a dielectric layer. A lower conductive layer is formed in the via hole and over the dielectric layer. A portion of the lower conductive layer is removed. As a result, the dielectric layer is exposed. An upper conductive layer is formed over the lower conductive layer and over the dielectric layer. The lower conductive layer has a rough surface and the upper conductive layer has a smooth surface. In this manner, following patterning of conductive stripes over the conductive layer, residue is mitigated, and thus, inadvertent interconnection of neighboring stripes is eliminated.

Abstract: A single-substrate-heat-processing method performs a reformation process for a tantalum oxide film on a wafer and a crystallization process for this film in this order. In the reformation process and crystallization process, a heater is set at preset temperatures substantially equal to each other, and a pressure in a process chamber is set at first and second process pressures different from each other. A density of a gas present between a support surface and the wafer is changed by using the pressure in the process chamber as a parameter, and thus a heat transfer rate between the support surface and wafer is changed, thereby setting a wafer temperature at first and second process temperatures different from each other.

Abstract: A method for reducing surface hump phenomena of a doped amorphous silicon layer. A dielectric layer is formed on the device, and subsequently, is patterned to form openings for exposure of the electrode surface of the device. A first deposition step is performed to form a conformal first doped amorphous silicon layer in the opening and on the dielectric layer. A second deposition step is performed to form an undoped or a lightly doped amorphous silicon layer on the first doped amorphous silicon layer and filling the openings completely. A third deposition step is performed to form a second doped amorphous silicon layer on the undoped or a lightly doped amorphous silicon layer.

Abstract: A technique for forming a high surface area electrode or storage node for a capacitor and devices formed thereby, including depositing a first layer of conductive material on a substrate, such that a discontinuous layer is formed. A second conductive material layer is deposited over the discontinuous first conductive material layer, such that the second conductive material layer grows or accumulates on the discontinuous first conductive material layer at a faster rate than on the exposed areas of the substrate in the discontinuous first conductive material layer to form a rough conductive material layer.

Abstract: A process to selectively form silicon structures, such as a storage capacitor, by forming a conductive silicon, forming a silicon nitride layer on the conductive silicon substrate, forming a tungsten layer on the silicon nitride layer, patterning the tungsten layer and the silicon nitride layer to expose a underlying portion of the conductive silicon substrate, forming a continuous silicon film on the exposed portion of the conductive silicon substrate and on an adjacent portion of the silicon nitride layer while completely converting the tungsten layer to a tungsten silicide film by presenting a silicon source gas to the semiconductor memory assembly to form a continuous conductive silicon film used as a first capacitor electrode, forming a capacitor dielectric on the first capacitor electrode and the oxide layer, and forming a second capacitor electrode on the capacitor dielectric.

Abstract: A lower electrode of a capacitor which has uneven surface formed by using HSG-Si (hemispherical grained silicon) and which is used, for example, in a semiconductor device such as DRAM device. Such lower electrode is fabricated as follows. An insulating film is formed on a semiconductor substrate, and a silicon film is formed on the insulating film. Then, the silicon film is selectively patterned to pattern it. The semiconductor substrate is heated to remove moisture in the insulating film. An oxide film on the surface of the silicon film is then removed. Thereafter, silicon nuclei are formed on the surface of the silicon film by heating the semiconductor substrate in atmosphere containing silicon compound gas. The silicon nuclei are then grown and thereby a lower electrode is formed which has hemispherical grains on the surface thereof.

Abstract: This invention relates to a method for manufacturing a semiconductor device having polysilicon lines with micro-roughness on the surface. The micro-rough surface of the polysilicon lines help produce smaller grain size silicide graiicide film during the formation phase to reduce the sheet resistance. The micro-rough surface of the polysilicon lines also increases the effective surface area of the silicide contacting polysilicon lines thereby reduces the overall resistance of the final gate structure after metallization.

Abstract: HSG with an uneven surface is formed by (i) removing a spontaneous oxidation layer formed on an amorphous silicon surface of a semiconductor substrate by preprocessing, (ii) dissociating hydrogen in dangling bonds by heating it to a processing temperature, (iii) forming an amorphous silicon/polysilicon mixed-phase thin film selectively on solely an activated surface of the amorphous silicon surface in a silicon compound atmosphere, and (iv) annealing the film continuously. This method is characterized in including (a) a process which supplies a phosphorus compound and a dilution gas into a reactor while the semiconductor substrate is heated to a processing temperature, and (b) a process of annealing the semiconductor substrate in an atmosphere which contains the phosphorus compound and the dilution gas.

Abstract: An insulating and capping structure of an integrated circuit is formed on a semiconductor wafer. An insulating layer is formed on the semiconductor wafer, and the insulating layer is comprised of a dielectric material having a low dielectric constant that is less than about 4.0 and having chemical bonds that are chemically reactive with a predetermined reactant. A reaction barrier layer is formed on the insulating layer, and the reaction barrier layer is comprised of a material that is not chemically reactive with the predetermined reactant. A capping layer is formed on the reaction barrier layer, and the capping layer is formed using the predetermined reactant.

Abstract: A method and apparatus for selectively depositing hemispherical grained silicon on the surface of a wafer in a process chamber. The chamber is evacuated so that a partial pressure of water vapor in the chamber is less than 10−7 torr, preferably using a turbomolecular pump and a water vapor pump in cooperation. A process gas mixture including silicon is introduced into the chamber. The surface of the wafer is seeded with silicon nuclei, and the wafer is annealed to convert the silicon to HSG.

Abstract: An improved capacitor electrode made of polysilicon having a rough surface on a semiconductor substrate is formed by (a) removing a spontaneous oxidation film adhering to an amorphous silicon surface; (b) heating the amorphous silicon to a designated temperature; (c) spraying SiH4 at a designated temperature on the amorphous silicon to form an amorphous silicon/polysilicon mixed-phase active layer on the surface; (d) annealing at a designated temperature to form an HSG so as to roughen the amorphous silicon surface; (e) PH3-annealing the HSG-forming polysilicon, wherein PH3 is introduced at a designated concentration at the start of heating to a designated temperature; and (f) nitriding the amorphous silicon surface at the stated temperature by continuously introducing NH3 gas instead of PH3.

Abstract: There is formed, so as to cover the upper structure (a gold-containing, low-resistance metal layer) of a T- or Y-shaped gate, a thin film (e.g. a thin TiN film) which is not reactive to the low-resistance metal layer, which is resistant to an etching solution to be applied in a later wet etching step, and which has good adhesivity to a resist to be coated in a later step, to prevent the direct contact of the low-resistance metal layer with the resist. In this state, supports are formed.