Abstract: A gas sensor includes: a gas-sensitive body layer disposed above a substrate and including a metal oxide layer; a first electrode on the gas-sensitive body layer; and a second electrode on the gas-sensitive body layer, being apart from the first electrode by a gap. The gas-sensitive body layer has a resistance change characteristic that reversibly transitions to a high-resistance state and a low-resistance state on basis of a voltage applied across the first electrode and the second electrode. At least a part of the gas-sensitive body layer is exposed to the gap. The gas-sensitive body layer has a resistance that decreases when gas containing a hydrogen atom is in contact with the second electrode.

Abstract: A system and method of using electrochemical additive manufacturing to add interconnection features, such as wafer bumps or pillars, or similar structures like heatsinks, to a plate such as a silicon wafer. The plate may be coupled to a cathode, and material for the features may be deposited onto the plate by transmitting current from an anode array through an electrolyte to the cathode. Position actuators and sensors may control the position and orientation of the plate and the anode array to place features in precise positions. Use of electrochemical additive manufacturing may enable construction of features that cannot be created using current photoresist-based methods. For example, pillars may be taller and more closely spaced, with heights of 200 ?m or more, diameters of 10 ?m or below, and inter-pillar spacing below 20 ?m. Features may also extend horizontally instead of only vertically, enabling routing of interconnections to desired locations.

Abstract: A nitridation treatment method is provided. The nitridation treatment method includes executing a nitridation treatment with respect to a hydrophobic surface defining an interconnect trench to convert the hydrophobic surface to a hydrophilic surface. The nitridation treatment method further includes depositing a seed layer including a conductive material and manganese on the hydrophilic surface. The nitridation treatment method also includes thermally driving all the manganese out of the seed layer to form a diffusion barrier including manganese at the hydrophilic surface. In addition, the nitridation treatment method includes filling remaining space in the interconnect trench with the conductive material to form an interconnect.

Abstract: The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: An RRAM device is provided, which includes a bottom electrode in an oxide layer, a plurality of dielectric protrusions on the oxide layer, wherein the bottom electrode is disposed between the two adjacent dielectric protrusions. A resistive switching layer is conformally disposed on the dielectric protrusions, the oxide layer, and the bottom electrode. A conductive oxygen reservoir layer is disposed on the resistive switching layer, and an oxygen diffusion barrier layer is disposed on the conductive oxygen reservoir layer.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

Abstract: The present application discloses an array substrate and a display panel, the display panel including: a substrate, a gate electrode, a gate insulating layer, a semiconductor layer, a source and a drain electrode, the gate electrode formed on an upper surface of the substrate; the gate insulating layer formed on upper surfaces of the gate electrode and the substrate to cover the gate electrode; the semiconductor layer formed on an upper surface of the gate insulating layer, and disposed above the gate electrode, the semiconductor layer including silicon germanium oxide, and the semiconductor layer including a channel portion; the source electrode formed on surfaces of the gate insulating layer and the semiconductor layer, and disposed on a side of the channel portion; and the drain electrode formed on the surfaces of the gate insulating layer and the semiconductor layer, and disposed on the other side of the channel portion.

Abstract: Embodiments of the disclosure relate to an apparatus and method for annealing one or more semiconductor substrates. In one embodiment, a processing chamber is disclosed. The processing chamber includes a chamber body enclosing an internal volume, a substrate support disposed in the internal volume and configured to support a substrate during processing, a gas panel configured to provide a processing fluid into the internal volume, and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The temperature-controlled fluid circuit includes a gas conduit fluidly coupled to a port on the chamber body at a first end and to the gas panel at a second end.

Abstract: A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.

Abstract: Provided is a crystalline multilayer structure having good semiconductor properties. The crystalline multilayer structure includes a base substrate and a corundum-structured crystalline oxide semiconductor thin film disposed directly on the base substrate or with another layer therebetween. The crystalline oxide semiconductor thin film is 0.1 ?m or less in a surface roughness (Ra).

Abstract: A display device and method of fabricating the same are disclosed. In one aspect, the display device includes a substrate, a black matrix formed over the substrate, and a transparent electrode formed over the substrate. The black matrix and the transparent electrode have first and second areas, respectively. The sum of the first and second areas is substantially equal to the surface area of the substrate.

Abstract: A method for manufacturing a printed wiring board includes forming a through hole in an insulating substrate such that the hole extends from first surface of the substrate to second surface of the substrate on the opposite side, forming a seed layer on the first and second surfaces and wall of the hole, and applying pulse plating to the substrate via the seed layer such that a through-hole conductor is formed in the hole. The applying of the pulse plating includes flowing forward and reverse current on the first and second surfaces of the substrate such that when the forward current flows on the first surface of the substrate, the reverse current flows on the second surface of the substrate and that when the reverse current flows on the first surface of the substrate, the forward current flows on the second surface of the substrate.

Abstract: A reflective original includes: a reflection layer which has a multilayer film configured to reflect extreme ultraviolet light; a base material configured to support the reflection layer; and a thermal diffusion layer interposed between the reflection layer and the base material, and configured to diffuse heat of the reflection layer. A heat capacity, per unit area, of a structure constituted by both the reflection layer and the thermal diffusion layer is not lower than 1.1 (J/(K·m2)).

Abstract: In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on an opposite second major surface. The semiconductor chip is configured to regulate flow of a current from the first contact region to the second contact region. An encapsulant is disposed at the semiconductor chip. A first contact plug is disposed within the encapsulant and coupled to the first contact region. A second side conductive layer is disposed under the second major surface and coupled to the second contact region. A through via is disposed within the encapsulant and coupled to the second side conductive layer. The first contact plug and the through via form terminals above the first major surface for contacting the semiconductor package.

Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.

Abstract: Provided is a plating method of a circuit substrate comprising a conductive pattern in which a metal layer containing at least silver and copper is exposed on an outer surface. The plating method comprises: step (A) of treating the circuit substrate with a first liquid agent containing an oxidizing agent; step (B) of treating the circuit substrate after the step (A) with a second liquid agent which dissolves copper oxide, and thereby removing copper oxide from the conductive pattern's surface; step (C) of treating the circuit substrate after the step (B) with a third liquid agent whose rate of dissolving silver oxide (I) at 25° C. is 1000 times or more faster than its rate of dissolving copper (0) at 25° C., and thereby removing silver oxide from the conductive pattern's surface; and step (D) of performing electroless plating on the conductive pattern of the circuit substrate after the step (C).

Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.

Abstract: A method of patterning a platinum layer includes the following steps. A substrate is provided. A platinum layer is formed on the substrate. An etching process is performed to pattern the platinum layer, wherein an etchant used in the etching process simultaneously includes at least a chloride-containing gas and at least a fluoride-containing gas.

Abstract: According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.

Abstract: A method of forming a metal layer on an electrically insulating substrate comprises depositing a photocatalyst layer onto the substrate and depositing a mask layer comprising voids on the substrate, such as a layer of latex microparticles with voids between them, to give an open pore structure to the mask. An electroless plating solution is then provided on the photocatalyst layer, and the photocatalyst layer and electroless plating solution are illuminated with actinic radiation whereby deposition of metal from the electroless plating solution to form a metal layer on the photocatalyst layer is initiated whereby the metal deposits in the voids of the mask layer. The mask layer is subsequently removed to leave a porous metal layer on the substrate. The method allows for deposition of porous metal films with controlled thickness and excellent adhesion onto electrically insulating substrates. The method is suitable for providing metal layers with controlled, regular porosity.

Abstract: A nitride-based semiconductor device of the present invention includes: a nitride-based semiconductor multilayer structure 20 which includes a p-type semiconductor region with a surface 12 being inclined from the m-plane by an angle of not less than 1° and not more than 5°; and an electrode 30 provided on the p-type semiconductor region. The p-type semiconductor region is formed by an AlxInyGazN (where x+y+z=1, x?0, y?0, and z?0) layer 26. The electrode 30 includes a Mg layer 32 and an Ag layer 34 provided on the Mg layer 32. The Mg layer 32 is in contact with the surface 12 of the p-type semiconductor region of the semiconductor multilayer structure 20.

Abstract: Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.

Abstract: A method for forming a noble metal layer by Plasma Enhanced Atomic Layer Deposition (PE-ALD) is disclosed. The method includes providing a substrate in a PE-ALD chamber, the substrate comprising a first region having an exposed first material and a second region having an exposed second material. The first material comprises a metal nitride or a nitridable metal, and the second material comprises a non-nitridable metal or silicon oxide. The method further includes depositing selectively by PE-ALD a noble metal layer on the second region and not on the first region, by repeatedly performing a deposition cycle including (a) supplying a noble metal precursor to the PE-ALD chamber and contacting the noble metal precursor with the substrate in the presence of a carrier gas followed by purging the noble metal precursor, and (b) exposing the substrate to plasma while supplying ammonia and the carrier gas into the PE-ALD chamber.

Abstract: Nanoparticles may be formed on a substrate by mixing precursor solutions deposited by an inkjet printer. A first solution is deposited on a substrate from a first inkjet print cartridge. Then, a second solution is deposited on the substrate from a second inkjet print cartridge. The solutions may be printed in an array of droplets on the substrate. Nanoparticles form when droplets of the first solution overlap with droplets of the second solution. In one example, the nanoparticles may be gold nanoparticles formed from mixing a first solution of 1,2-dichlorobenzene (DCB) and oleylamine and a second solution of gold chloride trihydrite and dimethyl sulfoxide (DMSO). The nanoparticles may be incorporated into optoelectronic devices.

Abstract: Methods of forming an integrated circuit structure utilizing a selectively formed and at least partially oxidized metal cap over a gate, and associated structures. In one embodiment, a method includes providing a precursor structure including a transistor having a metal gate; forming an etch stop layer over an exposed portion of the metal gate; at least partially oxidizing the etch stop layer; and forming a dielectric layer over the at least partially oxidized etch stop layer.

Abstract: Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an aperture in a substrate material, disposing a conductive material on the substrate material and in the aperture, and disposing a fill material on the conductive material. The fill material at least partially fills the aperture. The substrate material is then polished to remove at least a portion of the conductive material and the fill material external to the aperture during which the fill material substantially prevents the conductive material from smearing into the aperture during polishing the substrate material.

Abstract: A thin film resistor structure includes a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD; a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD.

Abstract: Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage amount deposited in each trench is greater than the coverage amount deposited in each via.

Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: The present invention provides a current blocking structure for electronic devices, preferably optoelectronic devices. The current blocking structure comprises a semiconductor material arrangement comprising an n-type ruthenium doped indium phosphide (Ru—InP) layer and a first p-type semiconductor material layer wherein the n-type Ru—InP layer is less than 0.6 ?m thick. The semiconductor material arrangement and p-type semiconductor material layer form a current blocking p-n junction. The current blocking structure may further comprise other n-type layers and/or multiple n-type Ru—InP layers and/or intrinsic/undoped layers wherein the n-type Ru—InP layers may be thicker than 0.6 ?m.

Abstract: Dielectric materials having implanted metal sites and methods of their fabrication have been described. Such materials are suitable for use as charge-trapping nodes of non-volatile memory cells for memory devices. By incorporating metal sites into dielectric charge-trapping materials using an ammonia plasma and a metal source in contact with the plasma, improved programming and erase voltages may be facilitated.

Abstract: Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO3 in an SWC tool. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer by applying HNO3 to the annealed Ni/Pt layer in an SWC tool, annealing the Ni removed Ni/Pt layer, and removing unreacted Pt from the annealed Ni removed Ni/Pt layer. Embodiments include forming first and second gate electrodes on a substrate, spacers on opposite sides of each gate electrode, and Pt-containing NiSi on the substrate adjacent each spacer, etching back the spacers, forming a tensile strain layer over the first gate electrode, applying a first HNO3 in an SWC tool, forming a compressive strain layer over the second gate electrode, and applying a second HNO3 in an SWC tool.

Abstract: A method for forming gold nanowires on a substrate is provided. The method includes a) attaching noble metal nanoparticles onto the substrate; and b) contacting the noble metal nanoparticles with an aqueous solution comprising a ligand, gold ions and a reducing agent, wherein the ligand is an organic compound having a thiol group. Gold nanowires formed by a method according to the method, and an electronic device comprising the gold nanowires are also provided.

Abstract: A tantalum nitride film rich in tantalum atoms is formed by simultaneously introducing a raw gas consisting of a coordination compound of elemental tantalum (Ta) having a coordinated ligand of formula: N?(R, R?) (wherein, R and R? each represents an alkyl group having 1 to 6 carbon atoms) and NH3 gas into a film-forming chamber; reacting the raw gas with the NH3 gas; forming a reduced compound having Ta—NH3 on a substrate; and introducing a hydrogen atom-containing gas into the chamber to form a tantalum nitride film rich in tantalum atoms. The resulting tantalum nitride film has a low resistance, low contents of C and N atoms, and a high compositional ratio: Ta/N, show sufficiently high adherence to Cu film and can thus be useful as a barrier film. Moreover, tantalum particles are implanted in the resulting film according to the sputtering technique to further enrich the film with tantalum.

Abstract: A method of forming a memory device. A first thickness of dielectric material overlies a surface region of a substrate. A first wiring material including a first lining material and a silver material are formed overlying the dielectric material. A first adhesion material and an amorphous silicon switching material including a contact material are deposited overlying the first wiring material. The method forms one or more first structures configured to spatially extend in a first direction from the amorphous silicon switching material, the contact material, and the first wiring material. A thickness of second dielectric material is deposited overlying the one or more first structures. The method forms a second wiring structure comprising at least a second silver material and a second lining material spatially extending in a second direction orthogonal to the first direction overlying the second dielectric material and in electrical contact with the switching material.

Abstract: A semiconductor die that includes a plurality of non-metallic slots that extend through a current routing line is disclosed. The semiconductor die comprises a semiconductor circuit that includes a plurality of semiconductor components and a current trace line that is coupled to a first semiconductor component. Further, the semiconductor die comprises a current routing line that is coupled with the current trace line. The current routing line includes a plurality of non-metallic slots that extend through the current routing line.

Abstract: A method includes providing a silicon-containing die and providing a heat sink having a palladium layer over a first surface of the heat sink. A first gold layer is located over one of a first surface of the die or the palladium layer. The silicon-containing die is bonded to the heat sink, where bonding includes joining the silicon-containing die and the heat sink such that the first gold layer and the palladium layer are between the first surface of the silicon-containing die and the first surface of the heat sink, and heating the first gold layer and the palladium layer to form a die attach layer between the first surface of the silicon-containing die and the first surface of the heat sink, the die attach layer comprising a gold interface layer having a plurality of intermetallic precipitates, each of the plurality of intermetallic precipitates comprising palladium, gold, and silicon.

Abstract: There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.

Abstract: Embodiments of the invention may provide a method of printing one or more print tracks on a print support, or substrate, comprising two or more printing steps in each of which a layer of material is deposited on the print support according to a predetermined print profile. In each printing step, subsequent to the first step, each layer of material is deposited at least partially on top of the layer of material printed in the preceding printing step, so that each layer of printed material has an identical or different print profile with respect to at least a layer of material underneath. The method may further comprise depositing material in each printing step that is equivalent to or different from the material deposited in at least one of other the print layers.

Abstract: A method of cleaning an inside of a processing chamber is provided according to an embodiment of the present disclosure. The method includes supplying a fluorine-based gas and a nitrogen oxide-based gas as the cleaning gas, into the processing chamber heated to a first temperature, and removing a deposit by a thermochemical reaction. The method further includes changing a temperature in the processing chamber to a second temperature higher than the first temperature, and supplying the fluorine-based gas and the nitrogen oxide-based gas as the cleaning gas, and removing extraneous materials, remaining on the surface of the member in the processing chamber, by a thermochemical reaction.

Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.

Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration and stress migration in bulk Cu metal. In one embodiment, the method includes providing a patterned substrate containing Cu metal surfaces and dielectric layer surfaces, exposing the patterned substrate to a process gas comprising a metal-containing precursor, and irradiating the patterned substrate with electromagnetic radiation, where selective metal-containing cap layer formation on the Cu metal surfaces is facilitated by the electromagnetic radiation. In some embodiments, the method further includes pre-treating the patterned substrate with additional electromagnetic radiation and optionally a cleaning gas prior to forming the metal-containing cap layer.

Abstract: A metallic liner stack including at least a Group VIIIB element layer and a CuMn alloy layer is deposited within a trench in a dielectric layer. Copper is deposited on the metallic liner stack and planarized to form a conductive interconnect structure, which can be a metal line, a metal via, or a combination thereof. The deposited copper and the metallic liner stack are annealed before or after planarization. The Mn atoms are gettered by the Group VIIIB element layer to form a metallic alloy liner including Mn and at least one of Group VIIIB elements. Mn within the metallic alloy liner combines with oxygen during the anneal to form MnO, which acts as a strong barrier to oxygen diffusion, thereby enhancing the reliability of the conductive interconnect structure.

Abstract: A photovoltaic cell such as a solar cell is disclosed. The cell comprises (a) a semiconductor substrate having a front surface, (b) one or more anti-reflection coating layers on the front surface of the semiconductor substrate, (c) a plurality of silver-containing fingers in contact with the one or more anti-reflection coating layers and in electrical contact with the semiconductor substrate; and (d) one or more base metal containing buss bars each in contact with the one or more anti-reflection coating layers and the silver-containing fingers. The base metal may be selected from one or more of copper, nickel, lead, tin, iron, indium, zinc, bismuth and cobalt. Methods for making protovoltaic cells with base metal containing buss bars are also disclosed.

Abstract: The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process, comprising using an aqua regia cleaning solution (comprising a mixture of nitric acid and hydrochloric acid) with microwave assisted heating. Low boiling temperature of hydrochloric acid prevents heating the aqua regia solution to a high temperature, impeding the effectiveness of post silicidation nickel and platinum residue removal. Therefore, embodiments of the invention provide a microwave assisted heating of the substrate in an aqua regia solution, selectively heating platinum residues without significantly increasing the temperature of the aqua regia solution, rendering platinum residues to be more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

Abstract: A method of manufacturing an optical semiconductor device includes: forming first and second optical semiconductor elements separated from each other by a separation groove on a semiconductor substrate; forming first and second electrodes containing Pt on top surfaces of the first and second optical semiconductor elements, respectively; forming a third electrode electrically connected to the first and second electrodes and preventing the third electrode from being formed in the separation groove; forming first and second Au plated layers on the first and second electrodes, respectively, by electrolytic plating, using the third electrode as a power supply layer; forming a resist covering the first and second Au plated layers by photolithography; and etching the third electrode, using the resist as a mask, to electrically separate the first electrode from the second electrode.

Abstract: In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region.

Abstract: A method for producing a nanoporous layer comprises applying a plating base with adhesion strengthening onto a substrate, depositing a layer made of gold and silver onto the substrate, the composition being in the range of 20% to 40% gold and 80% to 60% silver, and selectively removing the silver in order to produce a nanoporous gold layer.

Abstract: Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices. In one example, the method includes forming a trench/via in a layer of insulating material, performing a deposition process to form an as-deposited copper-based seed layer above the layer of insulating material in the trench/via, wherein the copper-based seed layer has a first portion that is positioned above a bottom of the trench/via that is thicker than second portions of the copper seed layer that are positioned above sidewalls of the trench/via, performing an etching process on the as-deposited copper-based seed layer to substantially remove portions of the second portions of the as-deposited copper-based seed layer and performing an electroless deposition process to fill the trench/via with a copper-based material.