Abstract: The present disclosure provides various methods for removing an anti-stiction layer. An exemplary method includes forming an anti-stiction layer over a substrate, including over a first substrate region of a first material and a second substrate region of a second material, wherein the second material is different than the first material; and selectively removing the anti-stiction layer from the second substrate region of the second material without using a mask.

Abstract: A light emitting device having auto-cloning photonic crystal structures comprises a substrate, a first semiconductor layer, an active emitting layer, a second semiconductor layer and a saw-toothed multilayer film comprising auto-cloning photonic crystal structures. The saw-toothed multilayer film provides a high reflection interface and a diffraction mechanism to prevent total internal reflection and enhance light extraction efficiency.

Abstract: A light emitting device having auto-cloning photonic crystal structures comprises a substrate, a first semiconductor layer, an active emitting layer, a second semiconductor layer and a saw-toothed multilayer film comprising auto-cloning photonic crystal structures. The saw-toothed multilayer film provides a high reflection interface and a diffraction mechanism to prevent total internal reflection and enhance light extraction efficiency. The manufacturing method of the light emitting device having auto-cloning photonic crystal structures is presented here.

Abstract: A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features.

Abstract: A method of treating the surface of a semiconductor wafer through the formation of a bonding system is provided in order to enhance the handling of the wafer during subsequent processing operations. The method generally comprises the steps of applying a release layer and an adhesive to different wafers; bonding the wafers together to form a bonded wafer system; performing at least one wafer processing operation (e.g., wafer grinding, etc.) to form a thin processed wafer; debonding the wafers; and then cleaning the surface of the processed wafer with an organic solvent that is capable of dissolving the release layer or any residue thereof. The adhesive includes a vinyl-functionalized polysiloxane oligomeric resin, a Si—H functional polysiloxane oligomeric resin, a catalyst, and optionally an inhibitor, while the release layer is comprised of either a silsesquioxane-based resin or a thermoplastic resin.

Abstract: Provided is a coating method of an alignment film, including: providing a board, having a substrate, the substrate forming an alignment liquid coating area thereon; forming a barrier structure around the alignment liquid coating area; coating an alignment liquid in the alignment liquid coating area, wherein the barrier structure blocks the alignment liquid to diffuse outside the alignment liquid coating area; and curing the alignment liquid to form an alignment film. The present invention may assure that the formed alignment film can not affect other areas adjacent to the alignment liquid coating area.

Abstract: A polyimide film is effectively formed on a complicated surface. The polyimide film is formed by reacting, on the surface, diamine monomer and tetracarboxylic acid dianhydride monomer both of which are dissolved within carbon dioxide in a supercritical states, together with a polyamic acid resulting from a reaction between the diamine monomer and the tetracarboxylic acid dianhydride reached to the surface.

Abstract: A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The stabilizing solution comprises a non-volatile component, such as non-volatile particles or polymers, which is applied after the photoresist material has been developed. By treating the photoresist with the solution containing a non-volatile component after developing but before drying, the non-volatile component fills the space between adjacent resist patterns and remains on the substrate during drying. The non-volatile component provides structural and mechanical support for the resist to prevent deformation or collapse by liquid surface tension forces.

Abstract: A multi-step system and method for curing a dielectric film in which the system includes a drying system configured to reduce the amount of contaminants, such as moisture, in the dielectric film. The system further includes a curing system coupled to the drying system, and configured to treat the dielectric film with ultraviolet (UV) radiation and infrared (IR) radiation in order to cure the dielectric film.

Abstract: Embodiments of the present invention provide a vapor phase organic polymer film deposited using a CVD process at low temperature during a process sequence for wafer-level chip scale packaging (WL-CSP), including system-in package (SiP), Package-on-Package (PoP) and Package-in-Package (PiP).

Abstract: In one embodiment, a method for forming an electronic device includes providing a substrate having a plurality of electronic devices formed therein, forming a protective layer over a major surface of the substrate containing the plurality of electronic devices, forming a mold layer over the protective layer, thinning a major surface of the substrate opposite to the major surface containing the plurality of electronic devices, and removing the adhesive layer and the mold layer. In another embodiment, a zone coating layer can be included between the protective layer and the mold layer.

Abstract: An exhausting method includes determining an exhaust flow rate of a process gas to be a predetermined value that is less than or equal to a gas flow rate corresponding to a maximum process capability of a purification system when the process gas is diluted to a lower explosive limit; calculating a pressure drop amount per unit time to maintain the determined exhaust flow rate of the process gas, based on a relation between the exhaust flow rate and the pressure drop amount per unit time; and evacuating an inside of the chamber to maintain the determined exhaust flow rate, while controlling the pressure through an automatic pressure control valve by setting a target pressure value to be updated as a control value of the automatic pressure control valve at every predetermined time interval so as to achieve a calculated pressure drop amount per unit time.

Abstract: The present invention relates to a method and apparatus for the synthesis of nanostructures using at least one solution providing at least one chemical element appropriate for the type of nanostructure, the method comprising the steps of: a) adding (admixing) a reducing agent to the at least one solution, b) bringing a suitable substrate into contact with the at least one solution before or after step a), c) forming nucleation growth sites on the substrate and d) maintaining the temperature at a suitable level for the growth of the nanostructures, characterized by the further steps of e) providing at least one space having at least one dimension in the micron range, e.g. in the range from 1 ?m to 500 ?m, adjacent a surface of the substrate, f) growing said nanostructures in said at least one space, g) periodically separating said nanostructures from the substrate and removing them.

Abstract: A method for spalling local areas of a base substrate utilizing at least one stressor layer portion which is located on a portion, but not all, of an uppermost surface of a base substrate. The method includes providing a base substrate having a uniform thickness and a planar uppermost surface spanning across an entirety of the base substrate. At least one stressor layer portion having a shape is formed on at least a portion, but not all, of the uppermost surface of the base substrate. Spalling is performed which removes a material layer portion from the base substrate and provides a remaining base substrate portion. The material layer portion has the shape of the at least one stressor layer portion, while the remaining base substrate portion has at least one opening located therein which correlates to the shape of the at least one stressor layer.

Abstract: The generation of surface patterns or the replication of surface patterns is achieved in the present disclosure without the need to employ an etching process. Instead, a unique fracture mode referred to as spalling is used in the present disclosure to generate or replicate surface patterns. In the case of surface pattern generation, a surface pattern is provided in a stressor layer and then spalling is performed. In the case of surface pattern replication, a surface pattern is formed within or on a surface of a base substrate, and then a stressor layer is applied. After applying the stressor layer, spalling is performed. Generation or replication of surface patterns utilizing spalling provides a low cost means for generation or replication of surface patterns.

Abstract: Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce.

Abstract: The present invention provided is the temporary adhesive for wafer processing which temporarily bonds a wafer having a circuit face on the front surface and a processing face on the back surface to a support, and includes a first temporary adhesive layer which is a layer (A) of a thermoplastic resin modified organopolysiloxane obtained by partial dehydration condensation of an organopolysiloxane resin containing a R21R22R23SiO1/2, and a SiO4/2 unit in a molar ratio of R21R22R23SiO1/2 unit/SiO4/2 unit of 0.6 to 1.7 and an organopolysiloxane represented by the following general formula (1), and a second temporary adhesive layer which is a thermosetting modified siloxane polymer layer (B) which is laminated on the first temporary adhesive layer and is releasably bonded to the support.

Abstract: A masking film (13) is formed so as to have an opening in a display region (R1) (luminescent region) and a sealing region. Subsequently, luminescent layers (8R, 8G, and 8B) having a stripe pattern are formed. Then, the masking film (13) is peeled off, so that the luminescent layers (8R, 8G, and 8B) patterned with high resolution are provided.

Abstract: A method for etching with a laser beam having a predetermined wavelength an area of a layer of a first material, said area being deposited at the surface of at least two second materials, includes: depositing a layer of a third material on the layer of the first material, the first and the third materials having a chemical affinity on application of the laser beam greater than the chemical affinity during said application between the first material and each of said at least two second materials; and applying the laser beam to an area of a free surface of the layer of third material vertically above the area of the layer of first material with a fluence of said laser beam causing the separation of said area.

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during formation of a capping layer on electrically conductive regions that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; capping layer material formed over the dielectric region can be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Abstract: On a surface of a substrate (3) on which surface a vapor-deposited film is to be formed, a photoresist (13) is formed so as to have an opening in a sealing region including a display region (R1) which sealing region is formed by a sealing resin (11) of a frame shape. Then, luminescent layers (8R, 8G, and 8B) having a striped pattern are formed. Subsequently, the photoresist (13) is removed with the use of an exfoliative solution so as to form the luminescent layers (8R, 8G, and 8B) patterned with high definition.

Abstract: A manufacturing method of a semiconductor device of which cost can be suppressed by using a nanoimprinting method is provided. In the invention, a gate insulating film, a conductive film, and a resist are formed in sequence over a semiconductor film and a resist is hardened while pressing a mold formed with a pattern to the resist. Therefore, the pattern is transferred to the resist, the surface of the resist to which the pattern is transferred is ashed until a part of the conductive film is exposed, the resist having the ashed surface is used a mask, and the conductive film is etched.

Abstract: It is an object of the present invention to provide a method of separating a thin film transistor, and circuit or a semiconductor device including the thin film transistor from a substrate by a method different from that disclosed in the patent document 1 and transposing the thin film transistor, and the circuit or the semiconductor device to a substrate having flexibility. According to the present invention, a large opening or a plurality of openings is formed at an insulating film, a conductive film connected to a thin film transistor is formed at the opening, and a peeling layer is removed, then, a layer having the thin film transistor is transposed to a substrate provided with a conductive film or the like. A thin film transistor according to the present invention has a semiconductor film which is crystallized by laser irradiation and prevents a peeling layer from exposing at laser irradiation not to be irradiated with laser light.

Abstract: Water-soluble electrically conductive polymers and a composition comprising such polymers are provided. Also, an electrically conductive layer or film formed from the composition, and articles comprising the electrically conductive layer or film are provided. The electrically conductive polymers according to the present disclosure have one or more hydrophilic side chains. Hydrophilic side chains are covalently bonded to the conductive polymers, which allow the polymer to be stable at high temperature. Thus, the stability of electrical conductivity is prolonged. Depending on the concentration of hydrophilic side chains, the conductivity may be changed. The hydrophilic side chains provide a successful way to fabricate a ductile film exhibiting tunable conductivity. Furthermore, high levels of surface-resistance uniformity can be achieved in the field of coating technology that uses eco-friendly water-based solvents to uniformly and quickly coat the conductive polymer on to plastic film surfaces.

Abstract: A method for preparing a semiconductor with preapplied underfill comprises providing a semiconductor wafer with a plurality of metallic bumps on its top side and, optionally, through-silica-vias vertically through the silicon wafer; laminating a back grinding tape to the top of the wafer covering the metallic bumps and through silicon vias; thinning the back side of the wafer; mounting a dicing tape to the back side of the thinned wafer and mounting the silicon wafer and dicing tape to a dicing frame; removing the back grinding tape; providing an underfill material precut into the shape of the wafer; aligning the underfill on with the wafer and laminating the underfill to the wafer.

Abstract: The present invention provides a temporary carrier bonding and detaching process. A first surface of a semiconductor wafer is mounted on a first carrier by a first adhesive, and a first isolation coating is disposed between the first adhesive and the first carrier. Then, a second carrier is mounted on the second surface of the semiconductor wafer. The first carrier is detached. The method of the present invention utilizes the second carrier to support and protect the semiconductor wafer, after which the first carrier is detached. Therefore, the semiconductor wafer will not be damaged or broken, thereby improving the yield rate of the semiconductor process. Furthermore, the simplicity of the detaching method for the first carrier allows for improvement in efficiency of the semiconductor process.

Abstract: A method is provided for forming FinFETS with improved alignment features. Embodiments include forming on a Si substrate pillars of TEOS on poly-Si; conformally depositing a first TEOS liner over the entire substrate; etching the first TEOS liner and substrate through the pillars, forming first trenches; filling the first trenches and spaces between the pillars with an oxide; removing the TEOS from the pillars and the oxide therebetween; removing the poly-Si; conformally depositing a second TEOS liner over the entire Si substrate; etching the second TEOS liner and Si between the oxide, forming second trenches having a larger depth than the first trenches; filling the second trenches with oxide; removing the oxide and the first and second TEOS liners down to an upper surface of the Si substrate; and recessing the oxide below the upper surface of the Si substrate.

Abstract: An underlayer coating is used as an underlayer of photoresists in lithography process of the manufacture of semiconductor devices and has a high dry etching rate in comparison to the photoresists, does not intermix with the photoresists, and is capable of flattening the surface of a semiconductor substrate having holes of a high aspect ratio; and an underlayer coating forming composition can form the underlayer coating. The underlayer coating forming composition for forming by light irradiation an underlayer coating used as an underlayer of a photoresist in a lithography process of the manufacture of semiconductor devices, includes a polymerizable substance and a photopolymerization initiator.

Abstract: A substrate processing apparatus includes a processing chamber configured to process a substrate, a substrate support member provided within the processing chamber to support the substrate, a microwave generator provided outside the processing chamber, a waveguide launch port configured to supply a microwave generated by the microwave generator into the processing chamber, wherein the central position of the waveguide launch port is deviated from the central position of the substrate supported on the substrate support member and the waveguide launch port faces a portion of a front surface of the substrate supported on the substrate support member, and a control unit configured to change a relative position of the substrate support member in a horizontal direction with respect to the waveguide launch port.

Abstract: A light emitting device having auto-cloning photonic crystal structures comprises a substrate, a first semiconductor layer, an active emitting layer, a second semiconductor layer and a saw-toothed multilayer film comprising auto-cloning photonic crystal structures. The saw-toothed multilayer film provides a high reflection interface and a diffraction mechanism to prevent total internal reflection and enhance light extraction efficiency. The manufacturing methods of the light emitting device having auto-cloning photonic crystal structures are also presented.

Abstract: A through-silicon via and a method for forming the same are provided. The method includes: providing a semiconductor substrate, the semiconductor substrate including an upper surface and an opposite lower surface; etching the upper surface of the semiconductor substrate to form an opening; filling the opening with a conductive material to form a first nail; etching the lower surface of the semiconductor substrate to form a recess, such that the first nail is exposed at a bottom of the recess; filling the recess with a conductive material that can be etched, and etching the conductive material that can be etched to form a second nail, such that the second nail is vertically connected with the first nail; and filling a gap between the second nail and the semiconductor substrate and a gap between the second nail and an adjacent second nail with a dielectric layer. Then invention can improve the reliability of through-silicon vias and avoid voids.

Abstract: A method for manufacturing a semiconductor device, includes: a step of etching a Si (111) substrate along a (111) plane of the Si (111) substrate to separate a Si (111) thin-film device having a separated surface along the (111) plane.

Abstract: Some embodiments discussed relates to an apparatus for holding a substrate, comprising a body with a surface for a semiconductor wafer to rest on, with the surface having a first surface area on which a first area of the semiconductor wafer can rest, and a second surface area on which a second area of the semiconductor wafer can rest, wherein the second surface area protrudes with respect to the first surface area.

Abstract: A method and apparatus for preparing thin TEM samples in a manner that reduces or prevents bending and curtaining is realized. Embodiments of the present invention deposit material onto the face of a TEM sample during the process of preparing the sample. In some embodiments, the material can be deposited on a sample face that has already been thinned before the opposite face is thinned, which can serve to reinforce the structural integrity of the sample and refill areas that have been over-thinned due to a curtaining phenomena. In other embodiments, material can also be deposited onto the face being milled, which can serve to reduce or eliminate curtaining on the sample face.

Abstract: The back side of a wafer having a plurality of devices formed on the front side thereof is ground to thereby reduce the thickness of the wafer. A resin layer is formed on the front side of the wafer and is cured. The resin layer is planarized while the back side of the wafer is held on a chuck table and the resin layer formed on the front side of the wafer is exposed. The resin layer is bonded to a hard plate through a bonding member, and the back side of the wafer is ground by using a grinding unit of a grinding apparatus to thereby reduce the thickness of the wafer to a predetermined thickness while the hard plate bonded to the wafer is held on a chuck table of the grinding apparatus.

Abstract: A method for operating one or more electronic device manufacturing systems is provided, including the steps 1) performing a series of electronic device manufacturing process steps with a process tool, wherein the process tool produces effluent as a byproduct of performing the series of process steps; 2) abating the effluent with an abatement tool; 3) supplying an abatement resource to the abatement tool from a first abatement resource supply; 4) changing an abatement resource supply from the first abatement resource supply to a second abatement resource supply, wherein changing the abatement resource supply comprises: i) interrupting a flow of the abatement resource from the first abatement resource supply; and ii) beginning a flow of the abatement resource from the second abatement resource supply; and 5) continuing to perform the series of process steps with the process tool, while changing, and after changing, the abatement resource supply.

Abstract: Provided is a method of post treating graphene including providing graphene on a metal thin film, providing a carrier on the graphene, hardening the carrier, and removing the metal thin film from the graphene.

Abstract: A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance with a scan pitch that is based on a pitch of conductive structure segments to be formed on the substrate. The beam of energy is defined to transform the mask material upon which the beam of energy is incident into a removable state. During scanning the beam of energy across the mask material, the beam of energy is turned on at locations where a conductive structure is to be formed on the substrate, and the beam of energy is turned off at locations where a conductive structure is not to be formed on the substrate.

Abstract: An evaporation donor substrate which enables only a desired evaporation material to be evaporated at the time of deposition by an evaporation method, and capable of reduction in manufacturing cost by increase in use efficiency of the evaporation material and deposition with high uniformity. An evaporation donor substrate capable of controlling laser light so that a desired position of an evaporation donor substrate is irradiated with the laser light in accordance with the wavelength of the emitted laser light at the time of evaporation. Specifically, an evaporation donor substrate in which a region which reflects laser light and a region which absorbs laser light at the time of irradiation with laser light having a wavelength of greater than or equal to 400 nm and less than or equal to 600 nm at the time of evaporation are formed.

Abstract: A polishing liquid composition includes composite oxide particles containing cerium and zirconium, a dispersing agent, and an aqueous medium. A powder X-ray diffraction spectrum of the composite oxide particles obtained by CuK?1 ray (?=0.154050 nm) irradiation includes a peak (first peak) having a peak top in a diffraction angle 2? (? is a Bragg angle) range of 28.61 to 29.67°, a peak (second peak) having a peak top in a diffraction angle 2? range of 33.14 to 34.53°, a peak (third peak) having a peak top in a diffraction angle 2? range of 47.57 to 49.63°, and a peak (fourth peak) having a peak top in a diffraction angle 2? range of 56.45 to 58.91°. A half-width of the first peak is 0.8° or less.

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during formation of a capping layer on electrically conductive regions that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; capping layer material formed over the dielectric region can be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Abstract: A conductive film containing aluminum or an aluminum alloy with a thickness equal to or greater than 1 ?m and equal to or less than 10 ?m is etched by wet-etching to be a predetermined thickness, and then etched by dry-etching, whereby side-etching of the conductive film can be suppressed and thickness reduction of a mask can be suppressed. The suppression of side-etching of the conductive film and the suppression of thickness reduction of the mask enable a conductive film containing aluminum or an aluminum alloy even with a large thickness equal to or greater than 1 ?m and equal to or less than 10 ?m to be etched such that the gradient of the edge portion of the conductive film can be steep, a predetermined thickness of the conductive film can be obtained, and shape difference from a mask pattern can be suppressed.

Abstract: Adaptive imprint planarization provides a surface having desired shape characteristics. Generally, topography of a first surface is mapped to provide a density map. The density map is evaluated to provide a drop pattern for dispensing polymerizable material on the first surface. The polymerizable material is solidified and etched to provide a second surface having the desired shape characteristics. Additionally, adaptive imprint planarization compensates for parasitic effects of the imprinting process.

Abstract: The invention includes methods of forming material on a substrate and methods of forming a field effect transistor gate oxide. In one implementation, a first species monolayer is chemisorbed onto a substrate within a chamber from a gaseous first precursor. The first species monolayer is discontinuously formed over the substrate. The substrate having the discontinuous first species monolayer is exposed to a gaseous second precursor different from the first precursor effective to react with the first species to form a second species monolayer, and effective to form a reaction product of the second precursor with substrate material not covered by the first species monolayer. The substrate having the second species monolayer and the reaction product is exposed to a third gaseous substance different from the first and second precursors effective to selectively remove the reaction product from the substrate relative to the second species monolayer. Other implementations are contemplated.

Abstract: A structure making up a part of a semiconductor device, such as a fin structure of a finFET device, is formed on and electrically isolated from a semiconductor substrate. The structure is comprised of the semiconductor substrate material and is electrically isolated from a remaining portion of the semiconductor substrate by an insulating barrier. The insulating barrier is formed by an isotropic oxidation process that oxidizes portions of the semiconductor substrate that are not protected by an oxidation barrier.

Abstract: In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to a surface of the first layer, where the filling material includes a polymer and at least one additive, where the at least one additive includes at least one of a surfactant, a high molecular weight polymer and a solvent; and after applying the filling material, heating the structure to enable the filling material to at least partially fill the plurality of pores uniformly across an area of the first layer, where heating the structure results in residual filling material being uniformly left on the surface of the first layer.

Abstract: A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers.

Abstract: A substrate with a vent for a semiconductor device where the vent is integrated within the substrate itself. The integrated air vent forms a passageway or relief path for gas or air within a mold cavity to escape during a transfer molding packaging process. The vents integrated in the substrate reduce trapped gas and mold voids and limit vent flash to improve yield.

Abstract: Methods of growing and manufacturing aluminum nitride crystal, and aluminum nitride crystal produced by the methods. Preventing sublimation of the starting substrate allows aluminum nitride crystal of excellent crystallinity to be grown at improved growth rates. The aluminum nitride crystal growth method includes the following steps. Initially, a laminar baseplate is prepared, furnished with a starting substrate having a major surface and a back side, a first layer formed on the back side, and a second layer formed on the first layer. Aluminum nitride crystal is then grown onto the major surface of the starting substrate by vapor deposition. The first layer is made of a substance that at the temperatures at which the aluminum nitride crystal is grown is less liable to sublimate than the starting substrate. The second layer is made of a substance whose thermal conductivity is higher than that of the first layer.

Abstract: The invention provides methods which can be applied during the epitaxial growth of two or more layers of Group III-nitride semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects interact with a protective layer of a protective material to form amorphous complex regions capable of preventing the further propagation of defects and dislocations. The invention also includes semiconductor structures fabricated by these methods.