Abstract: The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are provided within a reaction chamber. The gas mixture is reacted to form a layer of material over the substrate by simultaneous deposition and etch of the layer. The layer of material fills the gap such that the material within the gap is essentially void-free. The invention includes a method of providing improved deposition rate uniformity. A material is deposited over a surface in the presence of at least one gas selected from the group consisting of D2, HD, DT, T2 and TH. The net deposition rate during the deposition has a degree of variance across the surface which is measurably improved relative to a corresponding degree of variance that occurs during deposition utilizing H2 under otherwise substantially identical conditions.

Abstract: It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof.

Abstract: Methods of preparing a low-k dielectric material on a substrate are provided. The methods involve using plasma techniques to remove porogen from a precursor layer comprising porogen and a dielectric matrix and to protect the dielectric matrix with a silanol capping agent, resulting in a low-k dielectric matrix. Porogen removal and silanol capping can occur concurrently or sequentially. If performed sequentially, silanol capping is performed without first exposing the dielectric matrix to moisture or ambient conditions.

Abstract: A method and apparatus for mounting semiconductor die and integral heat spreader are disclosed. In one embodiment, thermal expansion of the integral heat spreader is restricted by physical constraints during the process of heating interface material that bonds the integral heat spreader and semiconductor die together. In an alternative embodiment, thermal expansion of the integral hat spreader is restricted by applying an external compressive force to the integral heat spreader while heating interface material that bonds the integral heat spreader and semiconductor die together.

Abstract: A process for forming a patterned thin film structure on a substrate or in-mold decoration film is disclosed. A pattern is printed with a material, such as a masking coating or ink, on the substrate, the pattern being such that, in one embodiment, the desired structures will be formed in the areas where the printed material is not present, i.e., a negative image of thin film structure to be formed is printed. In another embodiment, the pattern is printed with a material that is difficult to strip from the substrate, and the desired thin film structures will be formed in the areas where the printed material is present, i.e., a positive image of the thin film structure is printed. The thin film material is deposited on the patterned substrate, and the undesired area is stripped, leaving behind the patterned thin film structure.

Abstract: Methods and apparatuses are disclosed relating to blocking ultraviolet electromagnetic radiation from a semiconductor. Ultraviolet electromagnetic radiation, such as ultraviolet electromagnetic radiation generated by a plasma process, which may otherwise damage a semiconductor can be blocked from one or more layers below an ultraviolet blocking layer.

Abstract: An insulated structure of a chip array component and fabrication method of the same, the element is fabricated by enclosing its main body with a dense layer of high surface insulation resistance material, and then exposing the portions of the main body where terminal electrodes are to be formed by removing the dense layer of high surface insulation resistance material by employing sand blasting, laser trimming, grinding, or etching process.

Abstract: A substrate processing method includes the steps of removing carbon from a surface of a silicon substrate by irradiating an ultraviolet light on the surface in an essentially ultraviolet nonreactive gas atmosphere and forming an oxide film or an oxynitride film on the surface of the silicon substrate by irradiating an ultraviolet light thereon in an essentially ultraviolet reactive gas atmosphere. Further, a computer readable storage medium stores therein a program for controlling the substrate processing method.

Abstract: A printed wiring board including solder pads excellent in frequency characteristic is provided. To do so, each solder pad 73 is formed by providing a single tin layer 74 on a conductor circuit 158 or a via 160. Therefore, a signal propagation rate can be increased, as compared with a printed wiring board of the prior art on which two metal layers are formed. In addition, due to lack of nickel layers, manufacturing cost can be decreased and electric characteristics can be enhanced.

Abstract: Provided herein is a substrate processing system, which comprises a cassette load station; a load lock chamber; a centrally located transfer chamber; and one or more process chambers located about the periphery of the transfer chamber. The load lock chamber comprises double dual slot load locks constructed at same location. Such system may be used for processing substrates for semiconductor manufacturing.

Abstract: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

Abstract: The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are provided within a reaction chamber. The gas mixture is reacted to form a layer of material over the substrate by simultaneous deposition and etch of the layer. The layer of material fills the gap such that the material within the gap is essentially void-free. The invention includes a method of providing improved deposition rate uniformity. A material is deposited over a surface in the presence of at least one gas selected from the group consisting of D2, HD, DT, T2 and TH. The net deposition rate during the deposition has a degree of variance across the surface which is measurably improved relative to a corresponding degree of variance that occurs during deposition utilizing H2 under otherwise substantially identical conditions.

Abstract: A depression is formed from a first surface of a semiconductor substrate. An insulating layer is provided on the bottom surface and an inner wall surface of the depression. A conductive portion is provided inside the insulating layer. A second surface of the semiconductor substrate is etched by a first etchant having characteristics such that the etching amount with respect to the semiconductor substrate is greater than the etching amount with respect to the insulating layer, and the conductive portion is caused to project while covered by the insulating layer. At least a portion of the insulating layer formed on the bottom surface of the depression is etched with a second etchant having characteristics such that at least the insulating layer is etched without forming a residue on the conductive portion, to expose the conductive portion.

Abstract: Compositions that can be used in semiconductor manufacturing processes, comprising perhydro-polysilazane having a weight average molecular weight of about 300 to about 3,000 and a polydispersity index of about 1.8 to about 3.0 are provided. Solutions comprising the compositions of the present invention, methods of forming films in a semiconductor manufacturing process, and methods of manufacturing semiconductor devices are also provided.

Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same is disclosed. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the lead between the bonding locations to form multiple conductive elements from each individual lead.

Abstract: A method for thinning a wafer by placing a wafer having a protective tape attached to the front side thereof, on which chip circuits have been fabricated, on a working table in such a manner that the protective tape is intervened between the wafer and the working table, and grinding the back side of the wafer to thin it, the method comprising, prior to the thinning by grinding, adhering the beveled portion at the front side of the wafer to the protective tape. The adhesion is preferably effected by a material exhibiting a modulus of elasticity of 0.1 to 100 MPa at the state of the adhesion of the beveled portion to the protective tape. As the material for the adhesion, an acrylic resinous material of the UV-curing type can be used.

Abstract: A method and system for identifying and/or removing an oxide-induced dead zone in a VCSEL structure is disclosed herein. In general, a VCSEL structure can be formed having at least one oxide layer and an oxide-induced dead zone thereof. A thermal annealing operation can then be performed upon the VCSEL structure to remove the oxide-induced dead zone, thereby permitting oxide VCSEL structures thereof to be reliably and consistently fabricated. An oxidation operation may initially be performed upon the VCSEL structure to form the oxide layer and the associated oxide-induced dead zone. The thermal annealing operation is preferably performed upon the VCSEL after performing a wet oxidation operation upon the VCSEL structure.

Abstract: A solar cell module comprising a substrate, a filler, a photovoltaic element and a protective layer, wherein at least one of the substrate, the filler, the photovoltaic element and the protective layer is separable from other constituent members. Constituent members having been separated and still serviceable can be reused.

Abstract: A method of improving the yield and performance of IC devices fabricated on a semiconductor wafer is disclosed. The method includes fabricating via plugs in via openings provided in an intermetal dielectric (IMD) layer on a wafer, subjecting the wafer to CMP to isolate the via plugs, immersing and soaking the wafer in deionized (DI) water, and drying the wafer using isopropyl alcohol, typically in a Marangoni-type dryer. The Marangoni IPA drying step prevents the formation of static electricity on the wafer, and thus, prevents the adherence of small charged particles to the wafer. As a result, the yield of IC devices fabricated on the wafer, as well as the performance of the devices, is enhanced.

Abstract: Prior to converting a non-single crystal material of a semiconductor film into a single crystal material through the use of a laser beam, at least one dopant is introduced into whole of the semiconductor film. Then, the non-single crystal semiconductor film is irradiated with a laser beam to crystallize the semiconductor film. In this case, a ratio between quasi-fermi level of the single crystal material within one of transistor formation regions used to form transistors of different conductivity types and quasi-fermi level of the single crystal material within the other thereof is made to be between 0.5:1 and 2.0:1. Thus, transistors of different conductivity types are formed in the crystallized semiconductor film.

Abstract: A new method to form passivation openings in the manufacture of an integrated circuit device is achieved. The passivation openings have gradually sloping sidewalls that allow a protective tape to be completely removed without leaving adhesive residue. A semiconductor substrate is provided. A passivation layer is deposited. An organic photoresist layer is deposited overlying the passivation layer. The organic photoresist layer is patterned to expose the passivation layer in areas where passivation openings are planned. The organic photoresist layer is reflowed to create gradually sloping sidewalls on the organic photoresist layer. The passivation layer is etched through to from the passivation openings. The passivation openings are thereby formed with gradually sloping sidewalls. The organic photoresist layer is stripped away. A protective tape is applied overlying the passivation layer and the passivation openings. The protective tape is removed.

Abstract: A structure and method of forming a fully planarized polymer thin-film transistor by using a first planar carrier to process a first portion of the device including gate, source, drain and body elements. Preferably, the thin-film transistor is made with all organic materials. The gate dielectric can be a high-k polymer to boost the device performance. Then, the partially-finished device structures are flipped upside-down and transferred to a second planar carrier. A layer of wax or photo-sensitive organic material is then applied, and can be used as the temporary glue. The device, including its body area, is then defined by an etching process. Contacts to the devices are formed by conductive material deposition and chemical-mechanical polish.

Abstract: The present invention provides a method for forming a discontinuous conductive layer in the fabrication of integrated circuits. The method includes providing a substrate assembly having a surface including at least one metal-containing adhesion region separated by at least one surface region of the substrate assembly. A conductive metal layer is formed on the surface of the substrate assembly. The substrate assembly including the conductive metal layer thereon is then annealed. Any nonadhered conductive metal is removed from the at least one exposed surface region to form a discontinuous conductive metal layer on at least one metal-containing adhesion region, for example, by simply rinsing the substrate assembly in water. The conductive metal layer can be platinum or ruthenium.

Abstract: An organic resin with an optical crosslinking agent therein is coated to form an organic resin layer over a resist mast and a patterned thin film, and crosslinked. Although some debris are formed over the resist mask in the fabrication of the patterned thin film, they are trapped by the crosslinked organic resin layer. The resist mask and the organic resin layer are removed through immersion in an organic solvent and vibration therein without flashes.

Abstract: A method for depositing a passivation layer on a substrate surface using one or more electroplating techniques is provided. Embodiments of the method include selectively depositing an initiation layer on a conductive material by exposing the substrate surface to a first electroless solution, depositing a passivating material on the initiation layer by exposing the initiation layer to a second electroless solution, and cleaning the substrate surface with an acidic solution. In another aspect, the method includes applying ultrasonic or megasonic energy to the substrate surface during the application of the acidic solution. In still another aspect, the method includes using the acidic solution to remove between about 100 Å and about 200 Å of the passivating material. In yet another aspect, the method includes cleaning the substrate surface with a first acidic solution prior to the deposition of the initiation layer.

Abstract: A method of manufacturing electronic devices containing one or more layers of materials that are sensitive to the strong chemicals used to remove cross-linked polymeric layers such as photoresists and antireflective coatings is provided. The cross-linked polymeric layers can be easily removed following etching through the use of certain removable layers disposed between the substrate and the cross-linked polymeric layers.

Abstract: Methods are provided for removing edge beads from spin-on films. A spin-on film is removed from a region of a surface of a spin-coated substrate adjacent to an edge of the surface by spinning the spin-coated substrate, expanding a fluid through a nozzle to form a cryogenic aerosol stream, and directing the cryogenic aerosol stream against the spin-on film in the region as the substrate spins. In another aspect of the invention, a film is formed on a surface of a substrate by dispensing a liquid composition onto the surface, spinning the substrate to distribute the liquid composition to form a substantially uniform film on the surface, expanding a fluid through a nozzle to form a cryogenic aerosol stream, and directing the cryogenic aerosol stream against the film in a region of the surface adjacent to an edge of the surface as the substrate spins. The film may include an alkoxysilane and a low volatility solvent. The fluid may consists essentially of liquid carbon dioxide.

Abstract: A linewidth measurement structure for determining linewidths of damascened metal lines formed in an insulator is provided. The linewidth measurement structure including: a damascene polysilicon line formed in the insulator, the polysilicon line having an doped region having a predetermined resistivity.

Abstract: Disclosed is a CMP slurry for nitride having a low selectivity to oxide. More specifically, a CMP slurry for nitride is disclosed which has a high selectivity to nitride by regulating a weight content of an abrasive and by varying a pH of the slurry in order to prevent the oxide from being polished faster than the nitride. As a result, a semiconductor device of high density and high integration can be manufactured.

Abstract: Methods of oxidizing the surface of a photoresist material on a semiconductor substrate to alter the photoresist material surface to be substantially hydrophilic. Oxidation of the photoresist material surface substantially reduces or eliminates stiction between a planarizing pad and the photoresist material surface during chemical mechanical planarization. This oxidation of the photoresist material may be achieved by oxygen plasma etching or ashing, by immersing the semiconducter substrate in bath containing an oxidizing agent, or by the addition of an oxidizing agent to the chemical slurry used during planarization of the resist material.

Abstract: The present invention includes a filtered mask enclosure having an exterior portion and interior regions within the exterior portion such that the interior regions have a filtering region and a purging region connected to the filtering region. The present invention further includes a method of removing a first contaminant in a gas phase, a second contaminant in a solid phase, and a third contaminant having an electrical charge from a purge gas and flowing the purge gas through a vicinity of a mask while exposing a wafer with light through the mask.

Abstract: A method for utilizing a rough insulator to enhance metal-insulator-semiconductor reliability is provided. The method includes steps of: (a) providing a semiconductor substrate; (b) prebaking the semiconductor substrate under a relatively high vacuum to form a rough surface on the semiconductor substrate; and (c) growing an insulator on the semiconductor substrate to form a rough insulator and increase the metal-insulator-semiconductor reliability when the insulator is applied.

Abstract: A process for forming a thermally enhanced Chip On Board semiconductor device with a heat sink is described. In one aspect, a thermally conductive-filled gel elastomer or a silicon elastomeric material or elastomeric material, if the material is to be removed, is applied to the die surface to which the heat sink is to be bonded. During the subsequent glob top application and curing steps, difficult-to-remove glob top material which otherwise may be misapplied to the die surface adheres to the upper surface of the elastomer material. The elastomer material is removed by peeling prior to adhesion bonding of the heat sink to the die. In another aspect, the thermally conductive-filled gel elastomer is applied between a die surface and the inside attachment surface of a cap-style heat sink to eliminate overpressure on the die/substrate interface.

Abstract: A method of fabricating a semiconductor device, includes (a) forming an oxide film entirely over a silicon substrate on which a MOS transistor is fabricated, (b) carrying out first thermal-annealing to the silicon substrate, (c) removing the oxide film in an area where later mentioned silicide is to be formed, (d) forming a metal film entirely over the silicide substrate, (e) carrying out second thermal-annealing to the silicon substrate to form silicide in the area, and (f) removing the metal film having been not reacted with the silicon substrate.

Abstract: In a case where a CF film is used as an interlayer dielectric film of a semiconductor device, when a wiring of tungsten is formed, the CF film is heated to a temperature of, e.g., about 400 to 450° C. At this time, F gases are desorbed from the CF film, so that there are various disadvantages due to the corrosion of the wiring and the decrease of film thickness. In order to prevent this, thermostability is enhanced. A compound gas of C and F, e.g., C4F8 gas, and a hydrocarbon gas, e.g., C2H4 gas, are used as thin film deposition gases. These gases are activated as plasma to deposit a CF film on a semiconductor wafer 10 using active species thereof. Then, Ar gas serving as a sputtering gas is introduced to be activated as plasma, and the CF film deposited on the wafer 10 is sputtered with the Ar plasma. If the thin-film deposition process and the sputtering process are alternately repeated, weak bonds existing in the CF film are removed by sputtering.

Abstract: A method of manufacturing a semiconductor device includes the formation of a dielectric film on a substrate having an effective device area surrounded by a peripheral area. A resist pattern exposing part of the dielectric film in the peripheral area is formed, and the dielectric film is etched to reduce the thickness of the exposed part. After the resist pattern has been removed, the dielectric film is planarized by chemical-mechanical polishing. Good planarity is achieved because the etching step removes high parts of the dielectric film from the peripheral area. This method of achieving improved planarity is less expensive than conventional methods employing dummy devices.

Abstract: A semiconductor substrate includes a porous semiconductor having: a porous layer, with an impurity concentration on varying in the depth direction, or having a porous semiconductor containing an impurity with a content of 1×1018cm−3 or more, or provided by pore formation in an epitaxial growth layer. A method of making a semiconductor substrate; includes forming a variant impurity layer with an impurity concentration varying in the depth direction on one surface of a supporting substrate, and converting the variant impurity layer into a porous layer having a variant porosity in the depth direction. A method of making a thin-film semiconductive member; includes forming a semiconductive thin film on the supporting substrate and separating it by cleavage in the porous phase, in addition to the method for making the semiconductor substrate.

Abstract: A method for producing cavities, which are patterned in submicrometer dimensions, in a cavity layer of a semiconductor device, is described. In the method, a process liquid is frozen in the trenches in a process layer which has been patterned by ribs and trenches, then the process liquid is covered with a covering layer and is then expelled from the cavities resulting from the covering of the trenches.

Abstract: A method of enabling the removal of fluorine containing residue from a semiconductor substrate comprising applying a gas and/or vapor to which the residue is reactive to the residue while the temperature of the substrate is at an elevated level with respect to ambient temperature and the residue is exposed to ultraviolet radiation, for a time period which is sufficient to effect at least one of volatilizing the residue or rendering the residue hydrophilic enough to be removable with deionized water.

Abstract: A process for forming a portion of an integrated circuit includes placing a layer of material on a substrate, in which the material includes a polymeric composition or a precursor to a dielectric composition. The material is contacted with a stamping surface having relief structures that define a pattern, so that a patterned layer is formed as a result of the contact, which may include heating the material to mold it. A metal film or layer is then deposited onto the patterned layer. The metal can then be planarized to form a layer of an integrated circuit. A decomposable or sacrificial polymer is preferably included in the material, so that porous dielectric material is formed, thereby leading to a lower dielectric constant of the end product.

Abstract: A method of manufacturing a semiconductor device is capable of preventing a dishing phenomenon from occurring without using dummy patterns. A plurality of conductive patterns are formed along the entire surface of a semiconductor substrate with an irregular pattern density. The conductive patterns have a first stopper layer at the top thereof. An interlayer insulating layer is formed on the conductive patterns. Next, a second stopper layer is formed on the interlayer insulating layer. An etching mask is formed on the second stopper layer so as to expose a first region having a conductive pattern density that is higher than that of another region(s). By using the etching mask, the second stopper layer and part of the interlayer insulating layer are etched at the first region.

Abstract: A method of CMP thin films during fabrication of IC devices includes preparing a substrate, including building IC component structures on the substrate; depositing a bottom electrode on the substrate; depositing a first CMP layer having a first known CMP selectivity on the substrate; patterning the first CMP layer to form a pattern having a lower margin; forming indicator structures on the first CMP layer in the pattern; depositing a second CMP layer having a second known CMP selectivity relative to that of the first CMP layer, including depositing portions of the second CMP layer in the pattern of the first CMP layer; CMP the structure so that the indicator structures are removed and any portion of the first CMP layer and second CMP layer are removed to a level corresponding to the lower margin; and completing the IC structure.

Abstract: Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor such that at least a portion of the second capacitor is underlying the first capacitor. Such memory cell capacitors can thus have increased surface area for a given capacitor height versus memory cell capacitors formed strictly laterally adjacent one another. The memory cell capacitors can be fabricated using silicon-on-insulator (SOI) techniques. The memory cell capacitors are useful for a variety of memory arrays, memory devices and electronic systems.

Abstract: The present invention provides a method for fabricating bulbous-shaped vias on a substrate, having a surface, by disposing, on the substrate, a polymerizable fluid composition. A mold is placed in contact with the polymerizable fluid composition. The mold includes a relief structure on a surface thereof to create a recess in a layer of the polymerizable fluid composition. The polymerizable fluid composition is subjected to conditions to cause polymerization, forming a polymerized layer having a solidified indentation. An opening to the surface of the substrate is formed by removing material disposed on the substrate surface through etch processes. In a further embodiment a conductive layer may be disposed in the opening to form a gate. A lift-off process may be employed to remove the polymerized layer.

Abstract: Current passed through a resist layer or insulating layer is controlled by changing the amplitude of an AC voltage to provide an electron exposure device or electric characteristics evaluation device using a scanning probe.

Abstract: A method for fabricating a substantially smooth-surfaced anti-reflective coating on a semiconductor device structure including generating a plasma from an inert gas in a process chamber in which the anti-reflective coating is to be deposited. The anti-reflective coating may include silicon, oxygen and nitrogen, and is preferably of the general formula SixOyNz, where x equals 0.40 to 0.65, y equals 0.02 to 0.56 and z equals 0.05 to 0.33. Preferably, x+y+z equals one. The method may also include fabricating a silicon nitride layer over the anti-reflective coating. A semiconductor device which includes a silicon nitride layer over the anti-reflective coating has a density of less than about 40,000 particles or surface roughness features in the silicon nitride of about 120-150 nanometers dimension per eight inch wafer. Accordingly, a mask that is subsequently formed over the silicon nitride layer has a substantially uniform thickness and is substantially distortion-free.

Abstract: A process for forming sub-lithographic features in an integrated circuit is disclosed herein. A process for enhancing the etch trimmability and the etch stability of features patterned on a photoresist layer is also disclosed herein. The process includes curing a photoresist layer after patterning and development but before an etch process is performed thereon. By controlling the formation of the cured portions of the features patterned on the photoresist layer, the features can be trimmed to sub-lithographic critical dimensions without pattern deformation or occurrence of other failure mechanisms.

Abstract: Methods of oxidizing the surface of a photoresist material on a semiconductor substrate to alter the photoresist material surface to be substantially hydrophillic. Oxidation of the photoresist material surface substantially reduces or eliminates stiction between a planarizing pad and the photoresist material surface during chemical mechanical planarization. This oxidation of the photoresist material may be achieved by oxygen plasma etching or ashing, by immersing the semiconductor substrate in a bath containing an oxidizing agent, or by the addition an oxidizing agent to the chemical slurry used during planarization of the resist material.

Abstract: A polish head for Chemical Mechanical Polishing includes a backing film of silicone on a rigid support element, preferably, of amorphous ceramic. The silicone backing film is fabricated by molding, thereby enabling an appropriate cross-sectional shape for specific polishing needs. The head provides a uniform polishing of a semiconductor wafer.

Abstract: A semiconductor device in accordance with the present invention reduces cracks occurring in a junction between a semiconductor device and a mounting substrate due to a heat stress when the semiconductor device is mounted on a printed circuit board or the like. The semiconductor device has a semiconductor element having a thickness of 200 &mgr;m or less, an electrode pad formed on the semiconductor element, a post electrically connected to the electrode pad, and a sealing resin for sealing a surface where circuitry is formed and the post.