Abstract: A substrate processing apparatus, a method of manufacturing a semiconductor device, and a method of confirming an operation of a liquid flowrate control device are provided. The substrate processing apparatus comprises: a process chamber accommodating a substrate; a liquid source supply system supplying a liquid source into the process chamber; a solvent supply system supplying a solvent having a vapor pressure greater than that of the liquid source into the process chamber; a liquid flowrate control device controlling flowrates of the liquid source and the solvent; and a controller controlling the liquid source supply system, the solvent supply system, and the liquid flowrate control device so that the solvent is supplied into the liquid flowrate control device than the solvent supply system to confirm an operation of the liquid flowrate control device before the liquid source supply system supplies the liquid source into the process chamber.

Abstract: Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate.

Abstract: Disclosed is a sputtering target having a good appearance, which is free from white spots on the surface. The sputtering target is characterized by being composed of an oxide sintered body containing two or more kinds of homologous crystal structures.

Abstract: An apparatus for depositing a solid film onto a substrate from a reagent solution includes reservoirs of reagent solutions maintained at a sufficiently low temperature to inhibit homogeneous reactions within the reagent solutions. The chilled solutions are dispensed through showerheads, one at a time, onto a substrate. One of the showerheads includes a nebulizer so that the reagent solution is delivered as a fine mist, whereas the other showerhead delivers reagent as a flowing stream. A heater disposed beneath the substrate maintains the substrate at an elevated temperature at which the deposition of a desired solid phase from the reagent solutions may be initiated. Each reagent solution contains at least one metal and either S or Se, or both. At least one of the reagent solutions contains Cu. The apparatus and its associated method of use are particularly suited to forming films of Cu-containing compound semiconductors.

Abstract: The present invention relates to a dicing film having an adhesive film for dicing a wafer and a die adhesive film, which are used for manufacturing a semiconductor package, and a method of manufacturing a semiconductor package using the same. More particularly, the present invention relates to a dicing film wherein a shrinkage release film is inserted between an adhesive film for dicing a wafer and a die adhesive film so that the die adhesive film and a die can be easily separated from the adhesive film for dicing a wafer when picking up a semiconductor die, and a method of manufacturing a semiconductor package using the same.

Abstract: A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.

Abstract: A semiconductor device including a compound semiconductor laminated structure having a plurality of compound semiconductor layers formed over a semiconductor substrate, a first insulation film covering at least a part of a surface of the compound semiconductor laminated structure, and a second insulation film formed on the first insulation film, wherein the second insulation film includes more hydrogen than the first insulation film.

Abstract: A method of fabricating a semiconductor device, the method comprises forming a mask layer over a compound semiconductor substrate; and patterning a photoresist over the mask layer. The method comprises etching a portion of the mask layer beneath the photoresist; forming a hardmask over the substrate and not over the mask layer; removing the mask layer; etching to form and opening down to the substrate; and forming a gate in the opening.

Abstract: Methods of forming dielectric layers on a substrate comprising silicon and oxygen are disclosed herein. In some embodiments, a method of forming a dielectric layer on a substrate includes provide a substrate having an exposed silicon oxide layer; treating an upper surface of the silicon oxide layer with a plasma; and depositing a silicon nitride layer on the treated silicon oxide layer via atomic layer deposition. The silicon nitride layer may be exposed to a plasma nitridation process. The silicon oxide and silicon nitride layers may be subsequently thermally annealed. The dielectric layers may be used as part of a gate structure.

Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.

Abstract: Made available is a Group III nitride crystal manufacturing method whereby incidence of cracking in the III-nitride crystal when the III-nitride substrate is removed is kept to a minimum. III nitride crystal manufacturing method provided with: a step of growing, onto one principal face (10m) of a III-nitride substrate (10), III-nitride crystal (20) at least either whose constituent-atom type and ratios, or whose dopant type and concentration, differ from those of the III-nitride substrate (10); and a step of removing the III-nitride substrate (10) by vapor-phase etching.

Abstract: A SiC semiconductor device includes: a SiC substrate having a main surface; a channel region on the substrate; first and second impurity regions on upstream and downstream sides of the channel region, respectively; a gate on the channel region through a gate insulating film. The channel region for flowing current between the first and second impurity regions is controlled by a voltage applied to the gate. An interface between the channel region and the gate insulating film has a hydrogen concentration equal to or greater than 2.6×1020 cm?3. The interface provides a channel surface perpendicular to a (0001)-orientation plane.

Abstract: A composition comprising: a polymerized substance of a compound (I) that contains m numbers of RSi(O0.5)3 units, wherein m represents an integer of from 8 to 16; and R's each independently represents a non-hydrolysable group, provided that at least two among R's represent groups containing a vinyl group or an ethynyl group, and wherein each one of the RSi(O0.5)3 units is connected to another one of the RSi(O0.5)3 units by sharing an oxygen atom in each one of the RSi(O0.5)3 units, so as to form a cage structure, and wherein within a solid component contained in the composition, a polymerized substance formed by a reaction of the compound (I) represents 60 mass % or more.

Abstract: An apparatus for depositing a solid film onto a substrate from a reagent solution includes a reservoir of solution maintained at a low temperature to inhibit homogeneous reactions. The solution contains multiple ligands to control temperature stability and shelf life. The chilled solution is periodically dispensed onto a substrate positioned in a holder having a raised peripheral structure that retains a controlled volume of solution over the substrate. The solution is periodically replenished so that only the part of the solution directly adjacent to the substrate is heated. A heater maintains the substrate at an elevated temperature at which the deposition of a desired solid phase from the solution may be initiated. The apparatus may also dispense excess chilled solution to cool various components within the apparatus and minimize nucleation of solids in areas other than on the substrate. The apparatus is particularly suited to forming films of II-VI semiconductors.

Abstract: A method of manufacturing a silicon carbide semiconductor device having low interface state density in an interface region between a gate insulating film and a silicon carbide layer is provided. An epitaxially grown layer is grown on a 4H-SiC substrate, and thereafter ion implantation is performed to form a p well region, a source region and a p+ contact region that are ion implantation layers. Thereafter, using thermal oxidation or CVD, the gate insulating film formed by a silicon oxide film is formed on the p well region, the source region and the p+ contact region. Then, plasma is generated using a gas containing N2O, which is the gas containing at least any one of oxygen and nitrogen, so as to expose the gate insulating film to plasma.

Abstract: An apparatus for depositing a solid film onto a substrate from a reagent solution includes a reservoir of reagent solution maintained at a sufficiently low temperature to inhibit homogeneous reactions within the reagent solution. The reagent solution contains multiple ligands to further control temperature stability and shelf life. The chilled solution is dispensed through a showerhead onto a substrate. The substrate is positioned in a holder that has a raised structure peripheral to the substrate to retain or impound a controlled volume (or depth) of reagent solution over the exposed surface of the substrate. The reagent solution is periodically or continuously replenished from the showerhead so that only the part of the solution directly adjacent to the substrate is heated. A heater is disposed beneath the substrate and maintains the substrate at an elevated temperature at which the deposition of a desired solid phase from the reagent solution may be initiated.

Abstract: A method of forming a portion (10) of a compound semiconductor MOSFET structure comprises forming a compound semiconductor layer structure (14) and an oxide layer (20) overlying the same. Forming the compound semiconductor structure (14) includes forming at least one channel material (16) and a group-III rich surface termination layer (18) overlying the at least one channel material. Forming the oxide layer (20) includes forming the oxide layer to overlie the group-III rich surface termination layer and comprises one of (a) depositing essentially congruently evaporating oxide of at least one of (a(i)) a ternary oxide and (a(ii)) an oxide more complex than a ternary oxide and (b) depositing oxide molecules, with use of at least one of (b(i)) a ternary oxide and (b(ii)) an oxide more complex than a ternary oxide.

Abstract: A method of forming a low-K dielectric film, comprises the steps of placing a substrate carrying thereon a low-K dielectric film on a stage, heating the low-K dielectric film on the stage, processing the low-K dielectric film by plasma of a processing gas containing a hydrogen gas, the plasma being excited while supplying the processing gas over the low-K dielectric film, wherein the plasma is excited within 90 seconds after placing the substrate upon the stage.

Abstract: The major objective is to provide a fluorocarbon film wherein fine voids are formed by a step (SA1) for introducing a mixed gas containing a first carbon fluoride gas and a second carbon fluoride gas on a substrate placed inside a chamber, and depositing a fluorocarbon film on the substrate; and a step (SA2) for forming voids in the fluorocarbon film by selectively removing volatile components contained in the fluorocarbon film are included and especially in the step (SA2) for forming voids, it is preferable to include a step for cleaning the fluorocarbon film with a supercritical fluid.

Abstract: Group III-Nitride semiconductor device structures and methods of fabricating Group III-Nitride structures are provided that include an electrically conductive Group III-Nitride substrate, such as a GaN substrate, and a semi-insulating or insulating Group III-Nitride epitaxial layer, such as a GaN epitaxial layer, on the electrically conductive Group III-Nitride substrate. The Group III-Nitride epitaxial layer has a lattice constant that is and a composition that may be substantially the same as a composition and a lattice constant of the Group III-Nitride substrate.

Abstract: Methods are disclosed for preparing a reconditioned donor substrate by providing a remainder substrate from a donor substrate wherein the remainder substrate has a detachment surface where a transfer layer was detached and an opposite surface; and depositing an additional layer onto the opposite surface of the remainder substrate to increase its thickness and to form a reconditioned substrate. The reconditioned substrate is recycled as a donor substrate for fabricating compound material wafers.

Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.

Abstract: Thin films are disclosed that are suitable as dielectrics in IC's and for other similar applications. In particular, the invention concerns thin films comprising compositions obtainable by hydrolysis of two or more silicon compounds, which yield an at least partially cross-linked siloxane structure. The invention also concerns a method for producing such films by preparing siloxane compositions by hydrolysis of suitable reactants, by applying the hydrolyzed compositions on a substrate in the form of a thin layer and by curing the layer to form a film. In one example, a thin film comprising a composition is obtained by hydrolyzing a monomeric silicon compound having at least one hydrocarbyl radical, containing an unsaturated carbon-to-carbon bond, and at least one hydrolyzable group attached to the silicon atom of the compound with another monomeric silicon compound having at least one aryl group and at least one hydrolyzable group attached to the silicon atom of the compound to form a siloxane material.

Abstract: Provided is a method of controlling an alignment direction of CNTs in manufacturing a carbon nanotube semiconductor device using the CNTs for a channel region formed between a source electrode and a drain electrode. In manufacturing a carbon nanotube semiconductor device including a gate electrode, a gate insulating film, a source electrode, a drain electrode, a CNT layer formed between the source electrode and the drain electrode in contact therewith, the method conducts: dropping a CNT solution obtained by dispersing CNTs in a solvent onto a region between the source electrode and the drain electrode while an alternating current voltage is applied between the source electrode and the drain electrode; and removing the solvent to control an orientation of the CNTs in the CNT layer.

Abstract: The present invention is a method of manufacturing a semiconductor device from a layered body including: a semiconductor substrate; a high dielectric film formed on the semiconductor substrate; and an SiC-based film formed on a position upper than the high dielectric film, the SiC-based film having an anti-reflective function and a hardmask function. The present invention comprises a plasma-processing step for plasma-processing the SiC-based film and the high dielectric film to modify the SiC-based film and the high dielectric film by an action of a plasma; and a cleaning step for wet-cleaning the SiC-based film and the high dielectric film modified in the plasma-processing step to collectively remove the SiC-based film and the high dielectric film.

Abstract: An electronic apparatus includes an insulative substrate containing an aluminum-based glass and a layer containing a semiconductive material over the substrate. The insulative substrate can include aluminum oxycarbide. The insulative substrate can exhibit a CTE sufficiently close to a CTE of the semiconductive material layer such that a strain of less than 1% would exist between a 1000 Angstroms thickness of the semiconductive material layer and the insulative substrate. The semiconductive material layer can include monocrystalline silicon. The electronic apparatus can be a silicon-on-insulator integrated circuit. An electronic apparatus fabrication method includes forming an insulative substrate containing an aluminum-based glass and forming a layer containing a semiconductive material over the substrate.

Abstract: Hall device is provided by enabling stable provision of a quantum well compound semiconductor stacked structure. It has first and second compound semiconductor layers composed of Sb and at least two of five elements of Al, Ga, In, As and P, and an active layer composed of InxGa1-xAsySb1-y (0.8?x?1.0, 0.8?y?1.0), which are stacked. Compared with the active layer, the first and second compound semiconductor layers each have a wider band gap, and a resistance value five times or more greater. The lattice constant differences between the active layer and the first and second compound semiconductor layers are each designed in a range of 0.0-1.2%, and the thickness of the active layer is designed in a range of 30-100 nm.

Abstract: A semiconductor device is disclosed that includes a layer of Group III nitride semiconductor material that includes at least one surface, a control contact on the surface for controlling the electrical response of the semiconductor material, a dielectric barrier layer covering at least a portion of the one surface adjacent the control contact, the dielectric barrier layer having a bandgap greater than the bandgap of the Group III nitride and a conduction band offset from the conduction band of the Group III nitride; and a dielectric protective layer covering the remainder of the Group III nitride surface.

Abstract: A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.

Abstract: A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is higher near an interface to the insulator and lower in a surface side opposite to the insulator, and a second gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is substantially uniform and an n-type dopant of a concentration of above 6×1020 atoms/cm3 is contained.

Abstract: In one aspect, the invention encompasses a semiconductor processing method. A layer of material is formed over a semiconductive wafer substrate. Some portions of the layer are exposed to energy while other portions are not exposed. The exposure to energy alters physical properties of the exposed portions relative to the unexposed portions. After the portions are exposed, the exposed and unexposed portions of the layer are subjected to common conditions. The common conditions are effective to remove the material and comprise a rate of removal that is influenced by the altered physical properties of the layer. The common conditions remove either the exposed or unexposed portions faster than the other of the exposed and unexposed portions. After the selective removal of the exposed or unexposed portions, and while the other of the exposed and unexposed portions remains over the substrate, the wafer is cut into separated die. In another aspect, the invention encompasses another semiconductor processing method.

Abstract: There is provided a process for preparing a composite material of an oxide crystal film and a substrate by forming a Y123 type oxide crystal film from a solution phase on a substrate using a liquid phase method, wherein problems such as cracking of the oxide crystal film, separation of the oxide crystal film from the substrate, and development of a reaction layer between the substrate and the solution can be minimized. The solvent for forming the solution phase uses either a BaO—CuO—BaF2 system or a BaO—CuO—Ag—BaF2 system, and when the substrate with a seed crystal film bonded to the surface is brought in contact with the solution to form (grow) the oxide crystal film on the substrate, the temperature of the solution is controlled to a temperature of no more than 850° C.

Abstract: This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of integrated circuitry. In one implementation, a method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry includes flowing an aluminum containing organic precursor to a chamber containing a semiconductor substrate effective to deposit an aluminum comprising layer over the substrate. An alkoxysilanol is flowed to the substrate comprising the aluminum comprising layer within the chamber effective to deposit a silicon dioxide comprising layer over the substrate.

Abstract: A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material.

Abstract: A method for low-temperature plasma-enhanced chemical vapor deposition of a silicon-nitrogen-containing film on a substrate. The method includes providing a substrate in a process chamber, exciting a reactant gas in a remote plasma source, thereafter mixing the excited reactant gas with a silazane precursor gas, and depositing a silicon-nitrogen-containing film on the substrate from the excited gas mixture in a chemical vapor deposition process. In one embodiment of the invention, the reactant gas can contain a nitrogen-containing gas to deposit a SiCNH film. In another embodiment of the invention, the reactant gas can contain an oxygen-containing gas to deposit a SiCNOH film.

Abstract: The present invention has an object of providing a thyristor-type semiconductor device and a manufacturing method for the same which can prevent, even when conventional manufacturing equipment is used, the electrode terminals 13, 14 from being provided in a significantly tilted state where the electrode terminals 13, 14 are in contact with the silicon substrate 20, and can also prevent the electrode terminals 13, 14 from being provided in a state where the electrode terminals 13, 14 come into contact with the silicon substrate 20, even when there are warping and undulations in the silicon substrate 20. In a semiconductor device of the present invention, the supports 11a, 11b are provided on both surfaces of the silicon substrate 20 using a glass material. When doing so, the support 11b is disposed in a part of the boundary between the second N-type layer 18 and the second P-type layer 19 that is opposite the side surface 22.

Abstract: Provided is a method of controlling an alignment direction of CNTs in manufacturing a carbon nanotube semiconductor device using the CNTs for a channel region formed between a source electrode and a drain electrode. In manufacturing a carbon nanotube semiconductor device including a gate electrode, a gate insulating film, a source electrode, a drain electrode, a CNT layer formed between the source electrode and the drain electrode in contact therewith, the method conducts: dropping a CNT solution obtained by dispersing CNTs in a solvent onto a region between the source electrode and the drain electrode while an alternating current voltage is applied between the source electrode and the drain electrode; and removing the solvent to control an orientation of the CNTs in the CNT layer.

Abstract: A forming method and a forming apparatus of nanocrystalline silicon structure makes it possible to prepare a nanocrystalline silicon structure at a low temperature to have densely packed silicon crystal grains which are stably terminated and to effectively control the grain size in nanometer scale. A forming method and a forming apparatus of nanocrystalline silicon structure with oxide or nitride termination, carry out a first step of treating a surface of a substrate with hydrogen radical; a second step of depositing silicon crystals having a grain size of 10 nm or less by the thermal reaction of a silicon-containing gas; and a third step of terminating the surface of the silicon crystal with oxygen or nitrogen by using one of oxygen gas, oxygen radical and nitrogen radical.

Abstract: A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.

Abstract: A structure on a layer surface of the semiconductor wafer has at least one first area region (8, 9), which is reflective for electromagnetic radiation, and at least one second, essentially nonreflecting area region (10, 11, 12). A light-transmissive insulation layer (13) and a light-sensitive layer are produced on said layer surface. The electromagnetic radiation is directed onto the light-sensitive layer with an angle ? of incidence and the structure of the layer surface is imaged with a lateral offset into the light-sensitive layer.

Abstract: A method of forming low-dielectric-constant silicon oxide films by capacitive-coupled plasma CVD comprises: introducing a processing gas comprising SiH4 as a silicon source gas, SiF4 as a fluorine source gas, and CO2 as an oxidizing gas to a reaction chamber at a ratio of (SiH4+SiF4)/CO2 in the range of 0.02 to 0.2 and at a total pressure of 250 Pa to 350 Pa; applying first RF power at a frequency of 10 MHz to 30 MHz and second RF power at a frequency of 400 kHz to 500 kHz by overlaying the two RF powers to generate a plasma reaction field within the reaction chamber; and controlling a flow of the respective gases and the respective RF power outputs.

Abstract: A method of fabricating a nitride semiconductor includes the steps of forming a nitride semiconductor doped with a p-type impurity, treating the surface of the nitride semiconductor in an atmosphere containing active oxygen to remove carbon remaining on the surface and form an oxide film thereon, and activating the p-type impurity to turn the conductive type of the nitride semiconductor into a p-type. Since carbon remaining on the surface of the nitride semiconductor is removed and the oxide film is formed thereon, the surface of the nitride semiconductor is prevented from being deteriorated by the activating treatment and the rate of activating the p-type impurity is enhanced. As a result, it is possible to reduce the contact resistance of the nitride semiconductor with an electrode and, hence, the variation in characteristics of the nitride semiconductor.

Abstract: A new process is provided which is an extension and improvement of present processing for the creation of a solder bump. After the layers of Under Bump Metal and a layer of solder metal have been created in patterned and etched format and overlying the contact pad, following a conventional processing sequence, a layer of polyimide is deposited. The solder flow is performed using the thickness of the deposited layer of polyimide to control the height of the column underneath the reflown solder.

Abstract: The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 ?m, and a passive element formed directly or indirectly on the insulating region. It is desirable for the passive element to be an inductor.

Abstract: A method passivates a surface of a semiconductor structure. The method provides III-V semiconductor material having a surface to be passivated. Upon the surface of the III-V semiconductor material to be passivated an oxide layer is formed. Thereafter, the surface of the III-V semiconductor material having the oxide layer is passivated, without desorption of the oxide layer and in a vacuum of 2×10?6 Torr, with a material having the ability to intermix with the oxide layer so as to exchange oxygen, passivation layer material, and III-V semiconductor material therebetween to form graded layers of oxidized III-V and passivation material.

Abstract: A semiconductor laser device has on a compound semiconductor substrate at least a lower cladding layer, an active layer, an upper cladding layer and a contact layer. An upper part of the upper cladding layer and the contact layer are formed as a mesa-structured portion having a ridge stripe pattern, and the both sides of the mesa structured portion are buried with a current blocking layer. The laser device includes the current blocking layer having a pit-like recess penetrating thereof and extending towards the compound semiconductor substrate, and a portion of the recess other than that penetrating the current blocking layer being covered or buried with an insulating film or a compound semiconductor layer with a high resistivity. The compound semiconductor substrate and the electrode layer thus can be kept insulated in an area other than a current injection area, thereby non-emissive failure due to short-circuit is prevented.

Abstract: A method of manufacturing a compound semiconductor includes the steps of forming a layered structure of dielectric layers including oxygen or sulfur, and an inter layer formed between the dielectric layers, including rare earth transition metal that is highly reactive to oxygen and sulfur, and heating the layered structure. As a result of the chemical reaction and diffusion of elements, one can change a heated portion of the layered structure to a semiconductor or an insulator, depending on the temperature to which the portion is heated.

Abstract: An Al0.15Ga0.85N layer 2 is formed on a silicon substrate 1 in a striped or grid pattern. A GaN layer 3 is formed in regions A where the substrate 1 is exposed and in regions B which are defined above the layer 2. At this time, the GaN layer grows epitaxially and three-dimensionally (not only in a vertical direction but also in a lateral direction) on the Al0.15Ga0.85N layer 2. Since the GaN layer grows epitaxially in the lateral direction as well, a GaN compound semiconductor having a greatly reduced number of dislocations is obtained in lateral growth regions (regions A where the substrate 1 is exposed).

Abstract: A silicon oxide film formed on a compound semiconductor substrate is evaluated by estimating the quantity of silicon-silicon bonds operating as electron traps in the silicon oxide film from a peak with a wave number of 880/centimeter in the Fourier-transform infrared spectrum of the silicon oxide film. This peak, which is an indicator of silicon-silicon stretching vibration, provides an index of expected power performance degradation during operation of field-effect transistors incorporating the silicon oxide film as an interlayer. Power degradation can be reduced by fabricating the semiconductor device under conditions that reduce the estimated quantity of silicon-silicon bonds, without the need to measure the power degradation.

Abstract: There is disclosed a method of producing a diamond film formed on a substrate, wherein at least after a film (dopant layer) containing doping elements is formed on a surface of the substrate, a vapor phase synthetic diamond film is formed on the dopant layer, and the dopant layer contains diamond particles, which become sources of diamond nuclei, in addition to doping elements, and also disclosed a diamond film produced by the method. There can be provided a method of producing a diamond film that a diamond film having lowered electric resistance can be produced, and also provided a diamond film produced by the method.