Insulative Material Deposited Upon Semiconductive Substrate Patents (Class 438/778)
  • Patent number: 11482412
    Abstract: A film having filling capability of a patterned recess on a surface of a substrate is deposited by forming a viscous material in a gas phase by striking a plasma in a chamber filled with a volatile precursor that can be polymerized within certain parameter ranges which include a partial pressure of the precursor during a plasma strike and substrate temperature.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: October 25, 2022
    Assignee: ASM IP Holding B.V.
    Inventor: Timothee Julien Vincent Blanquart
  • Patent number: 11462398
    Abstract: Embodiments of the present invention are directed to forming a ternary compound using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor includes a first metal and a first ligand. The second precursor includes a second metal and a second ligand. The second ligand is selected based on the first ligand to target a second metal uptake. A substrate is exposed to the first precursor during a first pulse of an ALD cycle and the substrate is exposed to the second precursor during a second pulse of the ALD cycle, the second pulse occurring after the first pulse. The substrate is exposed to a third precursor (e.g., an oxidant) during a third pulse of the ALD cycle. The ternary compound can include a ternary oxide film.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: October 4, 2022
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ULVAC, INC
    Inventors: Martin Michael Frank, John Rozen, Yohei Ogawa
  • Patent number: 11437576
    Abstract: A method and a deposition apparatus of fabricating a display device is disclosed. The method may include providing a target substrate in an internal space of a chamber of a deposition apparatus, depositing a first material which includes an organic material and a deposition material coupled to each other, on the target substrate to form preliminary deposition layer, performing a preliminary decomposition step to remove the organic material, and performing a decomposition step to remove the organic material remained in the preliminary deposition layer and to form a deposition layer. The preliminary decomposition step may include heating the preliminary deposition layer, and the decomposition step may include injecting a second material containing an organic solvent onto the preliminary deposition layer.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: September 6, 2022
    Inventor: Seonghyeon Cheon
  • Patent number: 11430878
    Abstract: A method includes etching a semiconductor substrate to form a plurality of semiconductor fins. The semiconductor fins are etched to form a recess. An epitaxy structure is grown in the recess. The epitaxy structure has a W-shape cross section. A capping layer is formed over the epitaxy structure. The capping layer is at least conformal to a sidewall of the epitaxy structure. The capping layer is etched to expose a top surface of the epitaxy structure. A first portion of the capping layer remains over the sidewall of the epitaxy structure after etching the capping layer. A contact is formed in contact with the exposed top surface of the epitaxy structure and the first portion of the capping layer.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Lilly Su, Yang-Tai Hsiao
  • Patent number: 11424201
    Abstract: A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280° C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40°.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: August 23, 2022
    Assignee: Infineon Technologies AG
    Inventors: Michael Rogalli, Johann Gatterbauer, Wolfgang Lehnert, Kurt Matoy, Evelyn Napetschnig, Manfred Schneegans, Bernhard Weidgans
  • Patent number: 11380544
    Abstract: A laser annealing device includes a stage, a laser generator, and a reflective member. The stage supports a substrate with a thin film formed thereon to be processed, and may be moved in a first direction at a set or predetermined speed. The laser generator irradiates a first area of the thin film with a laser beam while the stage is moved. The reflective member reflects a part of the laser beam, which is reflected from the first area of the thin film, to a second area of the thin film. The first area and the second area are spaced apart from each other.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: July 5, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong-Min Lee, Ji-Hwan Kim, Jongoh Seo, Byung Soo So
  • Patent number: 11371136
    Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing a substrate to a blocking molecule to selectively deposit a blocking layer on the first surface. The blocking layer is exposed to a polymer initiator to form a networked blocking layer. A layer is selectively formed on the second surface. The blocking layer inhibits deposition on the first surface. The networked layer may then optionally be removed.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: June 28, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bhaskar Jyoti Bhuyan, Mark Saly, David Thompson, Lakmal C. Kalutarage, Rana Howlader
  • Patent number: 11367613
    Abstract: Methods and precursors for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD), such as plasma enhanced ALD. In some embodiments, deposited silicon nitride can be treated with a plasma treatment. The plasma treatment can be a nitrogen plasma treatment. In some embodiments the silicon precursors for depositing the silicon nitride comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%). In some embodiments, a method for depositing silicon nitride films comprises a multi-step plasma treatment.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: June 21, 2022
    Assignee: ASM IP HOLDING B.V.
    Inventors: Shang Chen, Viljami Pore, Ryoko Yamada, Antti Juhani Niskanen
  • Patent number: 11342479
    Abstract: Disclosed herein are techniques relating to wafer-to-wafer bonding for manufacturing light-emitting diodes (LEDs). In some embodiments, a method includes reducing bowing of a layered structure including a semiconductor material and a substrate on which the semiconductor material is formed by generating breakages, fractures, or at least one region of weakened bonding within the layered structure. The method also includes bonding a base wafer to the semiconductor material, removing the substrate from the semiconductor material, and forming a plurality of trenches through the semiconductor material to produce a plurality of LEDs.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: May 24, 2022
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: William Padraic Henry, Allan Pourchet
  • Patent number: 11335791
    Abstract: A method of fabricating a semiconductor device, including performing the following steps in the following sequence: providing a substrate including first and second gate regions separated by a trench formed in the substrate and growing a thin oxide layer on each of the first and second gate regions. The method further includes removing the thin oxide layer from the second gate region, and growing a thick oxide layer on the second gate region.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: May 17, 2022
    Assignee: X-FAB SARAWAK SDN. BHD.
    Inventors: Jerry Liew, Jee Chang Lai
  • Patent number: 11289369
    Abstract: A method of forming a low-k dielectric layer with barrier properties is disclosed. The method comprises forming a dielectric layer by PECVD which is doped with one or more of boron, nitrogen or phosphorous. The dopant gas of some embodiments may be coflowed with the other reactants during deposition.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: March 29, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yi Ding, Shaunak Mukherjee, Bo Xie, Kang Sub Yim, Deenesh Padhi
  • Patent number: 11282845
    Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jun Fang, Fei Wang, Saniya Rathod, Rutuparna Narulkar, Matthew Park, Matthew J. King
  • Patent number: 11276573
    Abstract: An exemplary method may include delivering a boron-containing precursor to a processing region of a semiconductor processing chamber. The method may also include forming a plasma within the processing region of the semiconductor processing chamber from the boron-containing precursor. The method may further include depositing a boron-containing material on a substrate disposed within the processing region of the semiconductor processing chamber. The boron-containing material may include greater than 50% of boron. In some embodiments, the boron-containing material may include substantially all boron. In some embodiments, the method may further include delivering at least one of a germanium-containing precursor, an oxygen-containing precursor, a silicon-containing precursor, a phosphorus-containing precursor, a carbon-containing precursor, and/or a nitrogen-containing precursor to the processing region of the semiconductor processing chamber.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: March 15, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Bo Qi, Zeqing Shen, Abhijit Mallick
  • Patent number: 11239310
    Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
  • Patent number: 11226554
    Abstract: An imprint apparatus executes imprint processing of curing imprint material in a state in which the imprint material supplied onto a substrate and a mold are in contact with each other. The imprint apparatus includes a modulator configured to modulate incident light, a first optical system configured to guide first light from a first light source to the modulator, and second light from a second light source that has a wavelength different from that of the first light to the modulator, and a second optical system configured to guide modulated light modulated by the modulator to the substrate.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: January 18, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kenichi Kobayashi, Tatsuya Arakawa
  • Patent number: 11181819
    Abstract: Systems and methods for shaping a film by: depositing a formable material on a field of a substrate; and positioning a template relative to the field. The template has a mesa with a shaping surface and mesa sidewalls surround the shaping surface. The shaping may further comprise contacting the formable material with the shaping surface. The formable material may spread when the shaping surface is in contact with the formable material. The shaping may comprise exposing the formable material to a curing dose of actinic radiation after the formable material has spread to the edge of the field. A spatial distribution of the curing dose may be such that an interior dose applied at an interior of the field may be greater than a sidewall dose that is incident on the mesa sidewalls.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: November 23, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Amir Tavakkoli Kermani Ghariehali, Mehul N. Patel, Edward Brian Fletcher
  • Patent number: 11181768
    Abstract: A display device includes a display panel; a color conversion display panel overlapping the display panel; and a polarizing plate positioned between the display panel and the color conversion display panel, wherein the polarizing plate may include a polarization film and a transfer layer overlapping the polarization film, the transfer layer may be positioned between the polarization film and the display panel, and the transfer layer may include an acrylamide-based compound.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: November 23, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang-Gil Lee, Byung-Gon Kum, Eun Guk Lee
  • Patent number: 11170996
    Abstract: (a) Loading a substrate into a process chamber; (b) supplying a processing gas including H2O-containing radicals to the substrate; (c) supplying a gas including a halogen element; (d) supplying a gas including one or both of an oxygen element and a nitrogen element after (c); and (e) repeating (c) and (d) are provided.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 9, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Hiroshi Ashihara, Toshiyuki Kikuchi
  • Patent number: 11158561
    Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: October 26, 2021
    Inventors: Pengyuan Zheng, David Ross Economy, Yongjun J. Hu, Kent H. Zhuang, Robert K. Grubbs
  • Patent number: 11145740
    Abstract: A ferroelectric field effect transistor (FeFET) device includes a semiconductor substrate and a 3D transistor. The 3D transistor includes drain and source electrodes; a channel structure that includes a channel body and a gate dielectric layer; and a gate electrode that is disposed on the gate dielectric layer and that is electrically isolated from the drain and source electrodes. The channel body is disposed between and connected to the drain and source electrodes. The gate dielectric layer covers the channel body, is made of crystalline hafnium zirconium oxide, and has a thickness ranging from 2 nm to 5 nm. The FeFET device has an on/off current ratio that is greater than 5×104.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: October 12, 2021
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Yung-Chun Wu, Fu-Ju Hou, Meng-Ju Tsai
  • Patent number: 11139175
    Abstract: A method includes anisotropically etching an etching target layer of a target object through an opening of the target object by generating plasma of a first gas within a processing vessel in which the target object is accommodated; and then forming a film on an inner surface of the opening by repeating a sequence comprising: a first process of supplying a second gas into the processing vessel; a second process of purging a space within the processing vessel; a third process of generating plasma of a third gas containing an oxygen atom within the processing vessel; and a fourth process of purging the space within the processing vessel. The first gas contains a carbon atom and a fluorine atom. The second gas contains an aminosilane-based gas. The etching target layer is a hydrophilic insulating layer containing silicon. Plasma of the first gas is not generated in the first process.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 5, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihide Kihara, Toru Hisamatsu, Masahiro Tabata
  • Patent number: 11092886
    Abstract: The present disclosure relates to a method for forming a pellicle for extreme ultraviolet lithography, the method comprising: forming a coating of a first material on a peripheral region of a main surface of a carbon nanotube pellicle membrane, the membrane including a carbon nanotube film, arranging the carbon nanotube pellicle membrane on a pellicle frame with the peripheral region facing a support surface of the pellicle frame, wherein the support surface of the pellicle frame is formed by a second material, and bonding together the coating of the carbon nanotube pellicle membrane and the pellicle support surface by pressing the carbon nanotube pellicle membrane and the pellicle support surface against each other. The present disclosure relates also relates to a method for forming a reticle system for extreme ultraviolet lithography.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: August 17, 2021
    Assignees: IMEC VZW, Imec USA Nanoelectronics Design Center
    Inventors: Marina Timmermans, Emily Gallagher, Ivan Pollentier, Hanns Christoph Adelmann, Cedric Huyghebaert, Jae Uk Lee
  • Patent number: 11075127
    Abstract: Disclosed are methods of and apparatuses and systems for depositing a film in a multi-station deposition apparatus. The methods may include: (a) providing a substrate to a first station of the apparatus, (b) adjusting the temperature of the substrate to a first temperature, (c) depositing a first portion of the material on the substrate while the substrate is at the first temperature in the first station, (d) transferring the substrate to the second station, (e) adjusting the temperature of the substrate to a second temperature, and (f) depositing a second portion of the material on the substrate while the substrate is at the second temperature, such that the first portion and the second portion exhibit different values of a property of the material. The apparatuses and systems may include a multi-station deposition apparatus and a controller having control logic for performing one or more of (a)-(f).
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: July 27, 2021
    Assignee: Lam Research Corporation
    Inventors: Seshasayee Varadarajan, Aaron R. Fellis, Andrew John McKerrow, James Samuel Sims, Ramesh Chandrasekharan, Jon Henri
  • Patent number: 11041239
    Abstract: A method for forming a SiC film on a target substrate by ALD, comprises: activating a surface of the target substrate by activation gas plasma which is plasmatized an activation gas; and forming a SiC film by supplying a source gas containing a precursor represented by a chemical formula RSiX13 or RSiHClX2 onto the target substrate whose the surface is activated by activating the surface of the target substrate, where, R is an organic group having an unsaturated bond, X1 is selected from a group consisting of H, F, Cl, Br and I, and X2 is one selected from a group consisting of Cl, Br and I.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: June 22, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Taiki Katou, Shuji Azumo, Yusaku Kashiwagi
  • Patent number: 11022582
    Abstract: A structure includes a substrate and a coating applied over the substrate, the coating containing particles sized between 30 and 250 micrometers. A proportion of the particles to the carrier is between 40 and 70 by volume percentage. In response to excitation of the structure by a controllable excitation source, a first instrument monitors behavior of the particles to determine a first condition of the structure thereby. In response to an absence of excitation of the structure by the controllable excitation source, a second instrument monitors behavior of the particles to determine a second condition of the structure thereby.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: June 1, 2021
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventor: George Ray Ely
  • Patent number: 11015243
    Abstract: A layer forming method according to one embodiment of the present invention comprises: a source gas dosing/pressurizing step of dosing a source gas into a chamber having a substrate loaded therein in a state in which the outlet of the chamber is closed, thereby increasing the pressure in the chamber and adsorbing the source gas onto the substrate; a first main purging step of purging the chamber, after the source gas dosing/pressurizing step; a reactive gas dosing step of dosing a reactive gas into the chamber, after the first main purging step; and a second main purging step of purging the chamber, after the reactive gas dosing step.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 25, 2021
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Myung Mo Sung, Jinwon Jung, Jin Seon Park
  • Patent number: 11004659
    Abstract: A method of manufacturing an amorphous carbon thin film is provided. The method includes the following steps: providing a substrate in a reaction chamber; flowing a precursor and a carrier gas into the reaction chamber; and performing a PECVD method to deposit the amorphous carbon thin film on the substrate. Wherein, the precursor includes a compound having a C?N functional group.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: May 11, 2021
    Assignee: National Chiao Tung University
    Inventors: Jih-Perng Leu, Jui-Min Chang
  • Patent number: 10985017
    Abstract: Described herein is a technique capable of improving a quality of a substrate processing performed using hydrogen peroxide. According to one aspect of the technique described herein, there is provided a method of manufacturing a semiconductor device including: (a) supplying a first process gas containing water and a first concentration of hydrogen peroxide to a substrate having a silicon-containing film formed on a surface thereof; and (b) supplying a second process gas containing water and a second concentration of hydrogen peroxide higher than the first concentration to the substrate after (a).
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: April 20, 2021
    Assignee: Kokusai Electric Corporation
    Inventors: Katsuhiko Yamamoto, Takuya Joda, Toru Kakuda, Sadayoshi Horii
  • Patent number: 10985042
    Abstract: A SiC substrate includes a first principal surface, a second principal surface disposed on a side opposite to the first principal surface, and an outer periphery connected to the first principal surface and the second principal surface, wherein a density of composite defects present at a peripheral edge portion of the SiC substrate, in which a hollow portion and a dislocation line extending from the hollow portion are connected to each other is equal to or greater than 0.01 pieces/cm2 and equal to or less than 10 pieces/cm2.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: April 20, 2021
    Assignee: SHOWA DENKO K.K.
    Inventors: Yoshitaka Nishihara, Koji Kamei
  • Patent number: 10957566
    Abstract: A system and method for wafer-level inspection using on-valve inspection detectors to detect defects on a semiconductor wafer surfaces during a semiconductor device manufacturing process is disclosed herein. In some exemplary embodiments, a method for wafer-level inspection includes: transporting a semiconductor wafer through a transfer port of a processing chamber; scanning a surface of the semiconductor wafer automatically using at least one on-valve inspection detector arranged on a vacuum valve providing access through the transfer port; generating at least one surface image of the surface of the semiconductor wafer; and analyzing the at least one surface image to detect defects on the surface of the semiconductor wafer.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mu-Lung Che, Fu Chiang Hsu
  • Patent number: 10950431
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Patent number: 10947126
    Abstract: Provided are a dielectric, a capacitor and a semiconductor device that include the dielectric, and a method of preparing the dielectric, the dielectric including: a composition represented by Formula 1; and an oxide including a perovskite type crystal structure having a polar space group or a non-polar space group other than a Pbnm space group: AxByO3-???<Formula 1> wherein, in Formula 1, A is a monovalent, divalent, or trivalent cation, B is a trivalent, tetravalent, or pentavalent cation, and 0.5?x?1.5, 0.5?y?1.5, and 0???0.5.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doh Won Jung, Chan Kwak, Euncheol Do, Hyeon Cheol Park, Daejin Yang, Taewon Jeong, Giyoung Jo
  • Patent number: 10941505
    Abstract: A method of forming a sp2 boron nitride (BN) layer on a surface of a substrate, the method comprising providing first and second precursors at the surface of the substrate, the first precursor being a source of boron and the second precursor being a source of nitrogen; heating the substrate to a temperature greater than a pyrolysis point for either of the first and second precursors; pyrolyzing the first precursor at the surface of the substrate; activating the second precursor at the surface of the substrate with the pyrolyzed first precursor; and adsorbing the pyrolyzed first precursor and the activated second precursor onto the surface of the substrate.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: March 9, 2021
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Michael R. Snure, Gene P. Siegel, Catalin S. Badescu, Cristian Ciobanu, Badri Narayanan
  • Patent number: 10943976
    Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: March 9, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Sundar Chetlur, Maxim Klebanov, Washington Lamar
  • Patent number: 10930550
    Abstract: Electronic devices and methods with a barrier layer and methods of forming the barrier layer are described. A substrate can be exposed to a metal precursor (e.g., a tantalum precursor), a reactant (e.g., ammonia) and an optional plasma to form a first thickness of the barrier layer. An optional aluminum film can be formed on the first barrier layer and a second barrier layer is formed on the first barrier layer to form barrier layer with an aluminum inter-layer.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: February 23, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Seshadri Ganguli, Sang Ho Yu, Lu Chen
  • Patent number: 10910200
    Abstract: A plasma processing apparatus includes a partition plate, an antenna, and a high frequency power supply. The partition plate has a plurality of holes and partitions an inside of the processing container into a plasma generation chamber and a processing chamber. The antenna generates plasma of the plasma excitation gas supplied into the plasma generation chamber. The high frequency power supply generates plasma of a precoating gas supplied into the plasma generation chamber and introduced into the processing chamber through the plurality of holes of the partition plate. The plasma processing apparatus performs a precoating on a surface of a partition plate on a side of the processing chamber by causing the high frequency power supply to generate plasma of the precoating gas before a plasma processing using the plasma of the plasma excitation gas is performed.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: February 2, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshiyuki Kikuchi, Akiyoshi Mitsumori
  • Patent number: 10894799
    Abstract: Provided are a novel disilylamine compound, a method for preparing same, and a composition for depositing a silicon-containing thin film including the same. A disilylamine compound of the present invention has excellent reactivity, is thermally stable, and has high volatility, and thus, is used as a silicon-containing precursor, thereby manufacturing a high-quality silicon-containing thin film.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: January 19, 2021
    Assignee: DNF CO., LTD.
    Inventors: Sung Gi Kim, Se Jin Jang, Byeong-il Yang, Joong Jin Park, Sang-Do Lee, Jeong Joo Park, Sam Dong Lee, Gun-Joo Park, Sang Ick Lee, Myong Woon Kim
  • Patent number: 10858758
    Abstract: A silicon carbide substrate (2) is positioned such that a principal surface of the silicon carbide substrate (2) is parallel to a plurality of injection holes (8) of a horizontal CVD apparatus arranged in a row. Source gas is fed from the plurality of injection holes (8) to epitaxially grow a silicon carbide epitaxial growth layer (10) on the principal surface of the silicon carbide substrate (2). The source gas fed from the plurality of injection holes (8) is divided into a plurality of system lines and controlled individually by separate mass flow controllers. A flow rate of the source gas on the principal surface of the silicon carbide substrate (2) is greater than 1 m/sec.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: December 8, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Akihito Ohno
  • Patent number: 10861732
    Abstract: An electrostatic chuck includes: an insulating plate consisting of alumina, and YAG (Yttrium Aluminum Garnet) added with cerium, and configured to mount a substrate thereon; and an electrode which is embedded in the insulating plate and configured to generate electrostatic force for adsorbing the substrate.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: December 8, 2020
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Masaya Tsuno, Tomotake Minemura, Shigeaki Suganuma
  • Patent number: 10851460
    Abstract: In example implementations, a vapor chamber is provided. The vapor chamber includes a metallic housing. A nickel coating is applied on inside walls of the metallic housing. A silica derived carbon nanotube (CNT) aerogel coating is applied on the nickel coating on the inside walls of the metallic housing. The silica derived CNT aerogel coating is sprayed onto the nickel coating, dried and cured.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: December 1, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kuan-Ting Wu, Kevin Voss, Chi-Hao Chang
  • Patent number: 10847365
    Abstract: A method of forming, on a substrate having a recess pattern, a silicon carbide film having a reflective index of 2.3 or higher as measured at 633 nm, includes (i) supplying an organosilane precursor in a pulse to a reaction space where the substrate is placed, which precursor has a formula of RSiH3 wherein R is a hydrocarbon-containing moiety including at least one unsaturated bond; (ii) continuously supplying a plasma-generating gas to the reaction space, which plasma-generating gas is selected from the group consisting of inert gases and hydride gases; (iii) continuously applying RF power to the reaction space to generate a plasma which excites the precursor; and (iv) repeating steps (i) through (iii), thereby forming a silicon carbide film on the substrate, which silicon carbide film has a reflective index of 2.3 or higher as measured at 633 nm.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: November 24, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Atsuki Fukazawa, Masaru Zaitsu
  • Patent number: 10825766
    Abstract: A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Young Kim, Kyu Hee Han, Sung Bin Park, Yeong Gil Kim, Jong Min Baek, Kyoung Woo Lee, Deok Young Jung
  • Patent number: 10811516
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Che-Cheng Chang, Mu-Tsang Lin, Tung-Wen Cheng, Zhe-Hao Zhang
  • Patent number: 10811477
    Abstract: A flexible organic light emitting display device includes a flexible substrate, an insulating layer, a polymer flat layer, an anode, and a pixel isolation layer. The pixel isolation layer and the anode are alternately disposed on the polymer flat layer, and the pixel isolation layer includes a first pixel isolation layer disposed on a bent area and a second pixel isolation layer disposed on a flat area. A thickness of the first pixel isolation layer is greater than a thickness of the second pixel isolation layer. A method of manufacturing an organic light emitting display device is further provided by increasing the thickness of the pixel isolation layer of the bent area, mechanical stress generated by a flexible organic light emitting diode (OLED) display device during bending can be reduced, thereby improving the bending performance of the flexible OLED display device.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: October 20, 2020
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Bo Wang
  • Patent number: 10793947
    Abstract: A deposited cobalt composition is described, including cobalt and one or more alloy component that is effective in combination with cobalt to enhance adhesion to a substrate when exposed on the substrate to variable temperature and/or delaminative force conditions, as compared to corresponding elemental cobalt, wherein the one or more alloy component is selected from the group consisting of boron, phosphorous, tin, antimony, indium, and gold. Such deposited cobalt composition may be employed for metallization in semiconductor devices and device precursor structures, flat-panel displays, and solar panels, and provides highly adherent metallization when the metallized substrate is subjected to thermal cycling and/or chemical mechanical planarization operations in the manufacturing of the semiconductor, flat-panel display, or solar panel product.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: October 6, 2020
    Assignee: ENTEGRIS, INC.
    Inventors: Philip S. H. Chen, Bryan C. Hendrix, Thomas H. Baum
  • Patent number: 10777415
    Abstract: Hydrogen annealing for heating a semiconductor wafer on which a thin film containing a dopant is deposited to an annealing temperature under an atmosphere containing hydrogen is performed. A native oxide film is inevitably formed between the thin film containing the dopant and the semiconductor wafer, however, by performing hydrogen annealing, the dopant atoms diffuse relatively easily in the native oxide film and accumulate at the interface between the front surface of the semiconductor wafer and the native oxide film. Subsequently, the semiconductor wafer is preheated to a preheating temperature under a nitrogen atmosphere, and then, flash heating treatment in which the front surface of the semiconductor wafer is heated to a peak temperature for less than one second is performed. The dopant atoms are diffused and activated in a shallow manner from the front surface of the semiconductor wafer, thus, the low-resistance and extremely shallow junction is obtained.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: September 15, 2020
    Assignee: SCREEN HOLDINGS CO., LTD.
    Inventors: Kazuhiko Fuse, Hikaru Kawarazaki, Hideaki Tanimura, Shinichi Kato
  • Patent number: 10712659
    Abstract: The present disclosure relates to a method for forming a carbon nanotube pellicle membrane for an extreme ultraviolet lithography reticle, the method comprising: bonding together overlapping carbon nanotubes of at least one carbon nanotube film by pressing the at least one carbon nanotube film between a first pressing surface and a second pressing surface, thereby forming a free-standing carbon nanotube pellicle membrane. The present disclosure also relates to a method for forming a pellicle for extreme ultraviolet lithography and for forming a reticle system for extreme ultraviolet lithography respectively.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 14, 2020
    Assignees: IMEC VZW, Imec USA Nanoelectronics Design Center
    Inventors: Emily Gallagher, Cedric Huyghebaert, Ivan Pollentier, Hanns Christoph Adelmann, Marina Timmermans, Jae Uk Lee
  • Patent number: 10707073
    Abstract: Examples of a film forming method includes repeating first processing and second processing in this order a plurality of times, wherein the first processing supplies material-1 having one silicon atom per molecule onto a substrate, and then generates plasma while reactant gas is introduced, thereby forming a silicon oxide film on the substrate, and the second processing provides material-2 having two or more silicon atoms per molecule onto the substrate, and then generates plasma while no reactant gas is introduced, thereby forming a double silicon compound on the substrate.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: July 7, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Yoshio Susa, Yuko Kengoyama, Taishi Ebisudani
  • Patent number: 10707116
    Abstract: Implementations disclosed herein relate to methods for forming and filling trenches in a substrate with a flowable dielectric material. In one implementation, the method includes subjecting a substrate having at least one trench to a deposition process to form a flowable layer over a bottom surface and sidewall surfaces of the trench in a bottom-up fashion until the flowable layer reaches a predetermined deposition thickness, subjecting the flowable layer to a first curing process, the first curing process being a UV curing process, subjecting the UV cured flowable layer to a second curing process, the second curing process being a plasma or plasma-assisted process, and performing sequentially and repeatedly the deposition process, the first curing process, and the second curing process until the plasma cured flowable layer fills the trench and reaches a predetermined height over a top surface of the trench.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: July 7, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jingmei Liang, Yong Sun, Jinrui Guo, Praket P. Jha, Jung Chan Lee, Tza-Jing Gung, Mukund Srinivasan
  • Patent number: 10707074
    Abstract: By sequentially performing, a plurality of times, a step of supplying a mixed gas of an organic metal-containing source gas and an inert gas to a process chamber housing a substrate by adjusting a flow velocity of the mixed gas on the substrate to 7.8 m/s to 15.6 m/s and adjusting a partial pressure of the organic metal-containing source gas in the mixed gas to 0.167 to 0.3, a step of exhausting the process chamber, a step of supplying an oxygen-containing gas to the process chamber, and a step of exhausting the process chamber, a metal oxide film is formed on the substrate.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 7, 2020
    Assignee: Kokusai Electric Corporation
    Inventors: Yoshimasa Nagatomi, Hirohisa Yamazaki