Insulative Material Deposited Upon Semiconductive Substrate Patents (Class 438/778)
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Patent number: 12234549Abstract: Methods for in situ seasoning of process chamber components, such as electrodes are described. In an embodiment, the method includes depositing a silicon oxide film over the process chamber component and converting the silicon oxide film to a silicon-carbon-containing film. The silicon-carbon-containing film forms a protective film over the process chamber components and is resistant to plasma processing and/or dry etch cleaning. The coatings has high density, good emissivity control, and reduces risk of device property drift.Type: GrantFiled: May 5, 2023Date of Patent: February 25, 2025Assignee: Applied Materials, Inc.Inventors: Sarah Michelle Bobek, Abdul Aziz Khaja, Ratsamee Limdulpaiboon, Kwangduk Douglas Lee
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Patent number: 12209303Abstract: A vapor deposition apparatus is provided. The vapor deposition apparatus includes a tank for providing a liquefied material, a first unit having an alterable first volume, the first unit including a first actuator and including a first line to be in fluid communication with the tank. Further, the vapor deposition apparatus includes a second unit having an alterable second volume, the second unit including a second actuator and including a second line to be in fluid communication with the tank. The vapor deposition apparatus includes an evaporation arrangement, the evaporation arrangement being in fluid communication with the first unit and the second unit. The first actuator and the second actuator are configured to alternatingly provide a force to the alterable first volume and the alterable second volume for providing the liquefied material to the evaporation arrangement.Type: GrantFiled: December 28, 2021Date of Patent: January 28, 2025Assignee: Applied Materials, Inc.Inventors: Andreas Sauer, Volker Hacker, Thomas Deppisch, Ralf Scheidt
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Patent number: 12176243Abstract: There is provided a method of filling one or more recesses by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, introducing a second reactant to the substrate with a second dose, wherein the first and the second doses overlap in an overlap area where the first and second reactants react and leave an initially substantially unreacted area where the first and the second areas do not overlap; introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant to form deposited material; and etching the deposited material. An apparatus for filling a recess is also disclosed.Type: GrantFiled: December 20, 2022Date of Patent: December 24, 2024Assignee: ASM IP Holding B.V.Inventors: Viljami Pore, Zecheng Liu
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Patent number: 12148610Abstract: A composition, comprising: a carbon backbone polymer; a first crosslinker; and a second crosslinker. The first crosslinker partially crosslinks the carbon backbone polymer at a temperature ranging from 100° C. to 170° C., and the second crosslinker crosslinks the carbon backbone polymer at a temperature ranging from 180° C. to 300° C. The first crosslinker is one or more selected from the group consisting of A-(OR)x, A-(NR)x, where A is a monomer, oligomer, or a second polymer having a molecular weight ranging from 100 to 20,000, R is an alkyl group, cycloalkyl group, cycloalkylepoxy group, or C3-C15 heterocyclic group, OR is an alkyloxy group, cycloalkyloxy group, carbonate group, alkylcarbonate group, alkyl carboxylate group, tosylate group, or mesylate group, NR is an alkylamide group or an alkylamino group, and x ranges from 2 to 1000. The second crosslinker is different from the first crosslinker.Type: GrantFiled: June 29, 2023Date of Patent: November 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jing Hong Huang, Ching-Yu Chang, Wei-Han Lai
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Patent number: 12142515Abstract: The present disclosure relates to a substrate processing apparatus including: a chamber; a supporting part coupled to the chamber to support the substrate; a lid disposed on the supporting part and coupled to the chamber; a purge gas injection unit coupled to the lid to inject a purge gas to a processing space between the lid and the supporting part, for dividing the processing space into a plurality of processing regions; a shield disposed between the lid and the supporting part and coupled to the lid; a first injection unit injecting a first gas to a first processing region of the processing regions; a second injection unit injecting the first gas to the first processing region at a position apart from the first injection unit; and a first partition wall part coupled to the shield so that a first injection region disposed under the first injection unit, a second injection region disposed under the second injection unit, and a first separation space between the first injection region and the second injectionType: GrantFiled: December 26, 2019Date of Patent: November 12, 2024Assignee: JUSUNG ENGINEERING CO., LTD.Inventors: DongHyuk Oh, Su-Young Kwon, JongSik Kim, Chul Joo Hwang
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Patent number: 12142480Abstract: Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more recessed features along the substrate and a seam or void may be defined by the silicon-containing material within at least one of the one or more recessed features along the substrate. The methods may also include treating the silicon-containing material with a hydrogen-containing gas, such as plasma effluents of the hydrogen-containing gas, which may cause a size of the seam or void to be reduced.Type: GrantFiled: August 13, 2021Date of Patent: November 12, 2024Assignee: Applied Materials, Inc.Inventors: Qinghua Zhao, Rui Cheng, Ruiyun Huang, Dong Hyung Lee, Aykut Aydin, Karthik Janakiraman
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Patent number: 12129546Abstract: In accordance with some embodiments herein, methods and apparatuses for flowable deposition of thin films are described. Some embodiments herein relate to cyclical processes for gap-fill in which deposition is followed by a thermal anneal and repeated. In some embodiments, the deposition and thermal anneal are carried out in separate station. In some embodiments second module is heated to a higher temperature than the first station. In some embodiments, the thermal anneal comprises RTA.Type: GrantFiled: October 18, 2021Date of Patent: October 29, 2024Assignee: ASM IP Holding B.V.Inventors: Shinya Yoshimoto, Takahiro Onuma, Makoto Igarashi, Yukihiro Mori, Hideaki Fukuda, Rene Henricus Jozef Vervuurt, Timothee Blanquart
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Patent number: 12068195Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.Type: GrantFiled: June 7, 2023Date of Patent: August 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
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Patent number: 12018364Abstract: Methods for forming coating films comprising germanium oxide are disclosed. In some embodiments, the films are super-conformal to a feature on the surface of a substrate. The films are deposited by exposing a substrate surface to a germane precursor and an oxidant simultaneously. The germane precursor may be flowed intermittently. The substrate may also be exposed to a second oxidant to increase the relative concentration of oxygen within the super-conformal film.Type: GrantFiled: December 11, 2020Date of Patent: June 25, 2024Assignee: Applied Materials, Inc.Inventors: Huiyuan Wang, Susmit Singha Roy, Takehito Koshizawa, Bo Qi, Abhijit Basu Mallick
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Patent number: 11990322Abstract: The present disclosure relates to a ceramic susceptor. The ceramic susceptor of the present disclosure may include: an insulating plate in which a RF electrode is disposed; a shaft connected to the insulating plate at one end and comprising a separator at a remaining end; a connection mount having an upper portion connected to the remaining end of the shaft; a first rod and a second rod connected to the RF electrode and penetrating the separator to extend into the connection mount; and a connection member disposed in the connection mount and connecting the first rod and the second rod extending into the connection mount to a draw-in rod, wherein the connection member may include an elastic member configured to absorb a difference in deformation due to heat among the first rod, the second rod, and the draw-in rod.Type: GrantFiled: July 31, 2023Date of Patent: May 21, 2024Assignee: MICO CERAMICS LTD.Inventors: Haneum Bae, Jusung Lee
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Patent number: 11972944Abstract: A film having filling capability of a patterned recess on a surface of a substrate is deposited by forming a viscous material in a gas phase by striking a plasma in a chamber filled with a volatile precursor that can be polymerized within certain parameter ranges which include a partial pressure of the precursor during a plasma strike and substrate temperature.Type: GrantFiled: October 21, 2022Date of Patent: April 30, 2024Assignee: ASM IP Holding B.V.Inventor: Timothee Julien Vincent Blanquart
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Patent number: 11821071Abstract: Molybdenum-containing films are deposited on semiconductor substrates using reactions of molybdenum-containing precursors in ALD and CVD processes. In some embodiments, the precursors can be used for deposition of molybdenum metal films with low levels of incorporation of carbon and nitrogen. In some embodiments, the films are deposited using fluorine-free precursors in a presence of exposed silicon-containing layers without using etch stop layers. The precursor, in some embodiments, is a compound that includes molybdenum, at least one halogen that forms a bond with molybdenum, and at chamber least one organic ligand that includes an element selected from the group consisting of N, O, and S, that forms a bond with molybdenum, In another aspect, the precursor is a molybdenum, compound with at least one sulfur-containing ligand, and preferably no molybdenum-carbon bonds.Type: GrantFiled: March 6, 2020Date of Patent: November 21, 2023Assignee: Lam Research CorporationInventor: Kyle Jordan Blakeney
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Patent number: 11795550Abstract: A method of etching a metal barrier layer and a metal layer is provided. The method includes forming the metal barrier layer and the metal layer on a substrate, and using an etching composition to etch the metal barrier layer and the metal layer. The etching composition may include an oxidant selected from nitric acid, bromic acid, iodic acid, perchloric acid, perbromic acid, periodic acid, sulfuric acid, methane sulfonic acid, p-toluenesulfonic acid, benzenesulfonic acid, or a combination thereof, a metal etching inhibitor including a compound expressed by Chemical Formula 1, and a metal oxide solubilizer selected from phosphoric acid, phosphate, carboxylic acid having 3 to 20 carbon atoms, or a combination thereof.Type: GrantFiled: May 6, 2021Date of Patent: October 24, 2023Assignees: SAMSUNG ELECTRONICS CO., LTD., SOULBRAIN CO., LTD.Inventors: Jungah Kim, Mihyun Park, Jinwoo Lee, Keonyoung Kim, Hyosan Lee, Hoon Han, Jin Uk Lee, Jung Hun Lim
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Patent number: 11776858Abstract: A method of manufacturing a semiconductor device includes preparing etched mapping data by measuring an etching amount of a wafer subjected to an etching process, determining an error region in which the etching amount of the wafer is outside of a reference value, based on the etched mapping data, compensating distribution of an electrical field applied to the wafer, and compensating exhaust distribution of a process gas, changed by the compensating distribution of an electrical field.Type: GrantFiled: February 24, 2020Date of Patent: October 3, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Joonsung Lee, Suhong Kim, Youngwon Shin, Hyungchul Cho, Jaehyoung Lee, Hyunjae Jung
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Patent number: 11778891Abstract: Disclosed is a preparation method for crosslinked nanoparticle film. The preparation method comprises: dispersing nanoparticles in a solvent and uniformly mixing same, so as to obtain a nanoparticle solution; and using the nanoparticle solution to prepare a nanoparticle thin film by means of a solution method, and introducing a gas combination to promote a crosslinking reaction, so as to obtain a crosslinked nanoparticle thin film. By introducing a gas combination during film formation of nanoparticles, the present disclosure promotes the crosslinking among particles, and thus increases the electrical coupling among particles, lowers the potential barrier of carrier transmission, and increases the carrier mobility, thereby greatly improving the electrical properties of the thin film.Type: GrantFiled: July 27, 2022Date of Patent: October 3, 2023Assignee: TCL TECHNOLOGY GROUP CORPORATIONInventors: Song Chen, Lei Qian, Yixing Yang, Weiran Cao, Chaoyu Xiang
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Patent number: 11753720Abstract: A film forming apparatus for forming a film on a substrate by transferring a source gas generated from a low-vapor-pressure source to a process container by a carrier gas includes: a source container configured to receive and heat the low-vapor-pressure source; a first gas pipe configured to supply the carrier gas to the source container; a second gas pipe connecting the source container and the process container; a first opening and closing valve provided in the second gas pipe; and a measurement part configured to measure a flow rate of the source gas flowing through the second gas pipe, wherein the second gas pipe is disposed on a central axis of the process container, and wherein the source container is offset with respect to the central axis of the process container.Type: GrantFiled: July 17, 2019Date of Patent: September 12, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Yuichi Furuya, Masayuki Tanaka
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Patent number: 11710659Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.Type: GrantFiled: December 27, 2021Date of Patent: July 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
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Patent number: 11692269Abstract: A plasma processing apparatus includes: a processing container having a cylindrical shape; a pair of plasma electrodes arranged along the longitudinal direction of the processing container while facing each other; and a radio-frequency power supply configured to supply a radio-frequency power to the pair of plasma electrodes. In the pair of plasma electrodes, an inter-electrode distance at a position distant from a power feed position to which the radio-frequency power is supplied is longer than an inter-electrode distance at the power feed position.Type: GrantFiled: May 26, 2020Date of Patent: July 4, 2023Assignee: TOKYO ELECTRON LIMITEDInventors: Hiroyuki Matsuura, Kiyotaka Ishibashi
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Patent number: 11676918Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.Type: GrantFiled: February 22, 2022Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
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Patent number: 11670608Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.Type: GrantFiled: July 23, 2020Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fan Huang, Hui-Chi Chen, Chih-Sheng Li, Chih-Hung Lu, Dian-Hau Chen, Yen-Ming Chen
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Patent number: 11664246Abstract: A method for thermally processing a substrate having a surface region and a buried region with a pulsed light beam, the substrate presenting an initial temperature-depth profile and the surface region presenting an initial surface temperature, including steps of: illuminating the surface region with a preliminary pulse so that it generates an amount of heat and reaches a predetermined preliminary surface temperature; and illuminating the surface region with a subsequent pulse after a time interval so that it reaches a predetermined subsequent surface temperature. The time interval is determined such that the surface region reaches a predetermined intermediate surface temperature greater than the initial surface temperature, such that during the time interval, the amount of heat is diffused within the substrate down to a predetermined depth so that the substrate presents a predetermined intermediate temperature-depth profile.Type: GrantFiled: December 3, 2019Date of Patent: May 30, 2023Assignee: LASER SYSTEMS & SOLUTIONS OF EUROPEInventor: Fulvio Mazzamuto
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Patent number: 11658062Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.Type: GrantFiled: May 13, 2019Date of Patent: May 23, 2023Assignee: TESSERA LLCInventors: Kangguo Cheng, Thomas J. Haigh, Juntao Li, Eric G. Liniger, Sanjay C. Mehta, Son V. Nguyen, Chanro Park, Tenko Yamashita
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Patent number: 11613808Abstract: Exemplary semiconductor processing methods may include forming a seasoning film on a heater of a processing chamber by a first deposition process. The method may include performing a hardmask deposition process in the processing chamber. The method may include cleaning the processing chamber by a first cleaning process. The method may include monitoring a gas produced during the first cleaning process. The method may include cleaning the processing chamber using a second cleaning process different from the first cleaning process. The method may also include monitoring the gas produced during the second cleaning process.Type: GrantFiled: October 22, 2020Date of Patent: March 28, 2023Assignee: Applied Materials, Inc.Inventors: Jiheng Zhao, Abdul Aziz Khaja, Prashant Kumar Kulshreshtha, Fang Ruan
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Patent number: 11566325Abstract: Methods for plasma enhanced chemical vapor deposition (PECVD) of silicon carbonitride films are described. A flowable silicon carbonitride film is formed on a substrate surface by exposing the substrate surface to a precursor and a reactant, the precursor having a structure of general formula (I) or general formula (II) wherein R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, and R12 are independently selected from hydrogen (H), substituted or unsubstituted alkyl, substituted or unsubstituted alkoxy, substituted or unsubstituted vinyl, silane, substituted or unsubstituted amine, or halide; purging the processing chamber of the silicon precursor, and then exposing the substrate to an ammonia plasma.Type: GrantFiled: December 14, 2020Date of Patent: January 31, 2023Assignee: Applied Materials, Inc.Inventors: Mei-Yee Shek, Bhargav S. Citla, Joshua Rubnitz, Jethro Tannos, Chentsau Chris Ying, Srinivas D. Nemani, Ellie Y. Yieh
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Patent number: 11532475Abstract: A method includes placing a semiconductor substrate in a deposition chamber, wherein the semiconductor substrate includes a trench, and performing an atomic layer deposition (ALD) process to deposit a dielectric material within the trench, including flowing a first precursor of the dielectric material into the deposition chamber as a gas phase; flowing a second precursor of the dielectric material into the deposition chamber as a gas phase; and controlling the pressure and temperature within the deposition chamber such that the second precursor condenses on surfaces within the trench as a liquid phase of the second precursor, wherein the liquid phase of the second precursor has capillarity.Type: GrantFiled: July 30, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Ting Ko, Chi On Chui
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Patent number: 11515144Abstract: Methods for filling the gap of a semiconductor feature comprising exposure of a substrate surface to a precursor and reactant and an anneal environment to decrease the wet etch rate ratio of the deposited film and fill the gap.Type: GrantFiled: December 9, 2016Date of Patent: November 29, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Keiichi Tanaka, Andrew Short, Mandyam Sriram, Srinivas Gandikota
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Patent number: 11482412Abstract: A film having filling capability of a patterned recess on a surface of a substrate is deposited by forming a viscous material in a gas phase by striking a plasma in a chamber filled with a volatile precursor that can be polymerized within certain parameter ranges which include a partial pressure of the precursor during a plasma strike and substrate temperature.Type: GrantFiled: January 18, 2019Date of Patent: October 25, 2022Assignee: ASM IP Holding B.V.Inventor: Timothee Julien Vincent Blanquart
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Patent number: 11462398Abstract: Embodiments of the present invention are directed to forming a ternary compound using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor includes a first metal and a first ligand. The second precursor includes a second metal and a second ligand. The second ligand is selected based on the first ligand to target a second metal uptake. A substrate is exposed to the first precursor during a first pulse of an ALD cycle and the substrate is exposed to the second precursor during a second pulse of the ALD cycle, the second pulse occurring after the first pulse. The substrate is exposed to a third precursor (e.g., an oxidant) during a third pulse of the ALD cycle. The ternary compound can include a ternary oxide film.Type: GrantFiled: July 17, 2019Date of Patent: October 4, 2022Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ULVAC, INCInventors: Martin Michael Frank, John Rozen, Yohei Ogawa
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Patent number: 11437576Abstract: A method and a deposition apparatus of fabricating a display device is disclosed. The method may include providing a target substrate in an internal space of a chamber of a deposition apparatus, depositing a first material which includes an organic material and a deposition material coupled to each other, on the target substrate to form preliminary deposition layer, performing a preliminary decomposition step to remove the organic material, and performing a decomposition step to remove the organic material remained in the preliminary deposition layer and to form a deposition layer. The preliminary decomposition step may include heating the preliminary deposition layer, and the decomposition step may include injecting a second material containing an organic solvent onto the preliminary deposition layer.Type: GrantFiled: September 23, 2019Date of Patent: September 6, 2022Inventor: Seonghyeon Cheon
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Patent number: 11430878Abstract: A method includes etching a semiconductor substrate to form a plurality of semiconductor fins. The semiconductor fins are etched to form a recess. An epitaxy structure is grown in the recess. The epitaxy structure has a W-shape cross section. A capping layer is formed over the epitaxy structure. The capping layer is at least conformal to a sidewall of the epitaxy structure. The capping layer is etched to expose a top surface of the epitaxy structure. A first portion of the capping layer remains over the sidewall of the epitaxy structure after etching the capping layer. A contact is formed in contact with the exposed top surface of the epitaxy structure and the first portion of the capping layer.Type: GrantFiled: August 14, 2020Date of Patent: August 30, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Lilly Su, Yang-Tai Hsiao
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Patent number: 11424201Abstract: A method of forming an aluminum oxide layer is provided. The method includes providing a metal surface including at least one metal of a group of metals, the group of metals consisting of copper, aluminum, palladium, nickel, silver, and alloys thereof. The method further includes depositing an aluminum oxide layer on the metal surface by atomic layer deposition, wherein a maximum processing temperature during the depositing is 280° C., such that the aluminum oxide layer is formed with a surface having a liquid solder contact angle of less than 40°.Type: GrantFiled: June 19, 2018Date of Patent: August 23, 2022Assignee: Infineon Technologies AGInventors: Michael Rogalli, Johann Gatterbauer, Wolfgang Lehnert, Kurt Matoy, Evelyn Napetschnig, Manfred Schneegans, Bernhard Weidgans
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Patent number: 11380544Abstract: A laser annealing device includes a stage, a laser generator, and a reflective member. The stage supports a substrate with a thin film formed thereon to be processed, and may be moved in a first direction at a set or predetermined speed. The laser generator irradiates a first area of the thin film with a laser beam while the stage is moved. The reflective member reflects a part of the laser beam, which is reflected from the first area of the thin film, to a second area of the thin film. The first area and the second area are spaced apart from each other.Type: GrantFiled: August 19, 2020Date of Patent: July 5, 2022Assignee: Samsung Display Co., Ltd.Inventors: Dong-Min Lee, Ji-Hwan Kim, Jongoh Seo, Byung Soo So
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Patent number: 11371136Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing a substrate to a blocking molecule to selectively deposit a blocking layer on the first surface. The blocking layer is exposed to a polymer initiator to form a networked blocking layer. A layer is selectively formed on the second surface. The blocking layer inhibits deposition on the first surface. The networked layer may then optionally be removed.Type: GrantFiled: September 19, 2018Date of Patent: June 28, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Bhaskar Jyoti Bhuyan, Mark Saly, David Thompson, Lakmal C. Kalutarage, Rana Howlader
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Patent number: 11367613Abstract: Methods and precursors for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD), such as plasma enhanced ALD. In some embodiments, deposited silicon nitride can be treated with a plasma treatment. The plasma treatment can be a nitrogen plasma treatment. In some embodiments the silicon precursors for depositing the silicon nitride comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%). In some embodiments, a method for depositing silicon nitride films comprises a multi-step plasma treatment.Type: GrantFiled: August 7, 2020Date of Patent: June 21, 2022Assignee: ASM IP HOLDING B.V.Inventors: Shang Chen, Viljami Pore, Ryoko Yamada, Antti Juhani Niskanen
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Patent number: 11342479Abstract: Disclosed herein are techniques relating to wafer-to-wafer bonding for manufacturing light-emitting diodes (LEDs). In some embodiments, a method includes reducing bowing of a layered structure including a semiconductor material and a substrate on which the semiconductor material is formed by generating breakages, fractures, or at least one region of weakened bonding within the layered structure. The method also includes bonding a base wafer to the semiconductor material, removing the substrate from the semiconductor material, and forming a plurality of trenches through the semiconductor material to produce a plurality of LEDs.Type: GrantFiled: September 4, 2019Date of Patent: May 24, 2022Assignee: FACEBOOK TECHNOLOGIES, LLCInventors: William Padraic Henry, Allan Pourchet
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Patent number: 11335791Abstract: A method of fabricating a semiconductor device, including performing the following steps in the following sequence: providing a substrate including first and second gate regions separated by a trench formed in the substrate and growing a thin oxide layer on each of the first and second gate regions. The method further includes removing the thin oxide layer from the second gate region, and growing a thick oxide layer on the second gate region.Type: GrantFiled: May 21, 2019Date of Patent: May 17, 2022Assignee: X-FAB SARAWAK SDN. BHD.Inventors: Jerry Liew, Jee Chang Lai
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Patent number: 11289369Abstract: A method of forming a low-k dielectric layer with barrier properties is disclosed. The method comprises forming a dielectric layer by PECVD which is doped with one or more of boron, nitrogen or phosphorous. The dopant gas of some embodiments may be coflowed with the other reactants during deposition.Type: GrantFiled: June 8, 2020Date of Patent: March 29, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Yi Ding, Shaunak Mukherjee, Bo Xie, Kang Sub Yim, Deenesh Padhi
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Patent number: 11282845Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.Type: GrantFiled: August 24, 2017Date of Patent: March 22, 2022Assignee: Micron Technology, Inc.Inventors: Jun Fang, Fei Wang, Saniya Rathod, Rutuparna Narulkar, Matthew Park, Matthew J. King
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Patent number: 11276573Abstract: An exemplary method may include delivering a boron-containing precursor to a processing region of a semiconductor processing chamber. The method may also include forming a plasma within the processing region of the semiconductor processing chamber from the boron-containing precursor. The method may further include depositing a boron-containing material on a substrate disposed within the processing region of the semiconductor processing chamber. The boron-containing material may include greater than 50% of boron. In some embodiments, the boron-containing material may include substantially all boron. In some embodiments, the method may further include delivering at least one of a germanium-containing precursor, an oxygen-containing precursor, a silicon-containing precursor, a phosphorus-containing precursor, a carbon-containing precursor, and/or a nitrogen-containing precursor to the processing region of the semiconductor processing chamber.Type: GrantFiled: December 4, 2019Date of Patent: March 15, 2022Assignee: Applied Materials, Inc.Inventors: Bo Qi, Zeqing Shen, Abhijit Mallick
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Patent number: 11239310Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.Type: GrantFiled: June 1, 2020Date of Patent: February 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
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Patent number: 11226554Abstract: An imprint apparatus executes imprint processing of curing imprint material in a state in which the imprint material supplied onto a substrate and a mold are in contact with each other. The imprint apparatus includes a modulator configured to modulate incident light, a first optical system configured to guide first light from a first light source to the modulator, and second light from a second light source that has a wavelength different from that of the first light to the modulator, and a second optical system configured to guide modulated light modulated by the modulator to the substrate.Type: GrantFiled: November 4, 2019Date of Patent: January 18, 2022Assignee: CANON KABUSHIKI KAISHAInventors: Kenichi Kobayashi, Tatsuya Arakawa
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Patent number: 11181768Abstract: A display device includes a display panel; a color conversion display panel overlapping the display panel; and a polarizing plate positioned between the display panel and the color conversion display panel, wherein the polarizing plate may include a polarization film and a transfer layer overlapping the polarization film, the transfer layer may be positioned between the polarization film and the display panel, and the transfer layer may include an acrylamide-based compound.Type: GrantFiled: January 1, 2018Date of Patent: November 23, 2021Assignee: Samsung Display Co., Ltd.Inventors: Sang-Gil Lee, Byung-Gon Kum, Eun Guk Lee
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Patent number: 11181819Abstract: Systems and methods for shaping a film by: depositing a formable material on a field of a substrate; and positioning a template relative to the field. The template has a mesa with a shaping surface and mesa sidewalls surround the shaping surface. The shaping may further comprise contacting the formable material with the shaping surface. The formable material may spread when the shaping surface is in contact with the formable material. The shaping may comprise exposing the formable material to a curing dose of actinic radiation after the formable material has spread to the edge of the field. A spatial distribution of the curing dose may be such that an interior dose applied at an interior of the field may be greater than a sidewall dose that is incident on the mesa sidewalls.Type: GrantFiled: May 31, 2019Date of Patent: November 23, 2021Assignee: CANON KABUSHIKI KAISHAInventors: Amir Tavakkoli Kermani Ghariehali, Mehul N. Patel, Edward Brian Fletcher
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Patent number: 11170996Abstract: (a) Loading a substrate into a process chamber; (b) supplying a processing gas including H2O-containing radicals to the substrate; (c) supplying a gas including a halogen element; (d) supplying a gas including one or both of an oxygen element and a nitrogen element after (c); and (e) repeating (c) and (d) are provided.Type: GrantFiled: February 13, 2020Date of Patent: November 9, 2021Assignee: KOKUSAI ELECTRIC CORPORATIONInventors: Hiroshi Ashihara, Toshiyuki Kikuchi
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Patent number: 11158561Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.Type: GrantFiled: May 1, 2019Date of Patent: October 26, 2021Inventors: Pengyuan Zheng, David Ross Economy, Yongjun J. Hu, Kent H. Zhuang, Robert K. Grubbs
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Patent number: 11145740Abstract: A ferroelectric field effect transistor (FeFET) device includes a semiconductor substrate and a 3D transistor. The 3D transistor includes drain and source electrodes; a channel structure that includes a channel body and a gate dielectric layer; and a gate electrode that is disposed on the gate dielectric layer and that is electrically isolated from the drain and source electrodes. The channel body is disposed between and connected to the drain and source electrodes. The gate dielectric layer covers the channel body, is made of crystalline hafnium zirconium oxide, and has a thickness ranging from 2 nm to 5 nm. The FeFET device has an on/off current ratio that is greater than 5×104.Type: GrantFiled: June 30, 2020Date of Patent: October 12, 2021Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Yung-Chun Wu, Fu-Ju Hou, Meng-Ju Tsai
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Patent number: 11139175Abstract: A method includes anisotropically etching an etching target layer of a target object through an opening of the target object by generating plasma of a first gas within a processing vessel in which the target object is accommodated; and then forming a film on an inner surface of the opening by repeating a sequence comprising: a first process of supplying a second gas into the processing vessel; a second process of purging a space within the processing vessel; a third process of generating plasma of a third gas containing an oxygen atom within the processing vessel; and a fourth process of purging the space within the processing vessel. The first gas contains a carbon atom and a fluorine atom. The second gas contains an aminosilane-based gas. The etching target layer is a hydrophilic insulating layer containing silicon. Plasma of the first gas is not generated in the first process.Type: GrantFiled: December 20, 2019Date of Patent: October 5, 2021Assignee: TOKYO ELECTRON LIMITEDInventors: Yoshihide Kihara, Toru Hisamatsu, Masahiro Tabata
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Patent number: 11092886Abstract: The present disclosure relates to a method for forming a pellicle for extreme ultraviolet lithography, the method comprising: forming a coating of a first material on a peripheral region of a main surface of a carbon nanotube pellicle membrane, the membrane including a carbon nanotube film, arranging the carbon nanotube pellicle membrane on a pellicle frame with the peripheral region facing a support surface of the pellicle frame, wherein the support surface of the pellicle frame is formed by a second material, and bonding together the coating of the carbon nanotube pellicle membrane and the pellicle support surface by pressing the carbon nanotube pellicle membrane and the pellicle support surface against each other. The present disclosure relates also relates to a method for forming a reticle system for extreme ultraviolet lithography.Type: GrantFiled: May 15, 2018Date of Patent: August 17, 2021Assignees: IMEC VZW, Imec USA Nanoelectronics Design CenterInventors: Marina Timmermans, Emily Gallagher, Ivan Pollentier, Hanns Christoph Adelmann, Cedric Huyghebaert, Jae Uk Lee
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Patent number: 11075127Abstract: Disclosed are methods of and apparatuses and systems for depositing a film in a multi-station deposition apparatus. The methods may include: (a) providing a substrate to a first station of the apparatus, (b) adjusting the temperature of the substrate to a first temperature, (c) depositing a first portion of the material on the substrate while the substrate is at the first temperature in the first station, (d) transferring the substrate to the second station, (e) adjusting the temperature of the substrate to a second temperature, and (f) depositing a second portion of the material on the substrate while the substrate is at the second temperature, such that the first portion and the second portion exhibit different values of a property of the material. The apparatuses and systems may include a multi-station deposition apparatus and a controller having control logic for performing one or more of (a)-(f).Type: GrantFiled: July 3, 2019Date of Patent: July 27, 2021Assignee: Lam Research CorporationInventors: Seshasayee Varadarajan, Aaron R. Fellis, Andrew John McKerrow, James Samuel Sims, Ramesh Chandrasekharan, Jon Henri
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Patent number: 11041239Abstract: A method for forming a SiC film on a target substrate by ALD, comprises: activating a surface of the target substrate by activation gas plasma which is plasmatized an activation gas; and forming a SiC film by supplying a source gas containing a precursor represented by a chemical formula RSiX13 or RSiHClX2 onto the target substrate whose the surface is activated by activating the surface of the target substrate, where, R is an organic group having an unsaturated bond, X1 is selected from a group consisting of H, F, Cl, Br and I, and X2 is one selected from a group consisting of Cl, Br and I.Type: GrantFiled: November 16, 2017Date of Patent: June 22, 2021Assignee: TOKYO ELECTRON LIMITEDInventors: Taiki Katou, Shuji Azumo, Yusaku Kashiwagi