Insulative Material Deposited Upon Semiconductive Substrate Patents (Class 438/778)
  • Patent number: 10847365
    Abstract: A method of forming, on a substrate having a recess pattern, a silicon carbide film having a reflective index of 2.3 or higher as measured at 633 nm, includes (i) supplying an organosilane precursor in a pulse to a reaction space where the substrate is placed, which precursor has a formula of RSiH3 wherein R is a hydrocarbon-containing moiety including at least one unsaturated bond; (ii) continuously supplying a plasma-generating gas to the reaction space, which plasma-generating gas is selected from the group consisting of inert gases and hydride gases; (iii) continuously applying RF power to the reaction space to generate a plasma which excites the precursor; and (iv) repeating steps (i) through (iii), thereby forming a silicon carbide film on the substrate, which silicon carbide film has a reflective index of 2.3 or higher as measured at 633 nm.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: November 24, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Atsuki Fukazawa, Masaru Zaitsu
  • Patent number: 10825766
    Abstract: A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Young Kim, Kyu Hee Han, Sung Bin Park, Yeong Gil Kim, Jong Min Baek, Kyoung Woo Lee, Deok Young Jung
  • Patent number: 10811477
    Abstract: A flexible organic light emitting display device includes a flexible substrate, an insulating layer, a polymer flat layer, an anode, and a pixel isolation layer. The pixel isolation layer and the anode are alternately disposed on the polymer flat layer, and the pixel isolation layer includes a first pixel isolation layer disposed on a bent area and a second pixel isolation layer disposed on a flat area. A thickness of the first pixel isolation layer is greater than a thickness of the second pixel isolation layer. A method of manufacturing an organic light emitting display device is further provided by increasing the thickness of the pixel isolation layer of the bent area, mechanical stress generated by a flexible organic light emitting diode (OLED) display device during bending can be reduced, thereby improving the bending performance of the flexible OLED display device.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: October 20, 2020
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Bo Wang
  • Patent number: 10811516
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Che-Cheng Chang, Mu-Tsang Lin, Tung-Wen Cheng, Zhe-Hao Zhang
  • Patent number: 10793947
    Abstract: A deposited cobalt composition is described, including cobalt and one or more alloy component that is effective in combination with cobalt to enhance adhesion to a substrate when exposed on the substrate to variable temperature and/or delaminative force conditions, as compared to corresponding elemental cobalt, wherein the one or more alloy component is selected from the group consisting of boron, phosphorous, tin, antimony, indium, and gold. Such deposited cobalt composition may be employed for metallization in semiconductor devices and device precursor structures, flat-panel displays, and solar panels, and provides highly adherent metallization when the metallized substrate is subjected to thermal cycling and/or chemical mechanical planarization operations in the manufacturing of the semiconductor, flat-panel display, or solar panel product.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: October 6, 2020
    Assignee: ENTEGRIS, INC.
    Inventors: Philip S. H. Chen, Bryan C. Hendrix, Thomas H. Baum
  • Patent number: 10777415
    Abstract: Hydrogen annealing for heating a semiconductor wafer on which a thin film containing a dopant is deposited to an annealing temperature under an atmosphere containing hydrogen is performed. A native oxide film is inevitably formed between the thin film containing the dopant and the semiconductor wafer, however, by performing hydrogen annealing, the dopant atoms diffuse relatively easily in the native oxide film and accumulate at the interface between the front surface of the semiconductor wafer and the native oxide film. Subsequently, the semiconductor wafer is preheated to a preheating temperature under a nitrogen atmosphere, and then, flash heating treatment in which the front surface of the semiconductor wafer is heated to a peak temperature for less than one second is performed. The dopant atoms are diffused and activated in a shallow manner from the front surface of the semiconductor wafer, thus, the low-resistance and extremely shallow junction is obtained.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: September 15, 2020
    Assignee: SCREEN HOLDINGS CO., LTD.
    Inventors: Kazuhiko Fuse, Hikaru Kawarazaki, Hideaki Tanimura, Shinichi Kato
  • Patent number: 10712659
    Abstract: The present disclosure relates to a method for forming a carbon nanotube pellicle membrane for an extreme ultraviolet lithography reticle, the method comprising: bonding together overlapping carbon nanotubes of at least one carbon nanotube film by pressing the at least one carbon nanotube film between a first pressing surface and a second pressing surface, thereby forming a free-standing carbon nanotube pellicle membrane. The present disclosure also relates to a method for forming a pellicle for extreme ultraviolet lithography and for forming a reticle system for extreme ultraviolet lithography respectively.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 14, 2020
    Assignees: IMEC VZW, Imec USA Nanoelectronics Design Center
    Inventors: Emily Gallagher, Cedric Huyghebaert, Ivan Pollentier, Hanns Christoph Adelmann, Marina Timmermans, Jae Uk Lee
  • Patent number: 10707073
    Abstract: Examples of a film forming method includes repeating first processing and second processing in this order a plurality of times, wherein the first processing supplies material-1 having one silicon atom per molecule onto a substrate, and then generates plasma while reactant gas is introduced, thereby forming a silicon oxide film on the substrate, and the second processing provides material-2 having two or more silicon atoms per molecule onto the substrate, and then generates plasma while no reactant gas is introduced, thereby forming a double silicon compound on the substrate.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: July 7, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Yoshio Susa, Yuko Kengoyama, Taishi Ebisudani
  • Patent number: 10707116
    Abstract: Implementations disclosed herein relate to methods for forming and filling trenches in a substrate with a flowable dielectric material. In one implementation, the method includes subjecting a substrate having at least one trench to a deposition process to form a flowable layer over a bottom surface and sidewall surfaces of the trench in a bottom-up fashion until the flowable layer reaches a predetermined deposition thickness, subjecting the flowable layer to a first curing process, the first curing process being a UV curing process, subjecting the UV cured flowable layer to a second curing process, the second curing process being a plasma or plasma-assisted process, and performing sequentially and repeatedly the deposition process, the first curing process, and the second curing process until the plasma cured flowable layer fills the trench and reaches a predetermined height over a top surface of the trench.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: July 7, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jingmei Liang, Yong Sun, Jinrui Guo, Praket P. Jha, Jung Chan Lee, Tza-Jing Gung, Mukund Srinivasan
  • Patent number: 10707074
    Abstract: By sequentially performing, a plurality of times, a step of supplying a mixed gas of an organic metal-containing source gas and an inert gas to a process chamber housing a substrate by adjusting a flow velocity of the mixed gas on the substrate to 7.8 m/s to 15.6 m/s and adjusting a partial pressure of the organic metal-containing source gas in the mixed gas to 0.167 to 0.3, a step of exhausting the process chamber, a step of supplying an oxygen-containing gas to the process chamber, and a step of exhausting the process chamber, a metal oxide film is formed on the substrate.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 7, 2020
    Assignee: Kokusai Electric Corporation
    Inventors: Yoshimasa Nagatomi, Hirohisa Yamazaki
  • Patent number: 10651045
    Abstract: Described are compositions and methods useful for wet-etching a microelectronic device substrate that includes silicon nitride; the compositions including phosphoric acid, hexafluorosilicic acid, and an amino alkoxy silane, and optionally one or more additional optional ingredients; a wet etching method of a substrate that includes silicon nitride and silicon oxide, that uses a composition as described, can achieve useful or improved silicon nitride etch rate, useful or improved silicon nitride selectivity, a combination of these, and optionally a reduction in particles present at a substrate surface after etching.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: May 12, 2020
    Assignee: ENTEGRIS, INC.
    Inventors: Emanuel Cooper, Steven Bilodeau, Wen-Haw Dai, Min-Chieh Yang, Sheng-Hung Tu, Hsing-Chen Wu, Sean Kim, SeongJin Hong
  • Patent number: 10643925
    Abstract: An atomic layer deposition (ALD) process for depositing a fluorine-containing thin film on a substrate can include a plurality of super-cycles. Each super-cycle may include a metal fluoride sub-cycle and a reducing sub-cycle. The metal fluoride sub-cycle may include contacting the substrate with a metal fluoride. The reducing sub-cycle may include alternately and sequentially contacting the substrate with a reducing agent and a nitrogen reactant.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: May 5, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Tom E. Blomberg, Linda Lindroos, Hannu Huotari
  • Patent number: 10643888
    Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham
  • Patent number: 10636681
    Abstract: A substrate processing apparatus includes a first processing module including a first processing module, a second processing module, a first utility system adjacent to a back surface of the first processing module, and a second utility system adjacent to a back surface of the second processing module, a first exhaust box of the first utility system and a second exhaust box of the second utility system being disposed to face each other across a maintenance area located behind a part of the back surface of the first processing module that is close to the second processing module and behind a part of the back surface of the second processing module that is close to the first processing module, and a first supply box of the first utility system and a second supply box of the second utility system being disposed to face each other across the maintenance area.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: April 28, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Daigi Kamimura, Tomoshi Taniyama, Takashi Nogami
  • Patent number: 10629428
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to metal insulator metal capacitor devices and methods of manufacture. The method includes: depositing a bottom plate; depositing a dielectric film over the bottom plate; exposing the dielectric film to a gas; curing the dielectric film; and depositing a top plate over the dielectric film.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 21, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shariq Siddiqui, Han You, Xunyuan Zhang, Rohit Galatage, Roger A. Quon, Christopher J. Penny
  • Patent number: 10586699
    Abstract: A method of assessing a semiconductor substrate includes a sticking step of sticking a device layer of the semiconductor substrate to a support substrate, a thinning step of thinning the semiconductor substrate from a reverse side thereof to a thickness smaller than a finished thickness after the sticking step is carried out, and an assessing step of applying light to the semiconductor substrate from the reverse side thereof and measuring scattered light from the semiconductor substrate thereby to assess a property of the semiconductor substrate.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: March 10, 2020
    Assignee: DISCO CORPORATION
    Inventors: Youngsuk Kim, Shoichi Kodama
  • Patent number: 10580642
    Abstract: Methods for seam-less gap fill comprising forming a flowable film by PECVD, treating the flowable film to form an Si—X film where X=C, O or N and curing the flowable film or Si—X film to solidify the film. The flowable film can be formed using a higher order silane and plasma. A UV cure, or other cure, can be used to solidify the flowable film or the Si—X film.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: March 3, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Pramit Manna, Shishi Jiang
  • Patent number: 10573514
    Abstract: A method of forming a silicon-containing film includes: an adsorption step of supplying a silicon-containing gas represented by a general formula XSiCl3 (wherein X is an element whose bonding energy with Si is smaller than bonding energy of a Si—Cl bond) into a processing chamber accommodating substrates to cause the silicon-containing gas to be adsorbed to a surface of each of the substrates; and a reaction step of supplying a reaction gas reacting with the silicon-containing gas into the processing chamber to cause the silicon-containing gas adsorbed to the surface of each of the substrates to react with the reaction gas.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: February 25, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tsubasa Watanabe, Yamato Tonegawa
  • Patent number: 10515855
    Abstract: At least one embodiment relates to a method for integrating Si1-xGex structures with Si1-x?Gex? structures in a semiconductor device. The method includes providing a device that includes a plurality of Si1-xGex structures, where 0?x<1. The method also includes depositing a layer of GeO2 on a subset of the Si1-xGex structures. Further, the method includes heating at least the subset of Si1-xGex structures at a temperature high enough and for a time long enough to transform the subset of Si1-xGex structures into a subset of Si1-x?Gex? structures with x?>x.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: December 24, 2019
    Assignee: IMEC VZW
    Inventor: Kurt Wostyn
  • Patent number: 10504990
    Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Wu, Fu-Kai Yang, Chen-Ming Lee, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
  • Patent number: 10483212
    Abstract: A substrate stacking apparatus that stacks first and second substrates on each other, by forming a contact region where the first substrate held by a first holding section and the second substrate held by a second holding section contact each other, at one portion of the first and second substrates, and expanding the contact region from the one portion by releasing holding of the first substrate by the first holding section, wherein an amount of deformation occurring in a plurality of directions at least in the first substrate differs when the contact region expands, and the substrate stacking apparatus includes a restricting section that restricts misalignment between the first and second substrates caused by a difference in the amount of deformation. In the substrate stacking apparatus above, the restricting section may restrict the misalignment such that an amount of the misalignment is less than or equal to a prescribed value.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: November 19, 2019
    Assignee: Nikon Corporation
    Inventors: Isao Sugaya, Kazuya Okamoto, Hajime Mitsuishi, Minoru Fukuda
  • Patent number: 10480067
    Abstract: A film deposition method for filling a recessed pattern with a SiN film is provided. NH2 groups are caused to adsorb on a surface of a substrate containing a recessed pattern formed in a top surface of the substrate by supplying a first process gas containing NH3 converted to first plasma to the surface of the substrate containing the recessed pattern. The NH2 groups is partially converted to N groups by supplying a second process gas containing N2 converted to second plasma to the surface of the substrate containing the recessed pattern on which the NH2 groups is adsorbed. A silicon-containing gas is caused to adsorb on the NH2 groups by supplying the silicon-containing gas to the surface of the substrate containing the recessed pattern on which the NH2 groups and the N groups are adsorbed. The above steps are cyclically repeated.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: November 19, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Hitoshi Kato, Masahiro Murata, Jun Sato, Shigehiro Miura
  • Patent number: 10468620
    Abstract: A plurality of lighting apparatuses according to the present disclosure may be formed on a film having flexibility, and then cut to complete each unit lighting apparatus, and an lighting apparatus formed on the film may be provided with an aging pad to apply an aging voltage to the organic light emitting layer through the aging pad so as to age the lighting apparatus during the process of forming the lighting apparatus, and when the film formed with the lighting apparatus is cut and divided into individual lighting apparatuses, the aging pad may be removed and cut, and only a pad line for electrically connecting the aging pad to the first electrode and the second electrode may remain in the lighting apparatus.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: November 5, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Namkook Kim, Taejoon Song, Shinbok Lee, Soonsung Yoo, Hwankeon Lee
  • Patent number: 10388512
    Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing (a) forming a first layer by supplying a precursor to the substrate from a first nozzle and (b) forming a second layer by supplying a reactant to the substrate from a second nozzle different from the first nozzle to thereby modify the first layer. The act (a) includes sequentially performing (a-1) supplying an inert gas from the second nozzle at a first flow rate smaller than a flow rate of the precursor in a state in which the precursor is supplied from the first nozzle and (a-2) supplying an inert gas from the second nozzle at a second flow rate larger than the flow rate of the precursor in a state in which the precursor is supplied from the first nozzle.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 20, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Takeo Hanashima, Takafumi Sasaki, Hiroaki Hiramatsu, Tsukasa Kamakura
  • Patent number: 10379094
    Abstract: A contamination control method includes: a wafer loading step for loading a monitor wafer in a chamber of a vapor deposition apparatus; a heat-treatment repetition step for consecutively repeating a heat-treatment step for thermally treating the monitor wafer for predetermined times; a wafer unloading step for unloading the monitor wafer from the chamber; and a wafer-contamination-evaluation step for evaluating a metal-contamination degree of the monitor wafer unloaded out of the chamber. The heat-treatment step includes a first heat-treatment step for thermally treating the monitor wafer in an atmosphere of a hydrogen-containing gas and a second heat-treatment step for thermally treating the monitor wafer in an atmosphere of a hydrogen-chloride-containing gas and the hydrogen-containing gas.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: August 13, 2019
    Assignee: SUMCO CORPORATION
    Inventor: Syouji Nogami
  • Patent number: 10364495
    Abstract: The present invention relates to an aluminum compound represented by general formula (I). The present invention also relates to a thin film-forming raw material that contains this aluminum compound. In general formula (I), R1 and R2 each independently denote a straight chain or branched alkyl group having 2-5 carbon atoms, and R3 denotes a methyl group or ethyl group. It is preferable for R1 and R2 to be ethyl groups. This compound has a low melting point, exhibits satisfactory volatility, has high thermal stability, and is suitable for use as a raw material used to form a thin film by a CVD method.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 30, 2019
    Assignee: ADEKA CORPORATION
    Inventors: Tomoharu Yoshino, Atsushi Sakurai, Tsubasa Shiratori, Masako Hatase, Hiroyuki Uchiuzou, Akihiro Nishida
  • Patent number: 10340298
    Abstract: The present disclosure relates to a semiconductor device and an electronic apparatus capable of reducing a leak current of a PN junction region. In a Si substrate, an N+ region is formed in a P-type Well (P_Well region). A depletion layer is formed in the circumference of a boundary (metallurgic boundary of a PN junction) between the P_Well region and the N+ region. On the surface of the Si substrate, a fixed charge layer having positive fixed charge is formed on the N+ region to be spanned to the depletion layer. The present disclosure is applicable to a CMOS solid-state imaging device used in an imaging apparatus such as a camera.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: July 2, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shinya Yamakawa, Satoe Miyata
  • Patent number: 10340134
    Abstract: A method includes forming a film on a substrate by performing a cycle n times (where n is an integer equal to or greater than 1), the cycle including alternately performing: performing a set m times (where m is an integer equal to or greater than 1), the set including supplying a precursor to the substrate and supplying a borazine compound to the substrate; and supplying an oxidizing agent to the substrate.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 2, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yoshiro Hirose, Atsushi Sano, Katsuyoshi Harada
  • Patent number: 10329667
    Abstract: A deposition method relating to semiconductor technology is presented. The deposition method includes: conducting a first deposition in a reaction chamber at a first deposition temperature; conducting a cool-down process on the reaction chamber, and conducting a second deposition during the cool-down process. In the first deposition, the thin-films deposited on the periphery of a wafer are thicker than those deposited on the center of a wafer, while in the second deposition, the thin-films deposited on the periphery of a wafer are thinner that those deposited on the center of a wafer. Therefore the thin-films deposited by this deposition method are more homogeneous in thickness that those deposited with conventional methods.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: June 25, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERATIONAL (BEIJING) CORPORATION
    Inventors: Jian Fei Shen, Yang Wang
  • Patent number: 10328532
    Abstract: In one aspect, a method includes conducting a plurality of tests on process variables of a thermal process, with a test of the plurality of tests being conducted on two or more process variables, the test comprising: locally heating a region of a structure, wherein the local heating results in formation of a thermal field in the structure; assessing one or more temperature integrals of the thermal field; and based on results of the plurality of tests, generating a process map of the one or more temperature integrals of the thermal field, with the one or more temperature integrals based on a function of the two or more process variables.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: June 25, 2019
    Assignee: Carnegie Mellon University
    Inventor: Jack Lee Beuth, Jr.
  • Patent number: 10325979
    Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a substrate, a first group of metal layers including a plurality of first fingers over the substrate, wherein the first fingers are formed without a via. The integrated circuit may further include a second group of metal layers including a plurality of second fingers over the first group of metal layers, wherein the second fingers are formed with vias, and wherein the first and the second group of metal layers are formed by a processing technology node of 7 nm or below.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Junjing Bao, Jun Chen, Yangyang Sun, Stanley Seungchul Song, Giridhar Nallapati
  • Patent number: 10276797
    Abstract: The present invention provides a vapor deposition device including a novel alignment mechanism applicable to a large substrate, a vapor deposition method, and a method for manufacturing an organic electroluminescence element. The vapor deposition device of the present invention is a vapor deposition device for performing vapor deposition while transporting a substrate in a first direction, and includes: a mask; a substrate tray including a substrate-holding portion and a guide portion protruding from the substrate-holding portion to the mask side and disposed along the first direction; at least one distance meter disposed on a first end which is one end of the mask or the guide portion; and at least one driver coupled with a second end which is the other end of the mask. The at least one distance meter is configured to measure a distance between the at least one distance meter and the guide portion or the first end when the guide portion faces the first end.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: April 30, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Ichihara, Eiichi Matsumoto, Yuhki Kobayashi, Katsuhiro Kikuchi, Shinichi Kawato, Takashi Ochi, Kazuki Matsunaga, Satoshi Inoue
  • Patent number: 10269560
    Abstract: A method for manufacturing semiconductor structure is disclosed. The method includes: providing a semiconductor substrate; hydrogenizing a surface of the semiconductor substrate; supplying a precursor to the surface of the semiconductor substrate; and supplying a reactant to the surface of the semiconductor substrate. An associated method for performing an atomic layer deposition (ALD) upon a semiconductor substrate and an associated atomic layer deposition (ALD) method are also disclosed.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yun-Tzu Chiu, Hsueh-Hui Kuo, Lin-Jung Wu, Chih-Tsung Lee
  • Patent number: 10249709
    Abstract: Nanosheet FET devices having substrate isolation layers are provided, as well as methods for fabricating nanosheet FET devices with substrate isolation layers. For example, a semiconductor device includes a nanosheet stack structure formed on a substrate, which includes a rare earth oxide (REO) layer formed on the substrate, and a semiconductor channel layer disposed adjacent to the REO layer. A metal gate structure is formed over the nanosheet stack structure, and a gate insulating spacer is disposed on sidewalls of the metal gate structure, wherein end portions of the semiconductor channel layer are exposed through the gate insulating spacer. Source/drain regions are formed in contact with the exposed end portions of the semiconductor channel layer. A portion of the metal gate structure is disposed between the semiconductor channel layer and the REO layer, wherein the REO layer isolates the metal gate structure from the substrate.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10176988
    Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes: supplying a precursor to the substrate in a process chamber and exhausting the precursor from a first exhaust system; and supplying a reactant to the substrate in the process chamber and exhausting the reactant from a second exhaust system. In the forming of the film, when the precursor does not flow through the first exhaust system, a deactivator that is a material different from the reactant is directly supplied from a supply port provided in the first exhaust system into the first exhaust system.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: January 8, 2019
    Assignee: Kokusai Electric Corporation
    Inventors: Ryota Horiike, Kenji Kameda
  • Patent number: 10153135
    Abstract: An ICP plasma etching apparatus for etching a substrate includes at least one chamber, a substrate support positioned within the chamber, a plasma production device for producing a plasma for use in etching the substrate, and a protective structure which surrounds the substrate support so that, in use, a peripheral portion of the substrate is protected from unwanted deposition of material. The protective structure is arranged to be electrically biased and is formed from a metallic material so that metallic material can be sputtered from the protective structure onto an interior surface of the chamber to adhere particulate material to the interior surface.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: December 11, 2018
    Assignee: SPTS TECHNOLOGIES LIMITED
    Inventors: Anthony Paul Wilby, Stephen R Burgess, Ian Moncrieff, Paul Densley, Clive L Widdicks, Paul Rich, Adrian Thomas
  • Patent number: 10147629
    Abstract: Provided is an electrostatic chuck device in which breakdown between an electrostatic chuck portion and a cooling base portion can be prevented, voltage endurance can be improved, uniformity in the in-plane temperature of a mounting surface of the electrostatic chuck portion where a plate-shaped sample is mounted can be improved, and voltage endurance of a heating member can be improved by applying a uniform voltage between the electrostatic chuck portion and the cooling base portion.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: December 4, 2018
    Assignee: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: Kentaro Takahashi, Megumi Ootomo
  • Patent number: 10126239
    Abstract: The present invention provides a sensor cell that has excellent measurement accuracy in repetitive measurement. An optical waveguide of the present invention includes a cladding layer and a core layer buried in the cladding layer so that at least one surface of the core layer is exposed. A water contact angle of a surface of the cladding layer on which the core layer is exposed is 80° or more. An SPR sensor cell and a colorimetric sensor cell of the present invention each include the optical waveguide of the present invention.
    Type: Grant
    Filed: September 1, 2014
    Date of Patent: November 13, 2018
    Assignee: NITTO DENKO CORPORATION
    Inventors: Shigenori Morita, Tomohiro Kontani, Mayu Ozaki, Chiharu Odane, Kazutaka Hara, Manabu Miyazaki
  • Patent number: 10128128
    Abstract: A method of manufacturing a semiconductor device includes: (a) loading into a process chamber a substrate including: a wiring layer including a first interlayer insulating film, a plurality of copper-containing films formed on the first interlayer insulating film and used as a wiring, an inter-wire insulating film electrically insulating the plurality of copper containing film and a recess formed between the plurality of copper-containing film; and a first diffusion barrier film formed on a first portion of a surface of the plurality of copper-containing films to suppress a diffusion of a component of the plurality of copper-containing film; and (b) supplying a silicon-containing gas into the process chamber to form a silicon-containing film on: a surface of the recess; and a second portion of the surface of the plurality of copper-containing films other than the first portion where the first diffusion barrier film is formed.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: November 13, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tsuyoshi Takeda, Hiroshi Ashihara, Naofumi Ohashi, Toshiyuki Kikuchi
  • Patent number: 10096485
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a plug in a first insulator, forming a first film on the first insulator and the plug, and forming an opening in the first film. The method further includes forming a second insulator in the opening to form an air gap in the opening, removing the first film after forming the second insulator, to expose the plug, and forming an interconnect on the exposed plug.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: October 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naomi Fukumaki
  • Patent number: 10086474
    Abstract: A protective film applying apparatus includes a protective film forming and cleaning unit for forming a protective film on a surface of a wafer and cleaning the protective film away. A coverage state detector detects a coverage state of the protective film, and a controller determines whether or not the protective film has a film thickness falling within a predetermined range. If the controller decides that the thickness of the protective film does not fall in the predetermined range, the controller operates the protective film forming and cleaning unit to clean away the protective film, performs a pretreating process selected depending on the film thickness on the surface, and operates the protective film forming and cleaning unit to form a protective film again on the surface of the wafer.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: October 2, 2018
    Assignee: Disco Corporation
    Inventors: Senichi Ryo, Kenta Nakano, Yukinobu Ohura, Toshiyuki Yoshikawa
  • Patent number: 10066294
    Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing: supplying a precursor gas to the substrate in a process chamber through a first nozzle; supplying an oxygen-containing gas to the substrate in the process chamber through a second nozzle made of quartz and differing from the first nozzle; and supplying a hydrogen-containing gas to the substrate in the process chamber through the second nozzle. The method further includes, prior to performing the act of forming the film, etching a surface of the second nozzle to a depth which falls within a range of 15 ?m or more and 30 ?m or less from the surface of the second nozzle.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: September 4, 2018
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Ryota Sasajima, Shintaro Kogura, Masayoshi Minami
  • Patent number: 10050133
    Abstract: In a pin diode, a new means for a soft recovery other than the means for the soft recovery using an anode layer with a low concentration and a local lifetime control is provided. A semiconductor device comprising a drift layer of a first conductivity type provided on a semiconductor substrate of a first conductivity type, a front-surface-side region of a second conductivity type provided on a front surface side of the drift layer, an insulating-film layer provided on a front surface side of the front-surface-side region with a thickness thinner than a natural oxide film, and a metal layer provided on a front surface side of the insulating-film layer is provided.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: August 14, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Eri Ogawa, Takashi Yoshimura
  • Patent number: 10041167
    Abstract: Methods are described for a cyclical deposition and curing process. More particularly, the implementations described herein provide a cyclic sequential deposition and curing process for filling features formed on a substrate. Features are filled to ensure electrical isolation of features in integrated circuits formed on a substrate. The processes described herein use flowable film deposition processes that have been effective in reducing voids or seams produced in features formed on a substrate. However, conventional gap-filling methods using flowable films typically contain dielectric materials that have undesirable physical and electrical properties. In particular, film density is not uniform, film dielectric constant varies across the film thickness, film stability is not ideal, film refractive index is inconsistent, and resistance to dilute hydrofluoric acid (DHF) is not ideal in conventional flowable films.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: August 7, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jingmei Liang, Jung Chan Lee, Jinrui Guo, Mukund Srinivasan
  • Patent number: 10043666
    Abstract: Embodiments described herein generally relate to a substrate processing system, such as an etch processing system. In one embodiment, a method of processing a substrate is disclosed herein. The method includes removing a native oxide from a surface of the substrate, baking the substrate in a pre-treatment thermal chamber such that double atomic steps are formed on the surface of the substrate, and forming an epitaxial layer on the substrate after the substrate is baked.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: August 7, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Errol Antonio C. Sanchez, Zhiyuan Ye, Keun-Yong Ban
  • Patent number: 10037905
    Abstract: Treatment of carbon-containing low-k dielectric with UV radiation and a reducing agent enables process-induced damage repair. Also, treatment with a reducing agent and UV radiation is effective to clean a processed wafer surface by removal of metal oxide (e.g., copper oxide) and/or organic residue of CMP slurry from the planarized surface of a processed wafer with or without low-k dielectric. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metalization, post-planarization, or both, and/or provide effective post-planarization surface cleaning to improve adhesion of subsequently applied dielectric barrier and/or other layers.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: July 31, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Bhadri Varadarajan, George A. Antonelli, Bart van Schravendijk
  • Patent number: 10008588
    Abstract: The amount of water and hydrogen contained in an oxide semiconductor film is reduced, and oxygen is supplied sufficiently from a base film to the oxide semiconductor film in order to reduce oxygen deficiencies. A stacked base film is formed, a first heat treatment is performed, an oxide semiconductor film is formed over and in contact with the stacked base film, and a second heat treatment is performed. In the stacked base film, a first base film and a second base film are stacked in this order. The first base film is an insulating oxide film from which oxygen is released by heating. The second base film is an insulating metal oxide film. An oxygen diffusion coefficient of the second base film is smaller than that of the first base film.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: June 26, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Imoto, Yuhei Sato
  • Patent number: 9985245
    Abstract: The present invention provides an organic light emitting device, a manufacturing method thereof and a display device. In the organic light emitting device provided by the present invention, a first inorganic thin film entirely covers a pre-encapsulation layer and an organic light emitting unit, and the first inorganic thin film has a denser molecular structure compared with the pre-encapsulation layer, thereby more effectively preventing water and oxygen from invading the organic light emitting unit via the pre-encapsulation layer to influence the service life of the organic light emitting unit.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: May 29, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Yulin Wang
  • Patent number: 9984869
    Abstract: A method is for forming a nitride or oxide film by plasma-assisted cyclic deposition, one cycle of which includes: feeding a first reactant, a second reactant, and a precursor to a reaction space where a substrate is placed, wherein the second reactant flows at a first flow ratio wherein a flow ratio is defined as a ratio of a flow rate of the second reactant to a total flow rate of gases flowing in the reaction space; and stopping feeding the precursor while continuously feeding the first and second reactants at a flow ratio which is gradually reduced from the first flow ratio to a second flow ratio while applying RF power to the reaction space to expose the substrate to a plasma. The second reactant is constituted by a hydrogen-containing compound or oxygen-containing compound.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: May 29, 2018
    Assignee: ASM IP Holding B.V.
    Inventor: Timothee Julien Vincent Blanquart
  • Patent number: 9966251
    Abstract: Provided is a method of manufacturing a semiconductor device.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: May 8, 2018
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Ryota Sasajima, Yoshiro Hirose, Yosuke Ota, Naonori Akae, Kojiro Yokozawa