Insulative Material Deposited Upon Semiconductive Substrate Patents (Class 438/778)
  • Patent number: 10468620
    Abstract: A plurality of lighting apparatuses according to the present disclosure may be formed on a film having flexibility, and then cut to complete each unit lighting apparatus, and an lighting apparatus formed on the film may be provided with an aging pad to apply an aging voltage to the organic light emitting layer through the aging pad so as to age the lighting apparatus during the process of forming the lighting apparatus, and when the film formed with the lighting apparatus is cut and divided into individual lighting apparatuses, the aging pad may be removed and cut, and only a pad line for electrically connecting the aging pad to the first electrode and the second electrode may remain in the lighting apparatus.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: November 5, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Namkook Kim, Taejoon Song, Shinbok Lee, Soonsung Yoo, Hwankeon Lee
  • Patent number: 10388512
    Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing (a) forming a first layer by supplying a precursor to the substrate from a first nozzle and (b) forming a second layer by supplying a reactant to the substrate from a second nozzle different from the first nozzle to thereby modify the first layer. The act (a) includes sequentially performing (a-1) supplying an inert gas from the second nozzle at a first flow rate smaller than a flow rate of the precursor in a state in which the precursor is supplied from the first nozzle and (a-2) supplying an inert gas from the second nozzle at a second flow rate larger than the flow rate of the precursor in a state in which the precursor is supplied from the first nozzle.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 20, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Takeo Hanashima, Takafumi Sasaki, Hiroaki Hiramatsu, Tsukasa Kamakura
  • Patent number: 10379094
    Abstract: A contamination control method includes: a wafer loading step for loading a monitor wafer in a chamber of a vapor deposition apparatus; a heat-treatment repetition step for consecutively repeating a heat-treatment step for thermally treating the monitor wafer for predetermined times; a wafer unloading step for unloading the monitor wafer from the chamber; and a wafer-contamination-evaluation step for evaluating a metal-contamination degree of the monitor wafer unloaded out of the chamber. The heat-treatment step includes a first heat-treatment step for thermally treating the monitor wafer in an atmosphere of a hydrogen-containing gas and a second heat-treatment step for thermally treating the monitor wafer in an atmosphere of a hydrogen-chloride-containing gas and the hydrogen-containing gas.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: August 13, 2019
    Assignee: SUMCO CORPORATION
    Inventor: Syouji Nogami
  • Patent number: 10364495
    Abstract: The present invention relates to an aluminum compound represented by general formula (I). The present invention also relates to a thin film-forming raw material that contains this aluminum compound. In general formula (I), R1 and R2 each independently denote a straight chain or branched alkyl group having 2-5 carbon atoms, and R3 denotes a methyl group or ethyl group. It is preferable for R1 and R2 to be ethyl groups. This compound has a low melting point, exhibits satisfactory volatility, has high thermal stability, and is suitable for use as a raw material used to form a thin film by a CVD method.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 30, 2019
    Assignee: ADEKA CORPORATION
    Inventors: Tomoharu Yoshino, Atsushi Sakurai, Tsubasa Shiratori, Masako Hatase, Hiroyuki Uchiuzou, Akihiro Nishida
  • Patent number: 10340298
    Abstract: The present disclosure relates to a semiconductor device and an electronic apparatus capable of reducing a leak current of a PN junction region. In a Si substrate, an N+ region is formed in a P-type Well (P_Well region). A depletion layer is formed in the circumference of a boundary (metallurgic boundary of a PN junction) between the P_Well region and the N+ region. On the surface of the Si substrate, a fixed charge layer having positive fixed charge is formed on the N+ region to be spanned to the depletion layer. The present disclosure is applicable to a CMOS solid-state imaging device used in an imaging apparatus such as a camera.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: July 2, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shinya Yamakawa, Satoe Miyata
  • Patent number: 10340134
    Abstract: A method includes forming a film on a substrate by performing a cycle n times (where n is an integer equal to or greater than 1), the cycle including alternately performing: performing a set m times (where m is an integer equal to or greater than 1), the set including supplying a precursor to the substrate and supplying a borazine compound to the substrate; and supplying an oxidizing agent to the substrate.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 2, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yoshiro Hirose, Atsushi Sano, Katsuyoshi Harada
  • Patent number: 10329667
    Abstract: A deposition method relating to semiconductor technology is presented. The deposition method includes: conducting a first deposition in a reaction chamber at a first deposition temperature; conducting a cool-down process on the reaction chamber, and conducting a second deposition during the cool-down process. In the first deposition, the thin-films deposited on the periphery of a wafer are thicker than those deposited on the center of a wafer, while in the second deposition, the thin-films deposited on the periphery of a wafer are thinner that those deposited on the center of a wafer. Therefore the thin-films deposited by this deposition method are more homogeneous in thickness that those deposited with conventional methods.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: June 25, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERATIONAL (BEIJING) CORPORATION
    Inventors: Jian Fei Shen, Yang Wang
  • Patent number: 10328532
    Abstract: In one aspect, a method includes conducting a plurality of tests on process variables of a thermal process, with a test of the plurality of tests being conducted on two or more process variables, the test comprising: locally heating a region of a structure, wherein the local heating results in formation of a thermal field in the structure; assessing one or more temperature integrals of the thermal field; and based on results of the plurality of tests, generating a process map of the one or more temperature integrals of the thermal field, with the one or more temperature integrals based on a function of the two or more process variables.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: June 25, 2019
    Assignee: Carnegie Mellon University
    Inventor: Jack Lee Beuth, Jr.
  • Patent number: 10325979
    Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a substrate, a first group of metal layers including a plurality of first fingers over the substrate, wherein the first fingers are formed without a via. The integrated circuit may further include a second group of metal layers including a plurality of second fingers over the first group of metal layers, wherein the second fingers are formed with vias, and wherein the first and the second group of metal layers are formed by a processing technology node of 7 nm or below.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Junjing Bao, Jun Chen, Yangyang Sun, Stanley Seungchul Song, Giridhar Nallapati
  • Patent number: 10276797
    Abstract: The present invention provides a vapor deposition device including a novel alignment mechanism applicable to a large substrate, a vapor deposition method, and a method for manufacturing an organic electroluminescence element. The vapor deposition device of the present invention is a vapor deposition device for performing vapor deposition while transporting a substrate in a first direction, and includes: a mask; a substrate tray including a substrate-holding portion and a guide portion protruding from the substrate-holding portion to the mask side and disposed along the first direction; at least one distance meter disposed on a first end which is one end of the mask or the guide portion; and at least one driver coupled with a second end which is the other end of the mask. The at least one distance meter is configured to measure a distance between the at least one distance meter and the guide portion or the first end when the guide portion faces the first end.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: April 30, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Ichihara, Eiichi Matsumoto, Yuhki Kobayashi, Katsuhiro Kikuchi, Shinichi Kawato, Takashi Ochi, Kazuki Matsunaga, Satoshi Inoue
  • Patent number: 10269560
    Abstract: A method for manufacturing semiconductor structure is disclosed. The method includes: providing a semiconductor substrate; hydrogenizing a surface of the semiconductor substrate; supplying a precursor to the surface of the semiconductor substrate; and supplying a reactant to the surface of the semiconductor substrate. An associated method for performing an atomic layer deposition (ALD) upon a semiconductor substrate and an associated atomic layer deposition (ALD) method are also disclosed.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yun-Tzu Chiu, Hsueh-Hui Kuo, Lin-Jung Wu, Chih-Tsung Lee
  • Patent number: 10249709
    Abstract: Nanosheet FET devices having substrate isolation layers are provided, as well as methods for fabricating nanosheet FET devices with substrate isolation layers. For example, a semiconductor device includes a nanosheet stack structure formed on a substrate, which includes a rare earth oxide (REO) layer formed on the substrate, and a semiconductor channel layer disposed adjacent to the REO layer. A metal gate structure is formed over the nanosheet stack structure, and a gate insulating spacer is disposed on sidewalls of the metal gate structure, wherein end portions of the semiconductor channel layer are exposed through the gate insulating spacer. Source/drain regions are formed in contact with the exposed end portions of the semiconductor channel layer. A portion of the metal gate structure is disposed between the semiconductor channel layer and the REO layer, wherein the REO layer isolates the metal gate structure from the substrate.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10176988
    Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes: supplying a precursor to the substrate in a process chamber and exhausting the precursor from a first exhaust system; and supplying a reactant to the substrate in the process chamber and exhausting the reactant from a second exhaust system. In the forming of the film, when the precursor does not flow through the first exhaust system, a deactivator that is a material different from the reactant is directly supplied from a supply port provided in the first exhaust system into the first exhaust system.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: January 8, 2019
    Assignee: Kokusai Electric Corporation
    Inventors: Ryota Horiike, Kenji Kameda
  • Patent number: 10153135
    Abstract: An ICP plasma etching apparatus for etching a substrate includes at least one chamber, a substrate support positioned within the chamber, a plasma production device for producing a plasma for use in etching the substrate, and a protective structure which surrounds the substrate support so that, in use, a peripheral portion of the substrate is protected from unwanted deposition of material. The protective structure is arranged to be electrically biased and is formed from a metallic material so that metallic material can be sputtered from the protective structure onto an interior surface of the chamber to adhere particulate material to the interior surface.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: December 11, 2018
    Assignee: SPTS TECHNOLOGIES LIMITED
    Inventors: Anthony Paul Wilby, Stephen R Burgess, Ian Moncrieff, Paul Densley, Clive L Widdicks, Paul Rich, Adrian Thomas
  • Patent number: 10147629
    Abstract: Provided is an electrostatic chuck device in which breakdown between an electrostatic chuck portion and a cooling base portion can be prevented, voltage endurance can be improved, uniformity in the in-plane temperature of a mounting surface of the electrostatic chuck portion where a plate-shaped sample is mounted can be improved, and voltage endurance of a heating member can be improved by applying a uniform voltage between the electrostatic chuck portion and the cooling base portion.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: December 4, 2018
    Assignee: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: Kentaro Takahashi, Megumi Ootomo
  • Patent number: 10126239
    Abstract: The present invention provides a sensor cell that has excellent measurement accuracy in repetitive measurement. An optical waveguide of the present invention includes a cladding layer and a core layer buried in the cladding layer so that at least one surface of the core layer is exposed. A water contact angle of a surface of the cladding layer on which the core layer is exposed is 80° or more. An SPR sensor cell and a colorimetric sensor cell of the present invention each include the optical waveguide of the present invention.
    Type: Grant
    Filed: September 1, 2014
    Date of Patent: November 13, 2018
    Assignee: NITTO DENKO CORPORATION
    Inventors: Shigenori Morita, Tomohiro Kontani, Mayu Ozaki, Chiharu Odane, Kazutaka Hara, Manabu Miyazaki
  • Patent number: 10128128
    Abstract: A method of manufacturing a semiconductor device includes: (a) loading into a process chamber a substrate including: a wiring layer including a first interlayer insulating film, a plurality of copper-containing films formed on the first interlayer insulating film and used as a wiring, an inter-wire insulating film electrically insulating the plurality of copper containing film and a recess formed between the plurality of copper-containing film; and a first diffusion barrier film formed on a first portion of a surface of the plurality of copper-containing films to suppress a diffusion of a component of the plurality of copper-containing film; and (b) supplying a silicon-containing gas into the process chamber to form a silicon-containing film on: a surface of the recess; and a second portion of the surface of the plurality of copper-containing films other than the first portion where the first diffusion barrier film is formed.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: November 13, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tsuyoshi Takeda, Hiroshi Ashihara, Naofumi Ohashi, Toshiyuki Kikuchi
  • Patent number: 10096485
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a plug in a first insulator, forming a first film on the first insulator and the plug, and forming an opening in the first film. The method further includes forming a second insulator in the opening to form an air gap in the opening, removing the first film after forming the second insulator, to expose the plug, and forming an interconnect on the exposed plug.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: October 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naomi Fukumaki
  • Patent number: 10086474
    Abstract: A protective film applying apparatus includes a protective film forming and cleaning unit for forming a protective film on a surface of a wafer and cleaning the protective film away. A coverage state detector detects a coverage state of the protective film, and a controller determines whether or not the protective film has a film thickness falling within a predetermined range. If the controller decides that the thickness of the protective film does not fall in the predetermined range, the controller operates the protective film forming and cleaning unit to clean away the protective film, performs a pretreating process selected depending on the film thickness on the surface, and operates the protective film forming and cleaning unit to form a protective film again on the surface of the wafer.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: October 2, 2018
    Assignee: Disco Corporation
    Inventors: Senichi Ryo, Kenta Nakano, Yukinobu Ohura, Toshiyuki Yoshikawa
  • Patent number: 10066294
    Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing: supplying a precursor gas to the substrate in a process chamber through a first nozzle; supplying an oxygen-containing gas to the substrate in the process chamber through a second nozzle made of quartz and differing from the first nozzle; and supplying a hydrogen-containing gas to the substrate in the process chamber through the second nozzle. The method further includes, prior to performing the act of forming the film, etching a surface of the second nozzle to a depth which falls within a range of 15 ?m or more and 30 ?m or less from the surface of the second nozzle.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: September 4, 2018
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Ryota Sasajima, Shintaro Kogura, Masayoshi Minami
  • Patent number: 10050133
    Abstract: In a pin diode, a new means for a soft recovery other than the means for the soft recovery using an anode layer with a low concentration and a local lifetime control is provided. A semiconductor device comprising a drift layer of a first conductivity type provided on a semiconductor substrate of a first conductivity type, a front-surface-side region of a second conductivity type provided on a front surface side of the drift layer, an insulating-film layer provided on a front surface side of the front-surface-side region with a thickness thinner than a natural oxide film, and a metal layer provided on a front surface side of the insulating-film layer is provided.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: August 14, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Eri Ogawa, Takashi Yoshimura
  • Patent number: 10041167
    Abstract: Methods are described for a cyclical deposition and curing process. More particularly, the implementations described herein provide a cyclic sequential deposition and curing process for filling features formed on a substrate. Features are filled to ensure electrical isolation of features in integrated circuits formed on a substrate. The processes described herein use flowable film deposition processes that have been effective in reducing voids or seams produced in features formed on a substrate. However, conventional gap-filling methods using flowable films typically contain dielectric materials that have undesirable physical and electrical properties. In particular, film density is not uniform, film dielectric constant varies across the film thickness, film stability is not ideal, film refractive index is inconsistent, and resistance to dilute hydrofluoric acid (DHF) is not ideal in conventional flowable films.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: August 7, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jingmei Liang, Jung Chan Lee, Jinrui Guo, Mukund Srinivasan
  • Patent number: 10043666
    Abstract: Embodiments described herein generally relate to a substrate processing system, such as an etch processing system. In one embodiment, a method of processing a substrate is disclosed herein. The method includes removing a native oxide from a surface of the substrate, baking the substrate in a pre-treatment thermal chamber such that double atomic steps are formed on the surface of the substrate, and forming an epitaxial layer on the substrate after the substrate is baked.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: August 7, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Errol Antonio C. Sanchez, Zhiyuan Ye, Keun-Yong Ban
  • Patent number: 10037905
    Abstract: Treatment of carbon-containing low-k dielectric with UV radiation and a reducing agent enables process-induced damage repair. Also, treatment with a reducing agent and UV radiation is effective to clean a processed wafer surface by removal of metal oxide (e.g., copper oxide) and/or organic residue of CMP slurry from the planarized surface of a processed wafer with or without low-k dielectric. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metalization, post-planarization, or both, and/or provide effective post-planarization surface cleaning to improve adhesion of subsequently applied dielectric barrier and/or other layers.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: July 31, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Bhadri Varadarajan, George A. Antonelli, Bart van Schravendijk
  • Patent number: 10008588
    Abstract: The amount of water and hydrogen contained in an oxide semiconductor film is reduced, and oxygen is supplied sufficiently from a base film to the oxide semiconductor film in order to reduce oxygen deficiencies. A stacked base film is formed, a first heat treatment is performed, an oxide semiconductor film is formed over and in contact with the stacked base film, and a second heat treatment is performed. In the stacked base film, a first base film and a second base film are stacked in this order. The first base film is an insulating oxide film from which oxygen is released by heating. The second base film is an insulating metal oxide film. An oxygen diffusion coefficient of the second base film is smaller than that of the first base film.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: June 26, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Imoto, Yuhei Sato
  • Patent number: 9985245
    Abstract: The present invention provides an organic light emitting device, a manufacturing method thereof and a display device. In the organic light emitting device provided by the present invention, a first inorganic thin film entirely covers a pre-encapsulation layer and an organic light emitting unit, and the first inorganic thin film has a denser molecular structure compared with the pre-encapsulation layer, thereby more effectively preventing water and oxygen from invading the organic light emitting unit via the pre-encapsulation layer to influence the service life of the organic light emitting unit.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: May 29, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Yulin Wang
  • Patent number: 9984869
    Abstract: A method is for forming a nitride or oxide film by plasma-assisted cyclic deposition, one cycle of which includes: feeding a first reactant, a second reactant, and a precursor to a reaction space where a substrate is placed, wherein the second reactant flows at a first flow ratio wherein a flow ratio is defined as a ratio of a flow rate of the second reactant to a total flow rate of gases flowing in the reaction space; and stopping feeding the precursor while continuously feeding the first and second reactants at a flow ratio which is gradually reduced from the first flow ratio to a second flow ratio while applying RF power to the reaction space to expose the substrate to a plasma. The second reactant is constituted by a hydrogen-containing compound or oxygen-containing compound.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: May 29, 2018
    Assignee: ASM IP Holding B.V.
    Inventor: Timothee Julien Vincent Blanquart
  • Patent number: 9966251
    Abstract: Provided is a method of manufacturing a semiconductor device.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: May 8, 2018
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Ryota Sasajima, Yoshiro Hirose, Yosuke Ota, Naonori Akae, Kojiro Yokozawa
  • Patent number: 9966252
    Abstract: Provided is a method of manufacturing a semiconductor device.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: May 8, 2018
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Ryota Sasajima, Yoshiro Hirose, Yosuke Ota, Naonori Akae, Kojiro Yokozawa
  • Patent number: 9960246
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an interfacial layer formed over the substrate, and an insertion layer formed over the interfacial layer. The semiconductor structure further includes a gate dielectric layer formed over the insertion layer and a gate structure formed over the gate dielectric layer. The insertion layer and the gate dielectric layer may be metal oxides where the insertion layer has an oxygen coordination number greater than the gate dielectric layer.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Lian, Chih-Lin Wang, Kang-Min Kuo, Chih-Wei Lin
  • Patent number: 9934960
    Abstract: A technique capable of suppressing the generation of foreign matter in a process container involves a method of manufacturing a semiconductor device including: (a) supplying a source gas to a substrate in a process container; (b) supplying an inert gas to an inner wall of an opening of the process container at a first flow rate while performing (a); (c) supplying a reactive gas to the substrate; and (d) supplying the inert gas to the inner wall at a second flow rate lower than the first flow rate while performing (c).
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: April 3, 2018
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Hideki Horita, Risa Yamakoshi, Masato Terasaki
  • Patent number: 9887129
    Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: February 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Jia Hsieh, Long-Jie Hong, Chih-Lin Wang, Kang-Min Kuo
  • Patent number: 9871058
    Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: January 16, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiro Takahashi, Takuya Hirohashi, Masashi Tsubuku, Noritaka Ishihara, Masashi Oota
  • Patent number: 9865458
    Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing: forming a first layer by supplying a precursor gas including a chemical bond of a first element and carbon and a first catalyst gas to the substrate; exhausting the precursor gas and the first catalyst gas through an exhaust system; forming a second layer by supplying a reaction gas including a second element and a second catalyst gas to the substrate to modify the first layer; and exhausting the reaction gas and the second catalyst gas through the exhaust system. At least in a specific cycle, the respective gases are supplied and confined in the process chamber while closing the exhaust system in at least one of the act of forming the first layer and the act of forming the second layer.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: January 9, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Ryuji Yamamoto, Yoshiro Hirose, Satoshi Shimamoto
  • Patent number: 9853212
    Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: December 26, 2017
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Gurtej S. Sandhu
  • Patent number: 9837296
    Abstract: An electrostatic chuck apparatus is disclosed which can be prevented from being damaged or fractured when the temperature abruptly increases or decreases when plasma is irradiated on a plate-like specimen, the heater is heated, or the like, and can also prevent corrosion when a corrosive gas or plasma is provided. The electrostatic chuck apparatus has an electrostatic chuck portion 2 having a mounting plate 11 made of a corrosion-resistant ceramic, a supporting plate 12 which is integrated with the mounting plate 11 so as to support the mounting plate 11 and is made of an insulating ceramic having a larger thermal conductivity than the thermal conductivity of the corrosion-resistant ceramic, and an internal electrode for electrostatic adsorption 13 provided between the mounting plate 11 and the supporting plate 12; and a temperature-controlling base portion 3 which adjusts the electrostatic chuck portion 2 to a desired temperature.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 5, 2017
    Assignee: Sumitomo Osaka Cement Co., Ltd.
    Inventors: Shinichi Maeta, Yoshiaki Moriya, Kei Furuuchi
  • Patent number: 9829797
    Abstract: Disclosed are a cleaning composition for photolithography and a method of forming a photoresist pattern using the same. The cleaning composition, necessary for forming a photoresist pattern having a high aspect ratio, includes water and a compound represented by Chemical Formula 1 below: wherein R is H or OH, x is an integer selected from 1 to 100, y is an integer selected from 0 to 100, and z is an integer selected from 0 to 100. This cleaning composition is useful for forming a pattern using any of a variety of light sources, and also, even when it is difficult to form a fine pattern as desired using a photoresist alone, a fine pattern can be realized at a desired level of fineness and production costs can be reduced.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: November 28, 2017
    Assignee: YOUNG CHANG CHEMICAL CO., LTD
    Inventors: Seung Hun Lee, Seung Hyun Lee, Sang Woong Yoon, Gyeong Guk Ham
  • Patent number: 9831274
    Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: November 28, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiro Takahashi, Takuya Hirohashi, Masashi Tsubuku, Noritaka Ishihara, Masashi Oota
  • Patent number: 9812320
    Abstract: According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a subsaturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: November 7, 2017
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami Pore, Werner Knaepen, Bert Jongbloed, Dieter Pierreux, Steven R. A. Van Aerde, Suvi Haukka, Atsuki Fukuzawa, Hideaki Fukuda
  • Patent number: 9761671
    Abstract: A spalling process can be employed to generate a fracture at a predetermined depth within a high quality crystalline nitride substrate, such as a bulk GaN substrate. A first crystalline conductive film layer can be separated, along the line of fracture, from the crystalline nitride substrate and subsequently bonded to a layered stack including a traditional lower-cost substrate. If the spalled surface of the first crystalline conductive film layer is exposed in the resulting structure, the structure can act as a substrate on which high quality GaN-based devices can be grown.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 12, 2017
    Assignee: Veeco Instruments, Inc.
    Inventors: Ajit Paranjpe, Craig Metzner, Joe Lamb
  • Patent number: 9754972
    Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: September 5, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiro Takahashi, Takuya Hirohashi, Masashi Tsubuku, Noritaka Ishihara, Masashi Oota
  • Patent number: 9711347
    Abstract: Methods and compositions for depositing rare earth metal-containing layers are described herein. In general, the disclosed methods deposit the precursor compounds comprising rare earth-containing compounds using deposition methods such as chemical vapor deposition or atomic layer deposition. The disclosed precursor compounds include a cyclopentadienyl ligand having at least one aliphatic group as a substituent and an amidine ligand.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: July 18, 2017
    Assignee: American Air Liquide, Inc.
    Inventors: Venkateswara R. Pallem, Christian Dussarrat, Wontae Noh
  • Patent number: 9704856
    Abstract: A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate structures in a capacitor region while forming contacts to source and drain (S/D) regions in a CMOS region. Gate structures are cut in the CMOS region and the capacitor region by etching a trench across the gate structures and filling the trench with a dielectric material. The gate structures and the dielectric material in the trench in the capacitor region are removed to form a position for an insulator and a second electrode. The insulator is deposited in the position. Gate metal is deposited to form gate conductors in the CMOS region and the second electrode in the capacitor region.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 9685320
    Abstract: The embodiments herein focus on plasma enhanced atomic layer deposition (PEALD) processes. Conventional PEALD techniques result in films having high quality at the bottom and top of a feature, but low quality on the sidewalls. The disclosed embodiments achieve more uniform film quality as evidenced by more uniform wet etch rates and electrical properties throughout the film. The disclosed embodiments may use one or more of a relatively high deposition temperature, a relatively high RF power for generating the plasma, and/or relatively long RF plasma exposure duration during each cycle of the PEALD reaction.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: June 20, 2017
    Assignee: Lam Research Corporation
    Inventors: Hu Kang, Wanki Kim, Adrien LaVoie
  • Patent number: 9685346
    Abstract: Provided are a method of generating plasma and a method of fabricating a semiconductor device including the method, which may improve selectivity in an etching process and minimize damage to layers. The method of generating plasma includes generating first plasma by supplying at least one first process gas into a first remote plasma source (RPS) and applying first energy having a first power at a first duty ratio, and generating second plasma by supplying at least one second process gas into a second RPS and applying second energy having a second power at a second duty ratio.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: June 20, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gon-jun Kim, Sam Hyungsam Kim, Sangheon Lee
  • Patent number: 9673306
    Abstract: The amount of water and hydrogen contained in an oxide semiconductor film is reduced, and oxygen is supplied sufficiently from a base film to the oxide semiconductor film in order to reduce oxygen deficiencies. A stacked base film is formed, a first heat treatment is performed, an oxide semiconductor film is formed over and in contact with the stacked base film, and a second heat treatment is performed. In the stacked base film, a first base film and a second base film are stacked in this order. The first base film is an insulating oxide film from which oxygen is released by heating. The second base film is an insulating metal oxide film. An oxygen diffusion coefficient of the second base film is smaller than that of the first base film.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: June 6, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Imoto, Yuhei Sato
  • Patent number: 9643844
    Abstract: Provided are methods for the deposition of films comprising SiCN and SiCON. Certain methods involve exposing a substrate surface to a first and second precursor, the first precursor having a formula (XyH3-ySi)zCH4-z, (XyH3-ySi)(CH2)(SiXpH2-p)(CH2)(SiXyH3-y), or (XyH3-ySi)(CH2)n(SiXyH3-y), wherein X is a halogen, y has a value of between 1 and 3, and z has a value of between 1 and 3, p has a value of between 0 and 2, and n has a value between 2 and 5, and the second precursor comprising a reducing amine. Certain methods also comprise exposure of the substrate surface to an oxygen source to provide a film comprising SiCON.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: May 9, 2017
    Assignee: Applied Materials, Inc.
    Inventor: David Thompson
  • Patent number: 9607829
    Abstract: A method of surface functionalization for high-k deposition is provided in several embodiments. The method provides interface layer growth with low effective oxide thickness and good nucleation behavior for high-k deposition. The method includes providing a substrate that is at least substantially free of oxygen on a surface of the substrate, forming an interface layer on the surface of the substrate by exposing the surface of the substrate to one or more pulses of ozone gas, modifying the interface layer by exposing the interface layer to one or more pulses of a treatment gas containing a functional group to form a functionalized interface layer terminated with the functional group, and depositing a high-k film on the functionalized interface layer.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: March 28, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N. Tapily, Robert D. Clark
  • Patent number: 9587308
    Abstract: A cleaning method includes performing a first cleaning process of supplying a fluorine-based gas from a first nozzle heated to a first temperature and a nitrogen oxide-based gas from a second nozzle heated to a first temperature into a process chamber heated to the first temperature in order to remove on surfaces of members in the process chamber by a thermochemical reaction, changing in internal temperature of the process chamber to a second temperature higher than the first temperature, and performing a second cleaning process of supplying a fluorine-based gas from the first nozzle heated to the second temperature into the process chamber heated to the second temperature in order to remove substances remaining on the surfaces of the members in the process chamber after removing the deposits by the thermochemical reaction and to remove deposits deposited in the first nozzle by the thermochemical reaction.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: March 7, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kenji Kameda, Ryuji Yamamoto, Yuji Urano
  • Patent number: 9551070
    Abstract: Corrosion resistant substrate supports and methods of making corrosion resistant substrate supports are provided herein. In some embodiments, a method of making corrosion resistant substrate supports includes exposing the substrate support disposed within a substrate processing chamber to a process gas comprising an aluminum containing precursor; and depositing an aluminum containing layer atop surfaces of the substrate support.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: January 24, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Mei Chang, Chien-Teh Kao, Juno Yu-Ting Huang