Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate, word lines, mask layers, spacers, a conductive plug, a conductive cap layer, and a dielectric layer. The word lines are disposed over the semiconductor substrate. The mask layers are disposed over the plurality of word line, respectively. The spacers are disposed over opposite sidewalls of the word lines and opposite sidewalls of the mask layers, respectively. The conductive plug is disposed between the word lines. The conductive cap layer is disposed over the conductive plug. The dielectric layer is disposed over the word lines and the spacers. Each of the spacers includes an inner spacer, an outer spacer, and an air gap. The inner spacer is in contact with the respective word line and the respective mask layer. The air gap is disposed between the inner spacer and the outer spacer.

Abstract: A method of forming a semiconductor structure includes annealing a surface of a substrate in an ambient of hydrogen to smooth the surface, pre-cleaning the surface of the substrate, depositing a high-? dielectric layer on the pre-cleaned surface of the substrate, performing a re-oxidation process to thermally oxidize the surface of the substrate; performing a plasma nitridation process to insert nitrogen atoms in the deposited high-? dielectric layer, and performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitridated high-? dielectric layer.

Abstract: A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

Abstract: A method of processing a substrate includes: (a) providing a substrate; (b) supplying a processing gas comprising H2O-containing radicals to the substrate; (c) supplying a gas including at least one element of Si, Ti, Mo, Al, W, Hf or Zr and a halogen element to the substrate; (d) supplying a gas including one or both of an oxygen element and a nitrogen element to the substrate after (c); and (e) repeating (c) and (d).

Abstract: A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between ?1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

Abstract: Methods for forming a semiconductor device structure are provided. The methods may include forming a molybdenum nitride film on a substrate by atomic layer deposition by contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, contacting the substrate with a second vapor phase reactant comprise a nitrogen precursor, and contacting the substrate with a third vapor phase reactant comprising a reducing precursor. The methods provided may also include forming a gate electrode structure comprising the molybdenum nitride film, the gate electrode structure having an effective work function greater than approximately 5.0 eV. Semiconductor device structures including molybdenum nitride films are also provided.

Abstract: A mask structure, a semiconductor structure and methods for manufacturing the same are disclosed. The method for manufacturing the mask structure includes: forming a pattern transfer layer, a first etching stop layer, a first sacrificial layer and a first hard mask layer sequentially stacked from bottom to top; patterning the first sacrificial layer and the first hard mask layer, to obtain a first sacrificial pattern, the first sacrificial pattern exposing the first etching stop layer; forming a first initial mask pattern on side walls of the first sacrificial pattern; removing the first sacrificial pattern; removing, based on the first initial mask pattern, a part of the first etching stop layer of which a top surface being exposed; removing the first initial mask pattern, and using the remaining part of the first etching stop layer on the upper surface of the pattern transfer layer as a first mask pattern.

Abstract: A method for manufacturing a sensor includes etching an insulator layer disposed over a substrate to define an opening exposing a sensor surface of a sensor disposed on the substrate, a native oxide forming on the sensor surface; sputtering the sensor surface with a noble gas to at least partially remove the native oxide from the sensor surface; and annealing the sensor surface in a hydrogen atmosphere.

Abstract: A method for solvent-free perovskite deposition. The method comprises loading a lead target and one or more samples adhered to a substrate holder into a deposition chamber, pumping down to a high vacuum pressure, and backfilling the deposition chamber with the vapor of a salt precursor to form a perovskite material.

Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.

Abstract: The present invention relates to a ruthenium thin film-forming method for forming a ruthenium thin film using a ruthenium precursor, in which tricarbonyl (?4-methylene-1,3-propanediyl) ruthenium ((CO)3Ru-TMM)) having a structure represented by the following formula 1 is used as the ruthenium precursor, and the method includes a stage of forming a ruthenium thin film by an atomic layer deposition at a temperature ranging from 200° C. to 350° C. using this ruthenium precursor and a reaction gas. As the reaction gas, one or more selected from the group consisting of oxygen, hydrogen, water and ammonia are preferably applied.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor device including a first substrate; a capacitor structure positioned on the first substrate and including an exposed portion; a contact structure deposited on the exposed portion; an assistant layer positioned between the contact structure and the exposed portion; and a bonding structure positioned on the contact structure. The assistant layer includes germanium or silicon germanium.

Abstract: An electric field variable gas sensor includes a semiconductor substrate, an insulating film disposed on the semiconductor substrate, a semiconductor thin film material disposed on a part of the semiconductor substrate and a part of the insulating film, a gas molecule adsorption inducing material disposed on the semiconductor thin film material, a first electrode disposed on the semiconductor substrate to be spaced apart from the semiconductor thin film material, and a second electrode disposed on the insulating film to be connected with the semiconductor thin film material.

Abstract: The present application provides a method for fabricating a semiconductor device. The method includes providing a first substrate; sequentially stacking a lower dielectric layer, a first dielectric layer, and a higher dielectric layer on the first substrate; forming a capacitor structure on the first substrate, along the lower dielectric layer, the first dielectric layer, and the higher dielectric layer, and extending upwardly from the higher dielectric layer; forming a second dielectric layer on the higher dielectric layer; forming a contact opening along the second dielectric layer to expose an exposed portion of the capacitor structure; selectively forming an assistant layer on the exposed portion over the second dielectric layer and the higher dielectric layer; forming a contact structure on the exposed portion and in the contact opening; and forming a bonding structure on the contact structure.

Abstract: A manufacturing method for capacitor structure includes: forming a dielectric layer on a first electrode, wherein the dielectric layer includes metal oxide layers doped with preset oxides, and part of the preset oxide and a metal oxide share oxygen atoms; and forming a second electrode on the dielectric layer, wherein the first electrode, the dielectric layer and the second electrode constitute a capacitor structure.

Abstract: Field effect transistors having field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, and methods of fabricating field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, are described. In an example, an integrated circuit structure includes a semiconductor channel structure including a monocrystalline material. A gate dielectric is over the semiconductor channel structure, the gate dielectric including a high-k dielectric layer on a dipole material layer, and the dipole material layer distinct from the high-k dielectric layer. A gate electrode has a workfunction layer on the high-k dielectric layer, the workfunction layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.

Abstract: Disclosed is a substrate processing apparatus and the method of processing an exhaust gas. The substrate processing apparatus and the method of processing an exhaust gas according to the present invention, an exhaust gas decomposition module may decompose a source gas exhausted from a process chamber to decompose a ligand of the source gas. Also, the ligand and the source gas of which the ligand has been decomposed may be put in a stabilized state by reacting with separately supplied O2, N2O, or O3, and then, may be changed to a mixed gas including a reactant gas mixed therewith. Subsequently, the mixed gas may flow into the exhaust pump and may be emitted. Alternatively, the ligand and the source gas may be mixed with the reactant gas and may be emitted.

Abstract: Provided are a method for manufacturing a single-crystal semiconductor layer. The method of manufacturing the single crystalline semiconductor layer includes performing a unit cycle multiple times, wherein the unit cycle includes a metal precursor pressurized dosing operation in which a metal precursor is adsorbed on a surface of a single crystalline substrate by supplying the metal precursor onto the single crystalline substrate while an outlet of a chamber in which the single crystalline substrate is loaded is closed such that a reaction pressure in the chamber is increased; a metal precursor purge operation; a reactive gas supplying operation in which a reactive gas is supplied into the chamber to cause a reaction of the reactive gas with the metal precursor adsorbed on the single crystalline substrate after the metal precursor purge operation; and a reactive gas purge operation.

Abstract: A method includes forming an interfacial layer over a substrate; forming a quasi-antiferroelectric (QAFE) layer over the interfacial layer, in which forming the QAFE layer comprises performing an atomic layer deposition (ALD) cycle, and the ALD cycle includes performing a first sub-cycle for X time(s), in which the first sub-cycle comprises providing a Zr-containing precursor; performing a second sub-cycle for Y time(s), in which the second sub-cycle comprises providing a Hf-containing precursor; and performing a third sub-cycle for Z time(s), in which the third sub-cycle comprises providing a Zr-containing precursor, and in which X+Z is at least three times Y; and forming a gate electrode over the QAFE layer.

Abstract: The invention provides a RRAM structure, which includes a substrate, a high voltage transistor, and a RRAM cell. The high voltage transistor includes a drift region, a gate structure, a source region, a drain region, and an isolation structure. The drift region is located in the substrate. The gate structure is located on the substrate and on a portion of the drift region. The source region and the drain region are located in the substrate on two sides of the gate structure. The drain region is located in the drift region. The isolation structure is located in the drift region and between the gate structure and the drain region. The RRAM cell includes a first electrode, a resistive switching layer, and a second electrode sequentially located on the drain region. The RRAM cell is electrically connected to the high voltage transistor.

Abstract: A deposition method of forming silicon oxide films collectively on a plurality of substrates in a processing container performs a plurality of execution cycles each of which includes: supplying a silicon material gas containing an organoamino-functionalized oligosiloxane compound into the processing container; and supplying an oxidizing gas into the processing container adjusted to a pressure of 1 Torr to 10 Torr (133 Pa to 1333 Pa).

Abstract: A high electron mobility transistor (HEMT) includes a GaN epi-layer, a first passivation layer, a source electrode metal, a drain electrode metal, a gate electrode metal, and a field plate. The first passivation layer is deposited on the GaN epi-layer. The source electrode metal, the drain electrode metal, and the gate electrode are recessed into the first passivation layer and deposited on the GaN epi-layer. The source electrode metal has a source field plate with a source field plate length Lsf. The drain electrode metal has a drain field plate with a drain field plate length Ldf, wherein Ldf>Lsf. The gate electrode is situated between the source electrode metal and the drain electrode metal. The field plate is situated between the gate electrode and the drain electrode metal.

Abstract: Embodiments of the present disclosure generally relate to protective coatings on an aerospace component and methods for depositing the protective coatings. The protective coating can be anti-coking coatings to reduce or suppress coke formation when the aerospace component is heated in the presence of a fuel. In one or more embodiments, a method for depositing the protective coating on an aerospace component includes exposing the aerospace component to a cleaning process to produce a cleaned surface on the aerospace component and sequentially exposing the aerospace component to a precursor and a reactant to form a protective coating on the cleaned surface of the aerospace component by an atomic layer deposition (ALD) process. The aerospace component can be one or more of a fuel nozzle, a combustor liner, a combustor shield, a heat exchanger, a fuel line, a fuel valve, or any combination thereof.

Abstract: Described herein are conformal films and methods for forming a conformal metal or metalloid doped silicon nitride dielectric film wherein the conformal metal is zirconium, hafnium, titanium, tantalum, or tungsten. A method includes providing a substrate in a reactor; introducing into the reactor an at least one metal precursor which reacts; purging the reactor with a purge gas; introducing into the reactor an organoaminosilane precursors to react on at least a portion of the surface of the substrate to provide a chemisorbed layer; introducing a plasma comprising nitrogen and an inert gas into the reactor to react with at least a portion of the chemisorbed layer and provide at least one reactive site wherein the plasma is generated; and optionally purge the reactor with an inert gas; and the steps are repeated until a desired thickness of the conformal metal nitride film is obtained.

Abstract: Provided are a logic switching device and a method of manufacturing the same. The logic switching device may include a domain switching layer adjacent to a gate electrode. The domain switching layer may include a ferroelectric material region and an anti-ferroelectric material region. The domain switching layer may be a non-memory element. The logic switching device may include a channel, a source and a drain both connected to the channel, the gate electrode arranged to face the channel, and the domain switching layer provided between the channel and the gate electrode.

Abstract: When a gas supplied to a gas injection unit is switched from a first processing gas to a second processing gas, a controller of a gas supply system performs control to open a first supply on/off valve connected to the gas injection unit and provided in a first gas supply line for supplying the first processing gas and a second exhaust on/off valve provided in a first gas exhaust line branched from the first gas supply line, close a second supply on/off valve connected to the gas injection unit and provided in a second gas supply line for supplying the second processing gas and a first exhaust on/off valve provided in a second gas exhaust line branched from the second gas supply line; and then open the second supply on/off valve and the first exhaust on/off valve and close the first supply on/off valve and the second exhaust on/off valve.

Abstract: Various aspects of a light extraction substrate, an organic light emitting device, and methods of fabrication are provided. A light extraction substrate of an organic light-emitting device includes a light-scattering layer disposed on a base substrate and contains a first material, and a number of holes (hole diameters ranging from 350 nm to 450 nm) extending between the first surface and the second surface. A planarization layer (thickness not greater than 200 nm) is disposed on the light-scattering layer and contains a second material.

Abstract: A capacitor and a DRAM device, the capacitor including a lower electrode; a dielectric layer structure on the lower electrode, the dielectric layer structure including a first zirconium oxide layer, a hafnium oxide layer, and a second zirconium oxide layer sequentially stacked; and an upper electrode on the dielectric layer structure, wherein the hafnium oxide layer has a tetragonal crystal phase or an orthorhombic crystal phase.

Abstract: Methods for forming a doped metal oxide film on a substrate by cyclical deposition are provided. In some embodiments, methods may include contacting the substrate with a first reactant comprising a metal halide source, contacting the substrate with a second reactant comprising a hydrogenated source and contacting the substrate with a third reactant comprising an oxide source. In some embodiments, related semiconductor device structures may include a doped metal oxide film formed by cyclical deposition processes.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are included. The method of manufacturing the semiconductor device includes forming a hafnium oxide layer on a substrate and crystallizing the hafnium oxide layer by using a hafnium cobalt oxide layer as a seed layer. According to the method of manufacturing the semiconductor device, a thin-film hafnium oxide layer may be easily crystallized.

Abstract: Chalcogen silane precursors are described. Methods for depositing a silicon nitride (SixNy) film on a substrate are described. The substrate is exposed to the chalcogen silane and a reactant to deposit the silicon nitride (SixNy) film. The exposures can be sequential or simultaneous. The chalcogen silane may be substantially free of halogen. The chalcogen may be selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).

Abstract: Embodiments described and discussed herein provide methods for selectively depositing a metal oxides on a substrate. In one or more embodiments, methods for forming a metal oxide material includes positioning a substrate within a processing chamber, where the substrate has passivated and non-passivated surfaces, exposing the substrate to a first metal alkoxide precursor to selectively deposit a first metal oxide layer on or over the non-passivated surface, and exposing the substrate to a second metal alkoxide precursor to selectively deposit a second metal oxide layer on the first metal oxide layer. The method also includes sequentially repeating exposing the substrate to the first and second metal alkoxide precursors to produce a laminate film containing alternating layers of the first and second metal oxide layers. Each of the first and second metal alkoxide precursors contain different types of metals which are selected from titanium, zirconium, hafnium, aluminum, or lanthanum.

Abstract: A film forming method includes forming a film by sequentially performing operations for each of a plurality of kinds of reaction gases, the operations being of storing the reaction gas in a storage part to raise a pressure in the storage part to a first pressure and then discharging the reaction gas into the process vessel, while continuously supplying the counter gas, and purging by repeating multiple times operations of storing a purge gas in the storage part provided in the reaction gas supply passage to raise the pressure in the storage part to a second pressure higher than the first pressure, and discharging the purge gas into the process vessel. A flow rate of the counter gas supplied into the process vessel in the purging is smaller than a flow rate of the counter gas supplied into the process vessel in the forming the film.

Abstract: A control method for an autonomous vehicle is used in an autonomous vehicle including an engine, and a controller that controls an operation of the engine. In the control method, required driving force is set in accordance with an intervehicular distance between an own vehicle and a preceding vehicle when there is the preceding vehicle in front of the own vehicle. Also, when there is the preceding vehicle, a behavior of the preceding vehicle is predicted from a situation in front of the preceding vehicle. Further, when there is the preceding vehicle, sailing stop is executed based on the required driving force and the predicted behavior of the preceding vehicle. The sailing stop causes the engine to stop automatically while the own vehicle is traveling at vehicle speed equal to or higher than given vehicle speed.

Abstract: A method used in forming an electronic device comprising conductive material and ferroelectric material comprises forming a composite stack comprising multiple metal oxide-comprising insulator materials. At least one of the metal oxide-comprising insulator materials is between and directly against non-ferroelectric insulating materials. The multiple metal oxide-comprising insulator materials are of different composition from that of immediately-adjacent of the non-ferroelectric insulating materials. The composite stack is subjected to a temperature of at least 200° C. After the subjecting, the composite stack comprises multiple ferroelectric metal oxide-comprising insulator materials at least one of which is between and directly against non-ferroelectric insulating materials. After the subjecting, the composite stack is ferroelectric. Conductive material is formed and that is adjacent the composite stack. Devices are also disclosed.

Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

Abstract: Disclosed herein are metal filament memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a transistor having a source/drain region; and a metal filament memory device including an active metal and an electrolyte; wherein the electrolyte is coupled between the active metal and the source/drain region when the transistor is an n-type metal oxide semiconductor (NMOS) transistor, and the active metal is coupled between the electrolyte and the source/drain region when the transistor is a p-type metal oxide semiconductor (PMOS) transistor.

Abstract: A process for forming a lithium-metal-carbon film on a lithium metal structure. A metal-ligand complex is exposed to the metal ligand, such as for 5-30 seconds in a chemical vapor transfer reactor at a temperature of 100-180° C.

Abstract: Methods and apparatus for filling a high aspect ratio feature such as a via with ruthenium including: contacting a ruthenium liner with a ruthenium precursor within a high aspect ratio feature such as a via, wherein the ruthenium liner has a top surface within a high aspect ratio feature such as a via, and wherein the top surface comprises a halogen material such as iodine or bromine. Embodiments also relate to selective deposition of ruthenium within a high-aspect ratio feature such as a via.

Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may include silicon germanium. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The methods may include forming a high-k dielectric material overlying the oxygen-containing material.

Abstract: When a gas supplied to a gas injection unit is switched from a first processing gas to a second processing gas, a controller of a gas supply system performs control to open a first supply on/off valve connected to the gas injection unit and provided in a first gas supply line for supplying the first processing gas and a second exhaust on/off valve provided in a first gas exhaust line branched from the first gas supply line, close a second supply on/off valve connected to the gas injection unit and provided in a second gas supply line for supplying the second processing gas and a first exhaust on/off valve provided in a second gas exhaust line branched from the second gas supply line; and then open the second supply on/off valve and the first exhaust on/off valve and close the first supply on/off valve and the second exhaust on/off valve.

Abstract: A capacitor comprising a solid electrolytic capacitor element that contains a sintered porous anode body, a dielectric film that is formed by sequential vapor deposition and overlies the anode body, and a solid electrolyte that overlies the dielectric film is provided. A method for forming a solid electrolytic capacitor element is also provided.

Abstract: Embodiments of the present invention are directed to forming a sub-stoichiometric metal-oxide film using a modified atomic layer deposition (ALD) process. In a non-limiting embodiment of the invention, a first precursor and a second precursor are selected. The first precursor can include a metal and a first ligand. The second precursor can include the same metal and a second ligand. A substrate can be exposed to the first precursor during a first pulse of an ALD cycle. The substrate can be exposed to the second precursor during a second pulse of the ALD cycle. The second pulse can occur directly after the first pulse without an intervening thermal oxidant. The substrate can be exposed to the thermal oxidant during a third pulse of the ALD cycle.

Abstract: Cross bar array devices and methods of forming the same include first electrodes arranged adjacent to each other and extending in a first direction. Second electrodes are arranged transversely to the first electrodes. An electrolyte layer is disposed between the first electrodes and the second electrodes, the electrolyte layer comprising a nitridated dielectric material.

Abstract: Methods are provided for preparing TiO2 nanofiltration membranes for water purification are provided. The method can include supplying a titanium precursor gas into a reaction chamber, where the titanium precursor gas reacts with a base support of an anodic aluminum oxide, and the base support of an anodic aluminum oxide has a surface defining a plurality of pores therein. The reaction chamber can then be evacuated to remove any unreacted titanium precursor gas, and an alkoxide precursor gas can be supplied into a reaction chamber such that the alkoxide precursor gas reacts to with the titanium on the base support to form a hybrid titanium alkoxide. Thereafter, the base support cab be heated to remove the organic component to leave titanium oxide on the surface of the base support.

Abstract: An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access. The system may still further include a second remote plasma unit fluidly coupled with a second access of the chamber and configured to deliver a second precursor into the chamber through the second access. The first and second access may be fluidly coupled with a mixing region of the chamber that is separate from and fluidly coupled with the processing region of the chamber. The mixing region may be configured to allow the first and second precursors to interact with each other externally from the processing region of the chamber.

Abstract: Techniques are disclosed for passivation of transistor channel region interfaces. In some cases, the transistor channel region interfaces to be passivated include the interface between the semiconductor channel and the gate dielectric and/or the interface between the sub-channel semiconductor material and isolation material. For example, an aluminum oxide (also referred to as alumina) layer may be used to passivate channel/gate interfaces where the channel material includes silicon germanium, germanium, or a III-V material. The techniques can be used to reduce the interface trap density at the channel/gate interface and the techniques can also be used to passivate the channel/gate interface in both gate first and gate last process flows. The techniques may also include an additional passivation layer at the sub-channel/isolation interface to, for example, avoid incurring additional parasitic capacitance penalty.

Abstract: A raw material for forming a thin film that includes a compound represented by General Formula (1) below. In the formula, R1 represents a linear or branched alkyl group having 2 to 4 carbon atoms; R2 to R5 each independently represent a linear or branched alkyl group having 1 to 4 carbon atoms; A represents an alkanediyl group having 1 to 4 carbon atoms; and M represents titanium, zirconium or hafnium. Provided that when M represents zirconium, A represents an alkanediyl group having 3 or 4 carbon atoms. When M represents titanium or hafnium, it is preferred that A represents an alkanediyl group having 2 or 3 carbon atoms. When M represents zirconium, it is preferred that A represent an alkanediyl group having 3 carbon atoms.

Abstract: A conductive fill is provided in an opening of an interconnect layer. A seed layer is formed, a portion of which is then oxidized. The oxygen is removed in a treatment process and the surface of the de-oxidized seed layer is hydrolyzed to form a hydroxyl sublayer and moisturized. The conductive fill is formed over the hydroxyl sublayer.