Abstract: A metastable depassivation lithography process for fabricating microstructures on a surface which utilizes the energy contained in neutral metastable rare gas atoms to remove passivating atoms from selected areas of a surface. Removal of the passivating atoms in a pattern allows further chemical processing to add or remove material to the exposed areas. The neutral metastable rare gas atoms can be directed to the surface using atom optical techniques to effect a desired pattern of exposure by the atoms. Alternatively, a mask can be used to effect a desired pattern of exposure.

Abstract: A substrate processing system that includes a deposition chamber having a reaction zone, first and second electrodes, a mixed frequency RF power supply including a low frequency RF power source and a high frequency RF power source. The high frequency RF power supply provides enough power to form a plasma from a process gas introduced into the reaction zone and the low frequency RF power supply is configured to supply an asymmetrical waveform to either said first or second electrodes to bias the plasma toward the substrate.

Abstract: The present invention provides apparatus and a process for efficiently removing particles generated during a laser marking of the semiconductor wafer substrate, thereby improving the yield. The process of the invention for marking a semiconductor wafer substrate by a beam of laser radiation comprises the steps of flowing a gas over a marking region at a predetermined flow rate and removing the gas from the marking region at the same predetermined flow rate, thereby generating a gas flow having a predetermined flow rate over and adjacent the marking region so that particles produced from the semiconductor wafer substrate while it is being marked will be removed. In a preferred embodiment, the semiconductor wafer substrate may be mounted with its upper surface to be marked directed downwardly while the laser marking beam is directed upwardly to the substrate.

Abstract: Described are preferred processes for conditioning semiconductor devices with deuterium to improve operating characteristics and decrease depassivation which occurs during the course of device operation. Also described are semiconductor devices which can be prepared by such processes.

Abstract: A method for forming a gate dielectric having different thickness begins by providing a substrate (12). A sacrificial oxide (14) is formed overlying the substrate (12). A first portion (11) of the sacrificial oxide (14) is exposed to a carbon-containing plasma environment (20). This carbon-containing plasma environment (20) forms a carbon-containing layer (24) within the region (11). After forming this region (24), a wet etch chemistry (22) is used to remove remaining portions of the sacrificial oxide (14) without forming a layer (24) in the region (13). Furnace oxidation is then used to form regions (26a) and (26b) wherein the growth of region (26a) has been retarded by the presence of the region (24). Therefore, the regions (26a) and (26b) are differing in thickness and can be used to make different transistors having different current gains.

Abstract: Cu diffusion between Cu and Cu alloy interconnect members, e.g., lines, in a silicon oxide inter-layer dielectric is avoided or substantially reduced by converting an upper portion of the silicon oxide inter-layer dielectric between neighboring lines to silicon oxynitride and then depositing a capping layer. Embodiments include filling damascene trenches in a silicon oxide inter-layer dielectric with Cu or a Cu alloy, CMP to effect planarization such that the upper surfaces of the lines are substantially coplanar with the upper surface of the inter-layer dielectric and treating the exposed surfaces with a high strength ammonia plasma to ion bombard the exposed inter line silicon oxide with nitrogen atoms, thereby converting the upper portion to silicon oxynitride, while simultaneously removing or substantially reducing surface oxides on the lines. A silicon nitride capping layer is then deposited.

Abstract: A method for controlling the morphology of deposited silicon on a layer of silicon dioxide and semiconductor devices incorporating such deposited silicon are provided. The method comprises the steps of: providing a layer of silicon dioxide; implanting hydrogen ions into the layer of silicon dioxide by plasma source ion implantation; and forming a layer of polycrystalline silicon on the layer of silicon dioxide.

Abstract: A method of treating the surface of a semiconductor wafer is disclosed for making the wafer resistant to particle adhesion, the method involving the application of a uniform corona charge to the wafer surface. The corona charge is deposited on the wafer using commercially available tools, and if necessary, it may be later removed by immersing the wafer in deionized water or by depositing a compensating corona charge over the wafer of opposite polarity relative to the originally-applied charge.

Abstract: A system and method for using a nitrous oxide plasma treatment to eliminate defects at an interface between a stop layer and an integral layered dielectric. The system and method provide a reliable and simplified technology that eliminates the small bubble-like defects that can be common to thin nitride layers. The system includes a plasma device and a processing chamber. The method encompasses the steps of preparing a first integral layered dielectric on a substrate before depositing a stop layer thereupon. A plasma gas is then ionized. Preferably, the plasma gas is composed of nitrogen and oxygen. The stop layer is then exposed to the plasma gas until a primary surface of the stop layer is bombarded plane. A second integral layered dielectric is then formed on the primary surface. A top surface of the second integral layered dielectric is generally plane and parallel to the primary surface.

Abstract: A hydrogen plasma downstream treatment equipment comprises a first gas supply source for supplying a hydrogen gas, a second gas supply source for supplying a nitrogen fluoride gas, and a tube-like chamber used for surface treatment of a semiconductor layer by use of the hydrogen gas and the nitrogen fluoride gas. The chamber includes a plasma generator for activating the hydrogen gas and the nitrogen fluoride gas by introducing the nitrogen fluoride gas in which a flow rate ratio of the hydrogen gas and the nitrogen fluoride gas is in excess of 4, a processor placed in a downstream of the plasma generator to place the semiconductor layer therein, and gas flow controlling means for controlling the first gas supply source and the second gas supply source so as to set a flow rate of the nitrogen fluoride gas four times a flow rate of the hydrogen gas.

Abstract: A metal interconnection is formed on a dielectric layer. A pre-treatment is then performed to remove organic materials on the surface of the metal layer. The pre-treatment is done by plasma bombardment using NH.sub.3 and NO.sub.2 as the reaction gases. A thin oxide layer is subsequently deposited on the metal layer and on the dielectric layer. The oxide layer serves a buffer layer to eliminate the stress between the metal layer and subsequent silicon nitride layer. A silicon nitride layer is then formed on the thin oxide layer to act as a passivation layer.

Abstract: A method of manufacturing a semiconductor device with improved adhesion between the local interconnect etch stop layer and the thermal oxide in an isolation region. The thermal oxide is treated with an NH.sub.3 /N.sub.2 plasma. The local interconnect etch stop layer is either silicon nitride or silicon oxynitride. A layer of a dielectric material such as PECVD SiO.sub.2 is formed on the local interconnect etch stop layer.

Abstract: The nickel element is provided selectively, i.e., adjacent to part of the surface of an amorphous silicon film in a long and narrow opening. The amorphous silicon film is irradiated with linear infrared light beams emitted from respective linear infrared lamps while scanned with the linear beams perpendicularly to the longitudinal direction of the opening. The longitudinal direction of the linear beams are set coincident with that of the opening. The infrared light beams are absorbed by the silicon film mainly as thermal energy, whereby a negative temperature gradient is formed in the silicon film. The temperature gradient moves as the lamps are moved for the scanning. The direction of the negative temperature gradient is set coincident with the lamp movement direction and an intended crystal growth direction, which enables crystal growth to proceed parallel with a substrate uniformly over a long distance.

Abstract: A device for forming a deposited film is provided. It comprises (a) a reaction chamber; (b) a heating means for heating a substrate placed in the reaction chamber; (c) a starting gas introducing means for introducing starting gases into the reaction chamber, the gas introducing means having a means for introducing two or more kinds of gases alternately and intermittently into the reaction chamber; (d) a decomposing means for decomposing the starting gases in the reaction chamber so as to form a deposited film on the substrate heated by said heating means in the reaction chamber, the decomposing means having a light source which irradiates at least one kind of light into the reaction chamber to decompose the starting gases.

Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 10.sup.12 eV .sup.-1 cm.sup.-2 or less, which is brought by the above pre-treatment in the insulator film deposition process.

Abstract: To produce a high quality thin film by effectively removing the particles from the emitted substance and the oxygen retained under a high vacuum during the production of the thin film by laser ablation, there is provided a process for producing a thin film on a substrate by laser ablation in a vacuum chamber in which a laser beam is irradiated to a target to cause emission of a substance from the target and allowing the emitted substance to deposit on the substrate to grow a thin film on the substrate by laser ablation, the process including irradiating an ion beam to at least one of the substrate and a plume of the emitted substance formed between the substrate and the target.

Abstract: A method of fabricating a transistor having an improved salicided gate is provided. The method may include forming a gate (14) that is separated from a substrate (12) by a gate insulator (16). A spacer (22) may be formed proximate the gate (14) such that the spacer (22) exposes a top region (28) and a side region (30) of the gate (14). The top region (28) and the side region (30) of the gate (14) may be irradiated at an angle (38) to form a post amorphous region (32) within the gate (14). A reactive layer (42) may be formed adjacent the post amorphous region (32). A salicidation region (44) may be then formed between the post amorphous region (32) and the reactive layer (42). The reactive layer (42) may be removed to expose the salicidation region (44).

Abstract: A method of fabricating semiconductor devices which satisfactorily removes native oxide films and damaged layers which are formed on the surfaces of the conductor layers in the silicon substrates when contact holes are opened, and which tend to increase the contact resistances. A thin oxide film 5 is formed on the surface of a conductor region 3 in a silicon substrate 1 which is exposed at the bottom of the contact hole, and the oxide film 5 is then etched off with hydrogen-containing plasma. The native oxide film and/or damaged layer 3a, and the etching residue on the surface of the conduct layer 3 are satisfactorily removed, thus allowing provision of a contact structure with a low contact resistance regardless of whether the conductor type is P or N, without increasing the diameter of the contact hole.

Abstract: A method for forming upon a patterned layer within an integrated circuit an ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layer having a diminished pattern sensitivity. There is first provided a semiconductor substrate. Formed upon the semiconductor substrate is a patterned layer which provides a pattern sensitivity to an ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layer formed upon the patterned layer. The patterned layer is also susceptible to modification with a plasma which reduces the pattern sensitivity of the ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layer formed upon the patterned layer. The patterned layer is treated with the plasma. Finally, the ozone assisted Chemical Vapor Deposited (CVD) silicon oxide insulator layer is formed upon the patterned layer.

Abstract: A wafer is subjected to a plasma process, using plasma generated while a process gas is fed into a process room, and a plus DC voltage is applied to an electrostatic chuck in order to attract and hold the wafer on the electrostatic chuck by an electrostatic force. A minus DC voltage is applied to the electrostatic chuck while nitrogen gas is fed into the process room in order to cause DC discharge after the processed wafer is separated from the electrostatic chuck and before a next wafer is attracted and held on the electrostatic chuck. By doing so, plus electric charge in the gas is attracted to the electrostatic chuck, so that the surface of the electrostatic chuck is charged with plus electric charge, thereby preventing its attracting function from being deteriorated.

Abstract: A thin film is transferred from an initial substrate onto a final substrate. The process includes the following successive stages: joining of the thin film (112) onto a handle substrate (120) comprising a cleavage zone, elimination of the initial substrate, joining of the thin film (112) with a final substrate (132), and cleavage of the handle substrate (120) following the cleavage zone. The cleavage zone includes a film of micro-bubbles formed by ion implantation. The invention has, in particular, applications in the fabrication of three-dimensional structures of integrated circuits.

Abstract: An insulating layer may be fabricated on a microelectronic substrate by spinning a layer of spin-on-glass (SOG) on a microelectronic substrate and curing the SOG layer by irradiating the SOG layer with an electronic beam. Irradiating may take place simultaneously with heating the substrate to a temperature below about 500.degree. C. An underlying and/or overlying capping layer may also be provided. Alternatively, rather than irradiating the SOG layer, an overlying capping layer may be irradiated.

Abstract: A process for ROM coding is described. First, the active device areas and isolation regions are defined on a semiconductor substrate. Then, silicon isotopes (Si.sup.30) are implanted into the active device areas to form isotope regions. Next, the remaining portions of the MOSFET structures are then formed. Next, an interlayer dielectric layer, and a metal layer are sequentially deposited and patterned to finish the basic ROM structure. Upon the receipt of an order, a passivation layer is deposited overlaying the interlayer dielectric layer. Next, a photoresist layer is coated over the passivation layer, and code implant windows are patterned. Finally, neutron irradiation is performed to activate the silicon isotopes into N-type phosphorus ions.

Abstract: A method for providing a lateral conductive link between conductive elements, e.g., metals, placed on a first non-conductive material, wherein a second non-conductive material is placed on said first non-conductive material to form an interface therebetween in a region between the conductive elements. Energy is applied to the conductive elements to produce mechanical strains by thermal expansion in the conductive elements which initiate a rupturing of the interface between the non-conductive materials so as to provide at least one fissure therein extending between the conductive elements. The energy applied causes a portion of at least one of the conductive elements to flow in such fissure to provide a lateral conductive link between the conductive elements.

Abstract: Method of improving the resistance of a metal against degradation from exposure to fluorine released from a fluorine-containing material by forming a fluorine-barrier layer between the insulator material and the metal. The invention is especially useful in improving corrosion and poisoning resistance of metallurgy, such as aluminum metallurgy, in semiconductor structures. The invention also covers integrated circuit structures made by this method.

Abstract: The invention provides methods and apparatus for treating substrates and hazardous biological wastes. According to one exemplary method, at least one substrate is placed into a chamber and a vacuum is applied to the chamber. After the pressure within the chamber is sufficiently reduced, water vapor is introduced into the chamber and electromagnetic radiation energy is applied to produce a plasma. In one particularly preferable aspect, the chamber is allowed to reach a static condition before the water vapor is introduced. In this way, the water vapor is able to equally distribute itself throughout the volume of the chamber so that an equally distributed plasma can be produced upon application of the electromagnetic radiation energy.

Abstract: A superconductive device manufacturing method is disclosed, which can prevent the characteristic deterioration on the processed surface, reduce the number of process steps, and thereby shorten the manufacturing time. The superconductive device manufacturing method comprises the steps of: forming a YBCO film (301) on a substrate (201); forming a mask pattern (302) on the formed YBCO film (301); and etching the YBCO film (301) by use of the formed mask pattern (302) and a plasma including at least oxygen plasma.

Abstract: Rapid Thermal Processing of a semiconductor wafer is performed by scanning a laser beam across a silicon dioxide film in contact with a surface of the wafer. The silicon dioxide film absorbs the energy from the laser beam and converts the energy to heat. The heat, in turn, is transferred to the wafer. Temperature feedback can be obtained to increase control and uniformity of temperatures across the wafer.

Abstract: The present invention is for enlarging a freedom of layout including an air bridge pattern and enhancing the availability for various purposes. A mask layer including an air bridge pattern is formed on a (100) plane of a silicon substrate, isotropic etching is carried out until a point of intersection between tangents of a peripheral curved plane comes to under the air bridge pattern plane, and then an air bridge is formed by means of anisotropic etching.

Abstract: A method for hydrogenating a thin film semiconductor wafer and an apparatus for performing the method. The method comprises the steps of applying a pulsed potential having a predetermined amplitude, a predetermined frequency, and a predetermined pulse duration to the thin film semiconductor wafer while exposing the thin film semiconductor wafer to a hydrogen plasma. The apparatus performs this method through the utilization of an inductively-coupled plasma (ICP) source so as to allow saturation of device parameter improvements within a reduced process time of 5 minutes. The ICP source allows this reduced process time to be achieved in a low energy, high dose rate plasma immersion ion implantation (PIII) hydrogenation process according to the present invention.

Abstract: A method for treating via sidewalls comprising the steps of providing a substrate having a number of metallic wires already formed; depositing a liner oxide layer; depositing an organic spin-on-glass layer; and depositing a second oxide layer. The second oxide layer is planarized by a chemical-mechanical polishing method. Photolithographic and etching methods, employing oxygen plasma treatment as well as a wet etching removal method are used to form vias above the metallic layers. A hydrogen plasma treatment is performed for the via sidewalls to prevent the occurrence of out-gassing and to obtain superior electrical properties. A titanium/titanium nitride film is deposited, and aluminium or tungsten is deposited into the vias and to form aluminium or tungsten plugs, thus completing the manufacturing process according to this invention. A semiconductor device formned by this method is also described.

Abstract: A method to prevent volcano effect in tungsten plug deposition is described. The method is applied to both the contact plugs as well as the via plugs. For these purposes, the use of a nitrogen (N.sub.2) plasma of a specific recipe is introduced. It is shown that the presence of the nitrogen plasma improves the titanium nitride (TiN) barrier layer through annealing, and nitrogen stuffing of the grain boundaries. In addition, a titanium (Ti) layer must be used prior to the deposition of the TiN layer in order to improve adhesion. This step also enhances the titanium nitride barrier, and reduces the contact resistance (R.sub.c) of the contact-plugs as well. Finally, the nitrogen plasma process and the metal deposition can be done in one and the same equipment.

Abstract: A dependable ohmic contact with consistently low specific contact resistance (<1.times.10.sub.-6 .OMEGA.-cm.sup.2) to n-type GaAs (10) is produced by a three or four step procedure. The procedure, which is employed following implantation to form doped regions in the GaAs substrate for contacting thereto, comprises: (a) adsorbing or reacting sulfur or a sulfur-containing compound (26) with the GaAs surface (10') at locations where the contact metal (28) is to be deposited; (b) forming a metal contact layer (28) on the treated portions of the GaAs surface; (c) optionally forming a protective layer (30) over the metal contact; and (d) heating the assembly (metal and substrate) to form the final ohmic contact. The surface treatment provides a lower specific contact resistance of the ohmic contact. Elimination of gold in the ohmic contact further improves the contact, since intermetallic compounds formed between gold and aluminum interconnects ("purple plague") are avoided.

Abstract: Apparatus controls a wafer potential in a plasma system when the plasma is off to keep the wafer slightly negative at all times in order to reduce and eliminate the collection of charged particles on the wafer. The apparatus allows the wafer bias to be reduced to a small negative voltage and then holds that voltage. This greatly reduces the net positive flux to the wafer. A diode and a programmed power supply hold a minimum negative voltage on the back of the wafer electrode when the plasma density is decaying to zero.

Abstract: A method for stabilizing a polysilicon resistor. Formed through a conventional method upon a semiconductor substrate is a polysilicon resistor. The polysilicon resistor is treated with a nitrogen plasma. After treatment with the nitrogen plasma, the polysilicon resistor exhibits a high and stable resistance having minimal susceptibility to variation due to intrusion of hydrogen or other reactive species into the polysilicon resistor.

Abstract: A process for synthesizing wide band gap materials, specifically, GaN, employs plasma-assisted and thermal nitridation with NH.sub.3 to convert GaAs to GaN. Thermal assisted nitridation with NH.sub.3 can be employed for forming layers of substantial thickness (on the order of 1 micron) of cubic and hexagonal GaN on a GaAs substrate. Plasma-assisted nitridation of NH.sub.3 results in formation of predominantly cubic GaN, a form particularly useful in optoelectronic devices. Preferably, very thin GaAs membranes are employed to permit formation thereon of GaN layers of any desired thickness without concern for critical thickness constraints. The thin membranes are preferably formed either with an epitaxial bonding technique, or by undercut etching.

Abstract: A method of fabricating a field effect thin film transistor is provided, in which, after a first amorphous semiconductor layer having a predetermined thickness is deposited on a gate insulating film, the first amorphous semiconductor layer is transformed to a micro-crystal semiconductor layer by exposing it to hydrogen plasma produced by hydrogen discharge and, then, a second amorphous semiconductor layer is deposited on the micro-crystal semiconductor layer. According to this method, it is possible to fabricate a high performance and high quality field effect thin film transistor through a simplified step of forming the micro-crystal semiconductor which becomes a channel region thereof.

Abstract: A polycrystalline silicon (polysilicon) layer is fabricated by forming a polysilicon layer on a substrate, implanting argon into the polysilicon layer to selectively amorphize the polysilicon layer and recrystallizing the selectively amorphized polysilicon layer. The argon dosage and energy may be controlled so that the argon passes through the polysilicon layer into the substrate so that argon ions do not disturb recrystallization. By using argon amorphizing, excessive heating of the substrate during implantation is prevented and ion implanter contamination from conventional silicon implantation is prevented.

Abstract: A P-type impurity layer, a silicon monocrystal film, a silicon oxide film and a crystal silicon film are successively formed on a semiconductor substrate by introducing appropriate functional gases on the semiconductor substrate, while irradiating the semiconductor substrate with ionizing radiation or light at a temperature lower than 250.degree. C. After forming a photoresist on the crystal silicon film at a temperature lower than 250.degree. C., the resultant semiconductor substrate is subjected to etching by using the photoresist as a mask, so as to form a gate electrode B out of the silicon oxide film and a gate insulating film out of the silicon oxide film. Then, the resultant semiconductor substrate is subjected to etching again by using the gate electrode as a mask, so as to form a channel region out of the P-type impurity layer.

Abstract: A multi-chamber system for providing a process of a high degree of cleanliness in fabricating semiconductor devices such as semiconductor integrated circuits. The system comprises a plurality of vacuum apparatus (e.g., a film formation apparatus, an etching apparatus, a thermal processing apparatus, and a preliminary chamber) for fabrication of semiconductor devices. At least one of these vacuum apparatuses is a laser.

Abstract: The present invention relates to a process for the production of a random access memory of the preloading static type, in which use is made of a static random access memory constituted by MOS transistors formed from the memory flip-flop array and in which a particle or photon beam is applied to the said MOS transistors in such a way that the accumulated dose received exceeds a predetermined value.

Abstract: A method and apparatus for depositing material to conformally cover or fill holes within the surface of a semiconductor substrate. The preferred method includes the steps of coherently depositing a first thickness of the material onto the surface of the substrate; reverse sputtering the deposited material so as to coat the sidewalls of the contact holes with the deposited material; after the first thickness of the material is deposited onto the surface of the substrate, depositing a second thickness of the material onto the surface of the substrate; and while depositing the second thickness of the material onto the surface of the substrate, heating the substrate to enhance reflow of the material being deposited.

Abstract: A thin film transistor formed on a non-single crystal silicon layer is exposed to hydrogen ion radiated from hydrogen plasma at 300 degrees to 400 degrees centigrade so as to deactivate trapping levels in the non-single crystal silicon layer, and, thereafter, the thin film transistor is annealed in nitrogen atmosphere at 200 degrees to 300 degrees centigrade so as to evacuate residual hydrogen from, for example, a gate insulating layer, thereby improving the transistor characteristics of the thin film transistor.

Abstract: Nonpolar substrates comprising off-axis growth regions for the growth of polar semiconductors, and a method for making such substrates, are disclosed. According to the invention, an erodible material, such as a photoresist, is applied to a substrate at a site and is exposed to radiation at that site which has an linear variation in energy at the surface of the erodible material. Due to this variation in exposure energy, a taper results in the erodible material after development. The tapered region is then etched in a manner which etches both the erodible layer and the underlying substrate. The taper in the erodible layer provides a varying attenuation during the etching process such that the taper of the erodible layer is transferred to the substrate.

Abstract: A plasma-processing method used in processes for manufacturing semiconductor devices. During plasma processing, ultraviolet radiation is emitted from a region where a plasma is created. An ultraviolet radiation-blocking means blocks the ultraviolet radiation from impinging on the sample surface to protect it. The blocking means passes particles forming a plasma onto the sample surface. The particles passed through the ultraviolet radiation-blocking plates are implanted into the sample. Alternatively, the processed surface of the sample is etched, or a film is deposited on the processed surface of the sample.

Abstract: A new-type silicon material is produced by hydrogen ion implantation and subsequent annealing, the annealing being preferably in two steps. The present invention raises surface mobility of a silicon wafer and produces a buried high-resistivity layer beneath a silicon surface layer. The resulting products are particularly useful for the improvement of yield and speed and radiation hardness of very large scale integrated circuits.

Abstract: The present invention improves a current--voltage characteristic by perfectly eliminating defects in the polycrystal silicon layer of TFT by hydrogenation. In the first process, hydrogen is doped into the polycrystal silicon layer 16 of TFT 1 by the hydrogen plasma doping method to eliminate a greater part of the defects in the polycrystal silicon layer 16. Thereafter, in the second process, after an amorphous silicon nitride film 23 including hydrogen is formed on the polycrystal silicon layer 16 or on the stopper layer 17 provided on the polycrystal silicon layer 16, hydrogen is released from the amorphous silicon nitride film 23 including hydrogen by the annealing process and such released hydrogen is then diffused into the polycrystal silicon layer 16 in order to eliminate remaining defects in the polycrystal silicon layer 16.