Radiation Or Energy Treatment Modifying Properties Of Semiconductor Region Of Substrate (e.g., Thermal, Corpuscular, Electromagnetic, Etc.) Patents (Class 438/795)
  • Patent number: 11915953
    Abstract: Aspects of the present disclosure relate to apparatus, systems, and methods of measuring edge ring distance for thermal processing chambers. In one example, the distance measured is used to determine a center position shift of the edge ring.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: February 27, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Ole Luckner, Wolfgang R. Aderhold
  • Patent number: 11901195
    Abstract: Aspects of the present disclosure relate to methods, systems, and apparatus for conducting a radical treatment operation on a substrate prior to conducting an annealing operation on the substrate. In one implementation, a method of processing semiconductor substrates includes pre-heating a substrate, and exposing the substrate to species radicals. The exposing of the substrate to the species radicals includes a treatment temperature that is less than 300 degrees Celsius, a treatment pressure that is less than 1.0 Torr, and a treatment time that is within a range of 8.0 minutes to 12.0 minutes. The method includes annealing the substrate after the exposing of the substrate to the species radicals. The annealing includes exposing the substrate to molecules, an anneal temperature that is 300 degrees Celsius or greater, an anneal pressure that is within a range of 500 Torr to 550 Torr, and an anneal time that is less than 4.0 minutes.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: February 13, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Pradeep Sampath Kumar, Norman L. Tam, Dongming Iu, Shashank Sharma, Eric R. Rieske, Michael P. Kamp
  • Patent number: 11888084
    Abstract: Disclosed herein are laser scanning systems and methods of their use. In some embodiments, laser scanning systems can be used to ablatively or non-ablatively scan a surface of a material. Some embodiments include methods of scanning a multi-layer structure. Some embodiments include translating a focus-adjust optical system so as to vary laser beam diameter. Some embodiments make use of a 20-bit laser scanning system.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: January 30, 2024
    Assignee: nLIGHT, Inc.
    Inventor: Ken Gross
  • Patent number: 11878935
    Abstract: A method of coating a superstrate using a vacuum chuck containing ridges can comprise attaching the superstrate on the vacuum chuck; applying on the superstrate a liquid layer of a coating composition, the coating composition comprising a coating agent and a non-fluorinated solvent, wherein the non-fluorinated solvent has a boiling point of at least 165° C.; and solidifying the coating composition to form a solid coating layer. The material of the superstrate can have a thermal conductivity of not greater than 10 W/mK and the solid coating layer obtained after solidifying may comprise a smoothness value (SM) of not greater than 1%, the smoothness value being defined as SM=(CRD/CT)×100%, with CRD being a maximum roughness depth of the coating layer and CT an average thickness of the coating layer over a length of 10 mm of the solid coating layer.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: January 23, 2024
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Ilya L. Rushkin, Weijun Liu
  • Patent number: 11854800
    Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Szu-Ying Chen, Ya-Wen Chiu, Cheng-Po Chau, Yi Che Chan, Chih Ping Liao, YungHao Wang, Sen-Hong Syue
  • Patent number: 11768384
    Abstract: A cycloidal diffractive waveplate based star simulator generates a star field with very high precision star locations and accurate brightness. The present disclosure provides a star simulator that allows for a large FOV, modular, multi-star simulator capable of very high precision dynamic star locations for testing of high accuracy, large FOV star trackers. The system is composed of a light source, a polarization grating-based image [1], and an opto-mechanical system for steering the light. The light is projected onto a diffuse screen where the light is scattered, creating a functional point source at the screen. A star tracker or other device under test views the screen which has a multitude of projected spots (each with its own light source and beam steering device) positioned in a star field distribution appropriate for the simulated viewing direction.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: September 26, 2023
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventor: Joshua Lentz
  • Patent number: 11761704
    Abstract: An inspection apparatus includes: inspection chamber rows in each of which inspection chambers are arranged, the inspection chamber rows arranged in multiple stages and each of the inspection chambers being configured to accommodate therein a tester configured to inspect an inspection object on a chuck top; a refrigerant supplier configured to supply a refrigerant gas; and a controller. The refrigerant supplier includes: a refrigerant gas pipe connecting the chuck tops in each inspection chamber row to allow the refrigerant gas to pass therethrough; and a first heat exchanger disposed in the refrigerant gas pipe between the chuck tops to exchange heat with the refrigerant gas discharged from the chuck tops. Each of the chuck tops includes a heater configured to heat the inspection object and a temperature sensor. The controller is configured to control the heater based on a temperature detected by the temperature sensor.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: September 19, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Jun Fujihara
  • Patent number: 11664253
    Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a housing configured to house a substrate, and a plasma supplier configured to supply plasma on an upper face of the substrate. The apparatus further includes a support configured to support the substrate and a ring surrounding an end portion of the substrate, the ring including a member having a lower face on which a mark to be photographed is provided. The apparatus further includes equipment configured to photograph the mark or receive an image of the mark through a wiring that includes a first end portion able to be disposed in a vicinity of the mark and a second end portion different from the first end portion.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: May 30, 2023
    Assignee: Kioxia Corporation
    Inventor: Kazuya Yoshimori
  • Patent number: 11604451
    Abstract: A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. The area comprises a plurality of pixels, and the original set of exposure information comprises dosages for the plurality of pixels in the area. A backscatter is calculated for a sub area of the area based on the original set of exposure information. A dosage for at least one pixel in a plurality of pixels in the sub area is increased, in a location where the backscatter of the sub area is below a pre-determined threshold, thereby increasing the backscatter of the sub area. A modified set of exposure information is output, including the increased dosage of the at least one pixel in the sub area.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: March 14, 2023
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, Abhishek Shendre, William E. Guthrie, Ryan Pearman
  • Patent number: 11592802
    Abstract: A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. A backscatter is calculated for the area of the pattern based on the exposure information. An artificial background dose is determined for the area. The artificial background dose comprises additional exposure information and is combined with the original set of exposure information creating a modified set of exposure information. A system for exposing a pattern in an area on a surface using a charged particle beam lithography is also disclosed.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: February 28, 2023
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, William E. Guthrie, Ryan Pearman
  • Patent number: 11587807
    Abstract: An annealing apparatus includes a heater plate and a cooler plate disposed in a chamber, a delivering robot, a sensor and circuitry. The delivering robot is configured to deliver a wafer between the heater plate and the cooler plate in the chamber. The sensor is located on the delivering robot and configured to output a first signal in response to a motion of the delivering robot. The circuitry is coupled to the sensor and configured to detect whether an abnormality of the delivering robot occurs according to the first signal.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chang Huang, Yu-Chi Tsai
  • Patent number: 11574932
    Abstract: With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. Due to the increase in the numbers of gate lines and signal lines, it is difficult to mount an IC chip having a driver circuit for driving the gate and signal lines by bonding or the like, which causes an increase in manufacturing costs. A pixel portion and a driver circuit for driving the pixel portion are formed over one substrate. At least a part of the driver circuit is formed using an inverted staggered thin film transistor in which an oxide semiconductor is used. The driver circuit as well as the pixel portion is provided over the same substrate, whereby manufacturing costs are reduced.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: February 7, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Atsushi Umezaki
  • Patent number: 11557500
    Abstract: Embodiments of the present disclosure provide a heated support pedestal including a body comprising a ceramic material, a support arm extending radially outward from a periphery of the body that is coupled to a shaft, and a vacuum conduit disposed within the shaft and through the body to connect with a surface of the body.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: January 17, 2023
    Assignee: Applied Materials, Inc.
    Inventor: Vijay D. Parkhe
  • Patent number: 11521972
    Abstract: A semiconductor device is provided. The semiconductor device can include a bottom substrate, a device plane over the bottom substrate, a dielectric layer over the device plane, localized substrates over the dielectric layer, and semiconductor devices over the localized substrates. The localized substrates can be separated from each other along a top surface of the bottom substrate. A method of microfabrication is provided. The method can include forming a target layer over a bottom substrate where the target layer includes one or more localized regions that include one or more semiconductor materials. The method can also include performing a thermal process to change crystal structures of the one or more localized regions of the target layer. The method can further include forming semiconductor devices over the localized regions of the target layer.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: December 6, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Patent number: 11508573
    Abstract: In a variety of processes for forming electronic devices that use spin-on dielectric materials, properties of the spin-on dielectric materials can be enhanced by curing these materials using plasma doping. For example, hardness and Young's modulus can be increased for the cured material. Other properties may be enhanced. The plasma doping to cure the spin-on dielectric materials uses a mechanism that is a combination of plasma ion implant and high energy radiation associated with the species ionized. In addition, physical properties of the spin-on dielectric materials can be modified along a length of the spin-on dielectric materials by selection of an implant energy and dopant dose for the particular dopant used, corresponding to a selection variation with respect to length.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: November 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Santanu Sarkar, Jay Steven Brown, Shu Qin, Yongjun Jeff Hu, Farrell Martin Good
  • Patent number: 11478874
    Abstract: In a method of processing a substrate, in a second step, only some of a plurality of altered portions are exposed from an opening portion of a mask, and the remaining portions are not exposed. In this case, at the time of etching in a third step, an etching rate may be made different between the altered portions exposed from the opening portion of the mask and the altered portions which are not exposed. Accordingly, it becomes easier to obtain a desired processed shape by adjusting the altered portions exposed from the opening portion of the mask and the altered portions which are not exposed.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: October 25, 2022
    Assignee: TDK CORPORATION
    Inventor: Akifumi Kamijima
  • Patent number: 11469260
    Abstract: The present disclosure provides a display substrate, a method for preparing the same, and a display device including the display substrate. The method includes: forming a conductive layer; forming a first photoresist pattern and a second photoresist pattern on the conductive layer, in which the adhesion between the first photoresist pattern and the conductive layer is less than the adhesion between the second photoresist pattern and the conductive layer; and etching the conductive layer by using the first photoresist pattern and the second photoresist pattern as masks to form a first conductive pattern and a second conductive pattern, respectively, in which a line width difference between the first conductive pattern and the first photoresist pattern is greater than a line width difference between the second conductive pattern and the second photoresist pattern.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: October 11, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., Beijing BOE Technology Development Co., Ltd.
    Inventors: Ning Liu, Bin Zhou, Jun Liu, Yang Zhang, Tongshang Su, Haitao Wang
  • Patent number: 11448613
    Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: September 20, 2022
    Assignee: LIFE TECHNOLOGIES CORPORATION
    Inventors: Jonathan M. Rothberg, Wolfgang Hinz, John F. Davidson, Antoine M. van Oijen, John Leamon, Martin Huber, Mark James Milgrew, James Bustillo
  • Patent number: 11417754
    Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: August 16, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
  • Patent number: 11376553
    Abstract: A superhydrophobic polypropylene porous film, including a polypropylene porous film substrate, titanium dioxide layers and a surface modifier layer, is disclosed. The titanium dioxide layers are deposited on the surface of the polypropylene porous film substrate by atomic deposition technology; a surface modifier is coated on the titanium dioxide layers; hydrophobic bonds are formed between the titanium dioxide layers and the surface modifier layer; the superhydrophobic polypropylene porous film has a water contact angle greater than 150 degrees, a rolling angle less than 10 degrees, an aperture of 0.1-0.4 ?m, a porosity of 50%-80%, a tensile strength of 30-50 MPa, and an elongation at break of 10%-30%.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: July 5, 2022
    Assignee: Tianjin University of Science and Technology
    Inventors: Na Tang, Yangyang Song, Lei Zhang, Xingxing Shi, Songbo Wang, Penggao Cheng, Wei Du, Jianping Zhang
  • Patent number: 11302278
    Abstract: A display device capable of performing image processing is provided. A memory node is provided in each pixel included in the display device. An intended correction data is held in the memory node. The correction data is calculated by an external device and written into each pixel. The correction data is added to image data by capacitive coupling, and the resulting data is supplied to a display element. Thus, the display element can display a corrected image. The correction enables image upconversion, for example.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: April 12, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Susumu Kawashima, Koji Kusunoki, Kazunori Watanabe, Kouhei Toyotaka, Naoto Kusumoto, Shunpei Yamazaki
  • Patent number: 11302585
    Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: April 12, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Chul Sun, Myeong-Cheol Kim, Kyoung-Sub Shin
  • Patent number: 11280026
    Abstract: A semiconductor wafer made of single-crystal silicon has an oxygen concentration (new ASTM) of not less than 4.9×1017 atoms/cm3 and not more than 6.5×107 atoms/cm3 and a nitrogen concentration (new ASTM) of not less than 8×1012 atoms/cm3 and not more than 5×1013 atoms/cm3, wherein a frontside of the semiconductor wafer is covered with an epitaxial layer made of silicon, wherein the semiconductor wafer comprises BMDs of octahedral shape whose mean size is 13 to 35 nm, and whose mean density is not less than 3×108 cm?3 and not more than 4×109 cm?3, as determined by IR tomography.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: March 22, 2022
    Assignee: SILTRONIC AG
    Inventors: Timo Mueller, Andreas Sattler, Robert Kretschmer, Gudrun Kissinger, Dawid Kot
  • Patent number: 11264280
    Abstract: A method for manufacturing a semiconductor device includes a step of preparing a semiconductor wafer source which includes a first main surface on one side, a second main surface on the other side and a side wall connecting the first main surface and the second main surface, an element forming step of setting a plurality of element forming regions on the first main surface of the semiconductor wafer source, and forming a semiconductor element at each of the plurality of element forming regions, and a wafer source separating step of cutting the semiconductor wafer source from a thickness direction intermediate portion along a horizontal direction parallel to the first main surface, and separating the semiconductor wafer source into an element formation wafer and an element non-formation wafer after the element forming step.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: March 1, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Masatoshi Aketa, Kazunori Fuji
  • Patent number: 11189519
    Abstract: A process for forming a predetermined separation zone inside a donor substrate, in particular, to be used in a process of transferring a layer onto a carrier substrate comprises an implantation step that is carried out such that the implantation dose in a zone of the edge of the donor substrate is lower than the implantation dose in a central zone of the donor substrate to limit the formation of particles during thermal annealing. The present disclosure also relates to a donor substrate for a process of transferring a thin layer onto a carrier substrate produced by means of the process described above. The present disclosure also relates to a device for limiting an implantation region to a zone of the edge of a donor substrate.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: November 30, 2021
    Assignees: Soitec, Commissariat a L'Energie Atomique Et Aux Energies Alternatives
    Inventors: Séverin Rouchier, Frédéric Mazen
  • Patent number: 11164761
    Abstract: After treatment of a preceding lot is completed, warm up treatment is started. In the warm up treatment, an in-chamber structure such as a susceptor is kept at a constant heat-retaining temperature by light irradiation from a halogen lamp. When a signal to pay out a lot is received while the warm up treatment is performed, the treatment proceeds to conditioning treatment. In the conditioning treatment, the in-chamber structure like the susceptor and so on is temperature-controlled to a stable temperature by repeatedly performing light irradiation on a dummy wafer held on the susceptor, the light irradiation being similar to that performed on a semiconductor wafer included in a lot to be treated. Performing the conditioning treatment after the warm up treatment is performed enables the in-chamber structure to be temperature-controlled to the stable temperature in a short time.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: November 2, 2021
    Assignee: SCREEN Holdings Co., Ltd.
    Inventor: Yoshio Ito
  • Patent number: 11145505
    Abstract: There is provided a technique that includes: (a) loading a substrate into a process container; (b) heating the substrate by supplying a first gas, which is heated when passing through a first heater installed at a first gas supply line, to the substrate via a gas supplier; (c) supplying a second gas, which flows through a second gas supply line different from the first gas supply line, to the substrate mounted on a substrate mounting table in the process container, via the gas supplier; and (d) lowering a temperature of the gas supplier by supplying a third gas, which has a temperature lower than that of the first gas, to the gas supplier between (b) and (c).
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: October 12, 2021
    Assignee: Kokusai Electric Corporation
    Inventors: Takashi Yahata, Naofumi Ohashi, Ryuji Yamamoto
  • Patent number: 11139359
    Abstract: A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: October 5, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
  • Patent number: 11111597
    Abstract: A method for growing a single crystal silicon ingot by the continuous Czochralski method is disclosed. The melt depth and thermal conditions are constant during growth because the silicon melt is continuously replenished as it is consumed, and the crucible location is fixed. The critical v/G is determined by the hot zone configuration, and the continuous replenishment of silicon to the melt during growth enables growth of the ingot at a constant pull rate consistent with the critical v/G during growth of a substantial portion of the main body of the ingot. The continuous replenishment of silicon is accompanied by periodic or continuous nitrogen addition to the melt to result in a nitrogen doped ingot.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: September 7, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Carissima Marie Hudson, Jae-Woo Ryu
  • Patent number: 11107704
    Abstract: A substrate processing system includes a processing chamber that includes a substrate support positioned therein. The substrate processing system includes a valve system fluidly coupled to the processing chamber and configured to control flow of gas into the processing chamber. The valve system includes a primary flow line and a first gas source flow line fluidly coupled to the primary flow line through a first gas source valve. The valve system includes a second gas source flow line fluidly coupled to the primary flow line through a second gas source valve. The first gas source valve and the second gas source valve are positioned in series within the primary flow line.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: August 31, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tejas Ulavi, Thuy Britcher, Amit Kumar Bansal
  • Patent number: 11107840
    Abstract: An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: August 31, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake
  • Patent number: 11065805
    Abstract: A warpage reduction device the present disclosure includes a jig having a warped shape capable of distributing stress of a workpiece, a light source heating the workpiece so as to be flat, a pressurizer applying pressure to the heated workpiece to be pressed against the jig so as to be deformed, a cooler cooling the deformed workpiece, and a controller controlling operations of the light source, the pressurizer, and the cooler.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 20, 2021
    Assignee: EO TECHNICS CO., LTD.
    Inventors: Tai O. Chung, Dae Ho Jung, In Su Kim, Gi Hong Seo
  • Patent number: 11031263
    Abstract: A laser stripping mass-transfer device includes a microdevice laser stripping transfer module, an auxiliary conveyor module, a transition conveyor module, a transfer conveyor module, a substrate carrier module, a microdevice filling module, a curing module, an encapsulation module and a substrate transportation module. The microdevice laser stripping transfer module is configured to implement detection and stripping of the microdevices. The auxiliary conveyor module is configured to adhere the stripped microdevices. The transition conveyor module is configured to pick up and transfer the microdevices to the transfer conveyor module. The transfer conveyor module is configured to pick up and transfer the microdevices to the substrate carrier module. The substrate carrier module is configured to feed the microdevices into the microdevice filling module, the curing module, the encapsulation module, and the substrate transportation module for filling, curing, encapsulating, loading and unloading.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 8, 2021
    Assignee: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Jiankui Chen, Yiwei Jin, Zhouping Yin, Yongan Huang
  • Patent number: 11022763
    Abstract: An optical module in which an optical element is housed in a housing includes: an optical window member through which input light to the optical element or output light from the optical element passes and which hermetically seals inside of the housing; and a holding member that holds the optical window member. The optical window member is fixed to the housing by the holding member. A difference between linear expansion coefficients of the holding member and the optical window member is smaller than a difference between linear expansion coefficients of the housing and the optical window member. A position where the optical window member is attached on the holding member protrudes to an optical element side from a position where the holding member itself is fixed.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: June 1, 2021
    Assignee: Sumitomo Osaka Cement Co., Ltd.
    Inventors: Tokutaka Hara, Kei Katou
  • Patent number: 11024524
    Abstract: Dummy running is carried out which performs preheating treatment using halogen lamps and flash heating treatment using flash lamps on a dummy wafer to control the temperature of in-chamber structures including a susceptor and the like. In this process, a preheating counter or a flash heating counter is incremented each time the preheating treatment or the flash heating treatment is performed. An alarm is issued, if the preheating counter or the flash heating counter that is a wear-and-tear value of the dummy wafer is not less than a predetermined threshold value. This allows an operator of a heat treatment apparatus to recognize that the deterioration of the dummy wafer reaches a limit value, thereby preventing the erroneous treatment of a dummy wafer suffering advanced deterioration.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: June 1, 2021
    Assignee: SCREEN HOLDINGS CO., LTD.
    Inventors: Tomohiro Ueno, Kazuhiko Fuse, Mao Omori
  • Patent number: 11018229
    Abstract: A method of forming a semiconductor structure includes forming a first material over a base material by vapor phase epitaxy. The first material has a crystalline portion and an amorphous portion. The amorphous portion of the first material is removed by abrasive planarization. At least a second material is formed by vapor phase epitaxy over the crystalline portion of first material. The second material has a crystalline portion and an amorphous portion. The amorphous portion of the second material is removed by abrasive planarization. A semiconductor structure formed by such a method includes the substrate, the first material, the second material, and optionally, an oxide material between the first material and the second material. The substrate, the first material, and the second material define a continuous crystalline structure. Semiconductor structures, memory devices, and systems are also disclosed.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael Mutch, Manuj Nahar
  • Patent number: 10981322
    Abstract: A process for 3D printing a material by successively solidifying layers of the material to form a cross section of an object. The process includes providing a layer of the material, preheating the material to a preheating temperature, below the temperature at which the material is solidified, and solidifying a layer of the material by electromagnetic radiation or particle radiation. In the solidification step, during a predetermined period of time starting with the beginning of the solidification step, the heat introduced per unit area is reduced over time and can be described by a function which decreases monotonously depending on the time.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: April 20, 2021
    Assignee: EOS GmbH Electro Optical Systems
    Inventor: Stefan Paternoster
  • Patent number: 10956368
    Abstract: The invention concerns a method of generating a digital signature of a geometric design represented by a geometric design file, the method involving generating, by a data processing device, the digital signature based on a single axis projection of the geometric design.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: March 23, 2021
    Assignee: Xyalis
    Inventors: Farid Benzakour, Philippe Morey-Chaisemartin, Frederic Brault, Eric Beisser
  • Patent number: 10937978
    Abstract: A perovskite thin film and method of forming a perovskite thin film are provided. The perovskite thin film includes a substrate, a hole blocking/electron transport layer, and a sintered perovskite layer. The method of forming the perovskite solar cell includes depositing a perovskite layer onto a substrate and sintering the perovskite layer with intense pulsed light.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: March 2, 2021
    Assignee: UNIVERSITY OF LOUISVILLE RESEARCH FOUNDATION, INC.
    Inventors: Thad Druffel, Brandon Lavery
  • Patent number: 10916433
    Abstract: Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10° and about 50°.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 9, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: He Ren, Maximillian Clemons, Mei-Yee Shek, Minrui Yu, Bencherki Mebarki, Mehul B. Naik, Chentsau Ying, Srinivas D. Nemani
  • Patent number: 10886132
    Abstract: A semiconductor wafer serving as a treatment target has a stack structure in which a high-dielectric-constant gate insulating film is formed on a silicon base material with an interface layer film of silicon dioxide sandwiched therebetween, and a metal gate electrode containing fluorine is further formed thereon. A heat treatment apparatus radiates flash light from a flash lamp to the semiconductor wafer in an atmosphere containing hydrogen to carry out heating treatment for an extremely short period of time of 100 milliseconds or less. As a result, diffusion of nitrogen contained in the metal gate electrode is inhibited, at the same time, only the fluorine is diffused from the high-dielectric-constant gate insulating film to an interface between the interface layer film and the silicon base material to reduce an interface state, and reliability of the gate stack structure can be improved.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: January 5, 2021
    Assignee: SCREEN HOLDINGS CO., LTD.
    Inventor: Takayuki Aoyama
  • Patent number: 10879068
    Abstract: A device and a method for forming the device is contemplated. The device and method include patterning a hardmask formed over a substrate. The hardmask is modified by raising an annealing temperature of the hardmask from a first annealing temperature to a second annealing temperature using ion implantation. The hardmask is annealed with a laser beam using a process temperature between the first annealing temperature and the second annealing temperature.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: December 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yongan Xu, Yann Mignot, John C. Arnold, Oleg Gluschenkov
  • Patent number: 10872767
    Abstract: A laser annealing apparatus, a fabrication method of a polysilicon thin film, and a fabrication method of a thin film transistor are provided. The laser annealing apparatus includes: a laser generator, an optical system and an annealing chamber. The laser generator is configured to emit a laser beam, and the laser beam is guided to the annealing chamber via the optical system. The optical system includes a beam splitter, the beam splitter decomposes the laser beam into a first beam and a second beam, an energy density of the first beam is greater than an energy density of the second beam, and the first beam and the second beam are guided into the annealing chamber for laser annealing.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: December 22, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECETRONICS CO., LTD.
    Inventor: Jingshuai Wang
  • Patent number: 10818524
    Abstract: An expanding method includes a plate cooling step of cooing a plate of a cooling/heating unit, which includes the plate for contact with a workpiece and a Peltier element for cooling or heating the plate, a workpiece cooling step of bringing the plate into contact with the workpiece through the expansion sheet to cool the workpiece, after the plate cooling step is performed, an expanding step of expanding the expansion sheet, after the workpiece cooling step is performed, a plate heating step of heating the plate, after the expanding step is performed, and a workpiece heating step of bringing the plate into contact with the workpiece through the expansion sheet to heat the workpiece, after the plate heating step is performed.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: October 27, 2020
    Assignee: DISCO CORPORATION
    Inventor: Shinichi Fujisawa
  • Patent number: 10795219
    Abstract: The present disclosure discloses a substrate, a display panel and a display device. The substrate includes a substrate body, a fan-out layer including a plurality of traces, the plurality of traces being arranged at intervals, and a transparent conductive layer defined as a different layer from the fan-out layer. The fan-out layer is located between the substrate body and the transparent conductive layer, the transparent conductive layer includes a plurality of pattern groups, which are arranged at intervals, the pattern groups and the traces are alternately defined, the pattern group includes a plurality of conductive patterns, which are arranged at intervals.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: October 6, 2020
    Assignee: HKC Corporation Limited
    Inventor: Huailiang He
  • Patent number: 10763127
    Abstract: A heat treatment method for a semiconductor wafer includes: heat treatment in a heat treatment furnace of single wafer processing type having a susceptor capable of mounting a semiconductor wafer, the heat treatment being performed on a semiconductor wafer mounted on the susceptor disposed in the heat treatment furnace; and pre-heating to hold the temperature in the heat treatment furnace at a prescribed temperature lower than the temperature of the heat treatment for a prescribed period before the heat treatment, holding the semiconductor wafer separated from the susceptor during the pre-heating. This heat treatment method for a semiconductor wafer makes it possible to reduce the slip of a semiconductor wafer without largely lowering the productivity even in a high-temperature heat treatment.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: September 1, 2020
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Taishi Wakabayashi, Miho Niitani, Kenji Meguro
  • Patent number: 10748764
    Abstract: A method for manufacturing a semiconductor device includes epitaxially growing a carrier-transport layer of a first conductivity type on a substrate of silicon carbide; irradiating the carrier-transport layer with a first light having a wavelength equal to or less than an absorption-edge wavelength of silicon carbide at a temperature of less than 400 degrees Celsius so as to expand a stacking fault originating from a basal plane dislocation which are propagated from the substrate to the carrier-transport layer; heating the carrier-transport layer in which the stacking fault has expanded so as to shrink the stacking fault, at a shrinking temperature of 400 degrees Celsius or more and 1000 degrees Celsius or less; and forming a carrier-injection region of a second conductivity type on the carrier-transport layer, the carrier-injection region injects carriers into the carrier-transport layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 18, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akira Saito, Kei Nakajima
  • Patent number: 10734530
    Abstract: An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: August 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto
  • Patent number: 10714334
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Huang-Yi Huang, Chun-chieh Wang, Yu-Ting Lin, Min-Hsiu Hung
  • Patent number: 10676826
    Abstract: Methods of forming 2D metal chalcogenide films using laser-assisted atomic layer deposition are disclosed. A direct-growth method includes: adhering a layer of metal-bearing molecules to the surface of a heated substrate; then reacting the layer of metal-bearing molecules with a chalcogenide-bearing radicalized precursor gas delivered using a plasma to form an amorphous 2D film of the metal chalcogenide; then laser annealing the amorphous 2D film to form a crystalline 2D film of the metal chalcogenide, which can have the form MX or MX2, where M is a metal and X is the chalcogenide. An indirect growth method that includes forming an MO3 film is also disclosed.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 9, 2020
    Assignee: Veeco Instruments Inc.
    Inventor: Ganesh Sundaram