Miscellaneous Patents (Class 438/800)
  • Patent number: 10636627
    Abstract: A substrate processing apparatus includes: a substrate holder which holds a plurality of substrates; a processing vessel including an inner tube and an outer tube disposed outside the inner tube; a gas supply part which supplies a process gas in parallel to target surfaces of the substrates; an exhaust part which exhausts the process gas from the processing vessel through a gas outlet; an exhaust port formed in the inner tube; and a rectifying plate installed in an outer wall of the inner tube or an inner wall of the outer tube between the exhaust port and the gas outlet in a circumferential direction of the processing vessel. The rectifying plate is installed to extend upward from a position below a lower end of the substrate holder to a location corresponding at least to a lower end of the exhaust port.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: April 28, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hirofumi Kaneko, Tomoyuki Nagata
  • Patent number: 10574468
    Abstract: The present invention discloses a chaos nanonet device including a nanonet material having metallic and semiconductive properties dispersed on a substrate and an electrode array composed of a plurality of electrodes that has a selected domain size on the nanonet material, and a PUF security apparatus based on the chaos nanonet device.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: February 25, 2020
    Assignees: UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY, RESEARCH BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Sun Kook Kim, Ik Joon Chang, Joon Sung Yang
  • Patent number: 10522319
    Abstract: An electron beam apparatus which can stably achieve high spatial resolution also during low acceleration observation using CeB6 for the CFE electron source is provided. In an electron beam apparatus having a CFE electron source, the emitter of the electron beam of the CFE electron source is Ce hexaboride or a hexaboride of a lanthanoid metal heavier than Ce, the hexaboride emits the electron beam from the {310} plane, and the number of the atoms of the lanthanoid metal on the {310} plane is larger than the number of boron molecules comprising six boron atoms on the {310} plane.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: December 31, 2019
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Keigo Kasuya, Noriaki Arai, Toshiaki Kusunoki, Takashi Ohshima, Tomihiro Hashizume, Yusuke Sakai
  • Patent number: 10374215
    Abstract: Iron nanoparticles that are useful for constructing electrodes for lithium ion batteries and a method of making said particles is disclosed herein. The nanoparticles may include magnetite. The electrode may be constructed by centrifuging the nanoparticles to a current collector, such as a disc of copper, without the use of an extrinsic binder. The solvothermal method of making nanoparticles decreases the time of the procedure from about 24 hours to about 75 minutes. The method of making electrode decreases the complexity and number of steps compared to the conventional procedure to prepare an electrode, and eliminates the use of additives (binder and current enhancer) and toxic NMP solvents in the electrode preparation process.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: August 6, 2019
    Assignee: WAYNE STATE UNIVERSITY
    Inventors: Da Deng, Jian Zhu, K. Y. Simon Ng
  • Patent number: 10224394
    Abstract: According to an embodiment of a semiconductor substrate, the semiconductor substrate includes a superjunction structure in a device region of a semiconductor layer and an alignment mark in a kerf region of the semiconductor layer. The superjunction structure includes first regions and second regions of opposite conductivity types, the first and the second regions alternating along at least one horizontal direction. The alignment mark includes a vertical step formed by an alignment structure projecting or recessed from a main surface of the semiconductor layer. The alignment structure is of a material of the first regions of the superjunction structure.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: March 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Christian Fachmann, Daniel Tutuc, Andreas Voerckel
  • Patent number: 10225888
    Abstract: A defrost window includes a transparent substrate, a carbon nanotube film, a first electrode, a second electrode and a protective layer. The transparent substrate has a top surface. The carbon nanotube film is disposed on the top surface of the transparent substrate. The first electrode and the second electrode electrically connect to the carbon nanotube film and space from each other. The protective layer covers the carbon nanotube film.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: March 5, 2019
    Assignee: Beijing FUNATE Innovation Technology Co., LTD.
    Inventors: Chen Feng, Yu-Quan Wang, Li Qian
  • Patent number: 10192761
    Abstract: A pick arm for a pick and place apparatus for semiconductor devices, the pick arm comprising first and second ends along a longitudinal axis of the pick arm, and a pick tool located at the first end of the pick arm for picking up semiconductor devices. The pick arm further comprises a winged part extending in a direction transverse to the longitudinal axis between the first and second ends of the pick arm, wherein the winged part comprising a sloping surface. The sloping surface is inclined between a top portion and a bottom portion of the winged part such that the sloping surface is nearer to the longitudinal axis at the top portion than at the bottom portion of the winged part.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: January 29, 2019
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Kin Fung Yu, Yu Xing Cao, Wing Chiu Lai, Kai Siu Lam, Gary Peter Widdowson, Ying Zhuo Liu
  • Patent number: 10068718
    Abstract: Embodiments of the present disclosure are directed towards Faradaic energy storage device structures and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a substrate having a plurality of holes disposed in a surface of the substrate, the plurality of holes being configured in an array of multiple rows and an active material for Faradaic energy storage disposed in the plurality of holes to substantially fill the plurality of holes. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Priyanka Pande, Cary L. Pint, Yang Liu, Wei Jin, Charles Holzwarth, Donald Gardner
  • Patent number: 10002908
    Abstract: Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 19, 2018
    Assignee: Nantero, Inc.
    Inventor: Claude L. Bertin
  • Patent number: 9954231
    Abstract: The present disclosure relates to a positive electrode for a lithium-air battery and a method for preparing the same, and the positive electrode for a lithium-air battery according to the present disclosure has advantages in that it improves electrical conductivity and mechanical strength of an electrode, and increases loading amounts.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: April 24, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Yu Mi Kim, Minchul Jang, Byoungkuk Son, Gi Su Park
  • Patent number: 9936575
    Abstract: A resin multilayer substrate includes a first resin layer, a conductive pattern that covers a portion of the first resin layer, a conductive via connected to the conductive pattern, and a second resin layer that is overlaid on the first resin layer. The second resin layer includes an opening through which the conductive pattern is partially exposed. As seen in plan view, the opening includes an inner peripheral edge including a first portion that is spaced from the conductive via by a first distance, and a second portion that is spaced from the conductive via by a second distance. The conductive pattern has a length that starts from the inner peripheral edge of the opening to outside and extends under the second resin layer. The length of the conductive pattern at the second portion is greater than the length of the conductive pattern at the first portion.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: April 3, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yoshihito Otsubo
  • Patent number: 9899338
    Abstract: Methods for enhancing mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks are provided. After forming interconnect structures in a dielectric material layer, a pore filling material is introduced into pores of a portion of the dielectric material layer that is located in a crack stop region present around a periphery of a chip region. By filling the pores of the portion of the dielectric material layer located in the crack stop region, the mechanical strength of the dielectric material layer is selectively enhanced in the crack stop region.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Patent number: 9847300
    Abstract: Product management and/or prompt defect analysis of a semiconductor device may be carried out without reducing the throughput in assembly and testing. Unique identification information is attached to a plurality of substrates (lead frames) used in manufacturing a semiconductor device (QFP) and to a transport unit for transporting a plurality of substrates, respectively. Identification information (rack ID) of the transport unit and identification information (substrate ID) of the substrate stored into the transport unit are associated with each other. The substrate is taken out from the transport unit set to a loader unit of each manufacturing apparatus and supplied to a processing unit, of the apparatus and in storing the substrate, the processing of which is complete, into a transport unit of an unloader unit of the apparatus, an association between identification information of the transport unit and the identification information of the substrate is checked.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: December 19, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Nobutaka Sakai, Mamoru Otake, Koji Saito, Tomishi Takahashi
  • Patent number: 9824982
    Abstract: Methods for enhancing mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks are provided. After forming interconnect structures in a dielectric material layer, a pore filling material is introduced into pores of a portion of the dielectric material layer that is located in a crack stop region present around a periphery of a chip region. By filling the pores of the portion of the dielectric material layer located in the crack stop region, the mechanical strength of the dielectric material layer is selectively enhanced in the crack stop region.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: November 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Patent number: 9799506
    Abstract: A breakdown voltage measuring method includes the steps of measuring a breakdown voltage of a semiconductor element in a state where a surface of the semiconductor element formed in a semiconductor substrate is covered with a high boiling point fluorine fluid having a boiling point of 90° C. or higher, and cleaning the semiconductor substrate, including the semiconductor element for which the breakdown voltage is measured, with a low boiling point fluorine inert fluid having a boiling point of 80° C. or lower. Accordingly, a breakdown voltage measuring method capable of suppressing generation of an electric discharge during the measurement of the breakdown voltage and suppressing a residue of a foreign object on the cleaned semiconductor substrate, and a semiconductor device to which the breakdown voltage measuring method is implemented are provided.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: October 24, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Mitsuhiko Sakai
  • Patent number: 9475973
    Abstract: In the method of embodiments of the invention, the metal seeded carbon allotropes are reacted in solution forming zero valent metallic nanowires at the seeded sites. A polymeric passivating reagent, which selects for anisotropic growth is also used in the reaction to facilitate nanowire formation. The resulting structure resembles a porcupine, where carbon allotropes have metallic wires of nanometer dimensions that emanate from the seed sites on the carbon allotrope. These sites are populated by nanowires having approximately the same diameter as the starting nanoparticle diameter.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: October 25, 2016
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Robin E. Southward, Donavon Mark Delozier, Kent A. Watson, Joseph G. Smith, Jr., Sayata Ghose, John W. Connell
  • Patent number: 9398714
    Abstract: A wearable electronics assembly includes one or more electronic modules coupled to a wearable electronics fabric. Each of the one or more electronic modules includes one or more metal foils, each metal foil electrically coupled at one end to an electrical connection point of the electrical module and at another end to an electrically conductive wire. The electrically conductive wire is stitched to the metal foil and to a fabric onto which the electronic module is attached. The electronic module can include one or more electronic components coupled to a printed circuit board. The metal foils can be formed from interconnects on the printed circuit board or the metal foils can be separate elements coupled to the printed circuit board.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 19, 2016
    Assignee: Flextronics AP, LLC
    Inventors: Weifeng Liu, Zhen Feng, Anwar Mohammed
  • Patent number: 9362390
    Abstract: Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: June 7, 2016
    Assignee: Nantero, Inc.
    Inventor: Claude L. Bertin
  • Patent number: 9296614
    Abstract: An assembly, such as for growing carbon nanotubes, includes a substrate including SiO2 and has a thickness of less than 500 ?m. Further, the substrate is bendable and has a surface with non-flat or non-polished texture such that surface comprises raised and recessed features for receiving a coating, such as a catalyst. Carbon nanotubes may be anchored to and grow from the recessed features of the substrate.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: March 29, 2016
    Assignee: CORNING INCORPORATED
    Inventors: Archit Lal, Windsor Pipes Thomas, III
  • Patent number: 9299478
    Abstract: A carbon nanotube composite film includes a treated patterned carbon nanotube film and a polymer film having the treated patterned carbon nanotube film located therein. The treated patterned carbon nanotube film includes carbon nanotube linear units spaced from each other and carbon nanotube groups spaced from each other and combined with the carbon nanotube linear units. A method for making the carbon nanotube composite film is also disclosed.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: March 29, 2016
    Assignee: Beijing FUNATE Innovation Technology Co., LTD.
    Inventors: Chen Feng, Yu-Quan Wang, Li Qian
  • Patent number: 9145303
    Abstract: Apparatus configured to produce polysilicon by chemical vapor deposition, including a reactor vessel having an inner surface defining at least a portion of a chamber, the inner surface having a lining of quartz ceramic. The apparatus also includes a silicon substrate disposed within the chamber of the reactor vessel, the silicon substrate having a deposition surface upon which polysilicon is deposited. Methods of producing polysilicon using such apparatus, as well as methods for applying the quartz ceramic lining onto a reactor vessel, are also provided.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: September 29, 2015
    Assignee: ECOLIVE TECHNOLOGIES LTD.
    Inventors: Anatoly Alexandrovich Goncharov, Yury Dmitrievich Kalashnikov
  • Patent number: 9103029
    Abstract: A processing apparatus for processing objects, includes: a processing container structure having a bottom opening and including a processing container having a processing space for housing the objects, the container having a nozzle housing area on one side of the processing space and a slit-like exhaust port on the opposite side of the processing space from the nozzle housing area; a lid for closing the bottom opening of the processing container structure; a support structure for supporting the objects and which can be inserted into and withdrawn from the processing container structure; a gas introduction means including a gas nozzle housed in the nozzle housing area; an exhaust means including a plurality of exhaust systems for exhausting the atmosphere in the processing container structure; a heating means for heating the objects; and a control means for controlling the gas introduction means, the exhaust means and the heating means.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: August 11, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Yu Wamura, Yuichiro Morozumi, Izumi Sato, Shinji Asari
  • Patent number: 9090477
    Abstract: A method of manufacturing silica nanowires includes: providing an object to be processed into a reaction chamber; supplying a precursor having a heteroleptic structure, which has a chemical formula SiA2B2 (A and B are different functional groups), into the reaction chamber; supplying an oxygen-containing gas that preferentially reacts with any one of the functional groups A and B of the precursor; and growing an intermediate on a surface of the object to be processed due to a reaction between the precursor and the oxygen-containing gas.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: July 28, 2015
    Assignee: SNU R&DB FOUNDATION
    Inventors: Sanghyun Park, Jaeyeong Heo, Hyeong Joon Kim
  • Publication number: 20150067428
    Abstract: A system-on-chip comprises an internal module having diagnostic functionality, and a physical communications port coupled to a first data path and arranged to support, when in use, a datagram-based communications interface for communicating with an external data communications unit. Debug logic circuitry is operably coupled to a debug interface and the internal module, the debug interface being arranged to support communication of debug data relating to the internal module. The system-on-chip also comprises configurable hardware logic circuitry configured as datagram processing logic and is arranged to support use of a datagram to communicate with the debug logic. The datagram processing logic is operably coupled to the first data path and a second data path, the second data path being operably coupled to the debug interface.
    Type: Application
    Filed: May 2, 2012
    Publication date: March 5, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Stefan Singer, Joseph Circello, Heinz Wrobel
  • Patent number: 8965550
    Abstract: A wafer fabrication outcome, such as wafer yield or wafer lifetime, is predicted by excluding uncontrollable but measurable internal/external noises of a DOE system, and by rendering relations between wafer design variables and wafer outcome outputs to be more causal, as well as the relations between variances for each of the wafer design variables and the wafer outcome outputs. With the aid of a wafer fabrication outcome predicting model formed by the more causal relations, precision of predicting wafer outcomes can be raised, and performance of wafer fabrication can be thus raised as a result.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Ming Hou, Ji-Fu Kung
  • Patent number: 8907299
    Abstract: The present disclosure provides a method of manufacturing film member for laser-driven ion acceleration, a film target, and a method of manufacturing the same, so that only the film member exists at a laser focusing point on the film target, allowing repeated ion acceleration from the film member by focusing high power laser beams thereon. The method includes preparing a film member solution containing a film material to be used for laser-driven ion acceleration; forming a film member on a base substrate by using the film member solution; and separating the film member from the base substrate by dipping the base substrate having the film member formed thereon into a film parting solvent.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: December 9, 2014
    Assignee: Gwangju Institute of Science and Technology
    Inventors: Il Woo Choi, Jongmin Lee, Chang-Lyoul Lee, KeeHwan Nam, I Jong Kim, Ki Hong Pae
  • Patent number: 8851008
    Abstract: A substrate treating apparatus includes a plurality of substrate treatment lines arranged vertically. Each substrate treatment line has a plurality of main transport mechanisms arranged horizontally, and a plurality of treating units provided for each main transport mechanism for treating substrates. A series of treatments is carried out for the substrates, with each main transport mechanism transporting the substrates to the treating units associated therewith, and transferring the substrates to the other main transport mechanism horizontally adjacent thereto. The substrate treating apparatus realizes increased processing capabilities by treating the substrates in parallel through the substrate treatment lines.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: October 7, 2014
    Assignee: Sokudo Co., Ltd.
    Inventors: Yoshiteru Fukutomi, Tsuyoshi Mitsuhashi, Hiroyuki Ogura, Kenya Morinishi, Yasuo Kawamatsu, Hiromichi Nagashima
  • Publication number: 20140273539
    Abstract: Embodiments of methods for treating dielectric layers are provided herein. In some embodiments, a method of treating a dielectric layer disposed on a substrate supported in a process chamber includes: (a) exposing the dielectric layer to an active radical species formed in a plasma for a first period of time; (b) heating the dielectric layer to a peak temperature of about 900 degrees Celsius to about 1200 degrees Celsius; and (c) maintaining the peak temperature for a second period of time of about 1 second to about 20 seconds.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 18, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: HENG PAN, MATTHEW SCOTT ROGERS, CHRISTOPHER S. OLSEN
  • Patent number: 8802480
    Abstract: The invention relates to a method for producing a monograin membrane and a monograin membrane produced according to said method. The invention further relates to the production of a solar cell from such a monograin membrane as well as a produced solar cell. The monograin membranes produced according to the invention can also be used for other applications, e.g. for converting electric energy into radiation energy or in detectors for detecting radiation. The aim of the invention is to improve the production of monograin membranes and solar cells. Said aim is achieved by first preparing a horizontally oriented layer made of a binder that is not yet cured or cross-linked such that the binder is liquid or at least viscous. Grains are partially introduced into the layer through a surface of the layer in such a way that only a portion of each grain is immersed in the layer and a zone of the grain remains above the surface of the layer.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: August 12, 2014
    Assignee: crystalsol GmbH
    Inventor: Dieter Meissner
  • Publication number: 20140217556
    Abstract: Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 7, 2014
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Chee Siong Peh, Chiew Hai NG, David G. McIntyre
  • Publication number: 20140159040
    Abstract: The present disclosure relates to secure devices having a physical unclonable function and methods of manufacturing such secure devices. One device includes at least one graphene layer representing a physical unclonable function and a measurement circuit for measuring at least one property of the at least one graphene layer. Another device includes at least a first graphene layer and a second graphene layer representing a physical unclonable function, where one of the graphene layers has been subjected to a variability enhancement such that a measurable property is different for each of the layers. A method includes providing a substrate for a secure device and providing at least one graphene layer on the substrate, the at least one graphene layer representing a physical unclonable function. The providing of the at least one graphene layer includes applying at least one variability enhancement to the at least one graphene layer.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Applicant: International Business Machines Corporation
    Inventors: CHRISTOS D. DIMITRAKOPOULOS, Dirk Pfeiffer, Joshua T. Smith
  • Publication number: 20140162458
    Abstract: A method of forming a pattern on a substrate includes forming openings in material of a substrate. The openings are widened to join with immediately adjacent of the openings to form spaced pillars comprising the material after the widening. Other embodiments are disclosed.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Ranjan Khurana, Anton J. DeVillers, Kevin J. Torek, Shane J. Trapp, Scott L. Light, James M. Buntin
  • Publication number: 20140162464
    Abstract: A method of manufacturing a secure device having a physical unclonable function includes providing a first graphene layer, providing a second graphene layer and applying a variability enhancement to at least one of the first graphene layer and the second graphene layer such that a measurable property is different for each of the first graphene layer and the second graphene layer. The physical unclonable function is represented by at least the first and second graphene layers. In still another embodiment, a method of manufacturing a secure device having a physical unclonable function includes providing an integrated circuit comprising at least one graphene layer and including a measurement circuit in the integrated circuit that is configured to measure at least one property of the at least one graphene layer for authenticating the secure device. The at least one graphene layer represents the physical unclonable function.
    Type: Application
    Filed: August 19, 2013
    Publication date: June 12, 2014
    Applicant: International Business Machines Corporation
    Inventors: Christos D. Dimitrakopoulos, Dirk Pfeiffer, Joshua T. Smith
  • Patent number: 8728831
    Abstract: A system and method for reducing warpage of a semiconductor wafer. The system includes a device for securing the semiconductor wafer in a heating area. The device includes a holding mechanism for securing an edge of the semiconductor wafer. The device further includes a pressure reducing device that reduces the pressure underneath the semiconductor device, which further secures the semiconductor device in the heating area. The heating area includes a plurality of heating and cooling zones in which the semiconductor wafer is subjected to various temperatures.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics Pte. Ltd.
    Inventors: Kah Wee Gan, Yonggang Jin
  • Publication number: 20140137271
    Abstract: A memory device includes but is not limited to a substrate, a non-volatile memory array integrated on the substrate, and data security logic integrated with the non-volatile memory array on the substrate. The data security logic is operable to perform at least one data security function associated with the non-volatile memory array.
    Type: Application
    Filed: January 10, 2013
    Publication date: May 15, 2014
    Applicant: Elwha LLC, a limited liability corporation of the State of Delaware
    Inventor: Elwha LLC, a limited liability corporation of the State of Delaware
  • Publication number: 20140134852
    Abstract: A method for forming a porous low-k film having an Si—O structure includes irradiating infrared light upon a film including a material having an Si—O structure, and irradiating ultraviolet light upon the film including the material having the Si—O structure such that a porous low-k film including the material having the Si—O structure is formed. The irradiating of the infrared light has an irradiation period of infrared light which is set shorter than an irradiation period of ultraviolet light in the irradiating of the ultraviolet light.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 15, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yusaku IZAWA, Masaki NARUSHIMA
  • Patent number: 8720049
    Abstract: Disclosed herein is a method for fabricating a printed circuit board, including: stacking a second insulating layer including a reinforcement on an outer surface of a first insulating layer having a post via formed thereon; polishing an upper surface of the second insulating layer to expose an upper side of the post via; stacking a film member on the second insulating layer to cover the post via and compress the second insulating layer; polishing an upper surface of the film member to expose an upper side of the post via; and forming a circuit layer connected to the post via on the upper surface of the film member.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: May 13, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Tae Kyun Bae, Chang Gun Oh, Ho Sik Park
  • Patent number: 8663532
    Abstract: A reticle comprising isolated pillars is configured for use in imprint lithography. In some embodiments, on a first substrate a pattern of pillars pitch-multiplied in two dimensions is formed in an imprint reticle. The imprint reticle is brought in contact with a transfer layer overlying a series of mask layers, which in turn overlie a second substrate. The pattern in the reticle is transferred to the transfer layer, forming an imprinted pattern. The imprinted pattern is transferred to the second substrate to form densely-spaced holes in the substrate. In other embodiments, a reticle is patterned by e-beam lithography and spacer formations. The resultant pattern of closely-spaced pillars is used to form containers in an active integrated circuit substrate.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: March 4, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 8657961
    Abstract: Embodiments of the invention generally provide methods for cleaning a UV processing chamber. In one embodiment, the method includes flowing an oxygen-containing gas through a plurality of passages formed in a UV transparent gas distribution showerhead and into a processing region located between the UV transparent gas distribution showerhead and a substrate support disposed within the thermal processing chamber, exposing the oxygen-containing gas to UV radiation under a pressure scheme comprising a low pressure stage and a high pressure stage to generate reactive oxygen radicals, and removing unwanted residues or deposition build-up from exposed surfaces of chamber components presented in the thermal processing chamber using the reactive oxygen radicals.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: February 25, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Bo Xie, Alexandros T. Demos, Scott A. Hendrickson, Sanjeev Baluja, Juan Carlos Rocha-Alvarez
  • Patent number: 8658532
    Abstract: Various lithography methods are disclosed. An exemplary lithography method includes forming a first patterned silicon-containing organic polymer layer over a substrate by removing a first patterned resist layer, wherein the first patterned silicon-containing organic polymer layer includes a first opening having a first dimension and a second opening having the first dimension, the first opening and the second opening exposing the substrate; forming a second patterned silicon-containing organic polymer layer over the substrate by removing a second patterned resist layer, wherein a portion of the patterned second silicon-containing organic polymer layer combines with a portion of the first patterned silicon-containing organic polymer layer to reduce the first dimension of the second opening to a second dimension; and etching the substrate exposed by the first opening having the first dimension and the second opening having the second dimension.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ching-Yu Chang
  • Publication number: 20140017903
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a first surface. In the method, a stress is applied to the semiconductor substrate to change inter-atomic spacing at the first surface of the semiconductor substrate to a stressed inter-atomic spacing. Then, the semiconductor substrate is processed. Thereafter, the stress is released and the first surface of the processed semiconductor substrate retains the stressed inter-atomic spacing.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 16, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Abner Bello, Abhijeet Paul
  • Patent number: 8627243
    Abstract: Methods for optimizing conductor patterns for conductors formed by ECP and CMP processes. A method includes receiving layout data for an IC design where electrochemical plating (ECP) processes form patterned conductors in at least one metal layer over a semiconductor wafer; determining from the received layout data a global effects factor corresponding to a global pattern density; determining layout effects factors for unit grid areas corresponding to the pattern density of the at least one metal layer within the unit grid areas, determining local effects factors for each unit grid area; using a computing device, executing an ECP simulator using at least one of the global effects factor and the local effects factors, and using the layout effects factor; outputting an predicted post-ECP hump data map from the ECP simulator; and if indicated by a threshold comparison, modifying the layout data.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Lin, Yu-Wei Chou, Wen-Cheng Huang, Cheng-I Huang, Ching-Hua Hsieh
  • Patent number: 8592107
    Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: November 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guo-Tsai Huang, Fu-Jye Liang, Li-Jui Chen, Chih-Ming Ke
  • Patent number: 8524611
    Abstract: In manufacturing a semiconductor device, a first chamber is provided. An opening couples the first chamber to a first environment through which at least one substrate can pass. A first seal environmentally isolates the first chamber from the first environment. A process chamber is coupled to the first chamber. Another seal environmental isolates the first and the process chambers. The substrate is placed within the first chamber, and the first chamber and the outside environment are isolated. The second opening is opened, and the substrate moves into the semiconductor process chamber. The first chamber is again environmentally isolated from the second volume. A semiconductor processing step is performed on the substrate within the processing chamber. While the substrate is processed, the substrate is rotated and translated through the processing chamber.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: September 3, 2013
    Assignee: Solyndra LLC
    Inventor: Ratson Morad
  • Publication number: 20130217152
    Abstract: Die may be thinned using a thinning and/or a polishing process. Such thinned die may be flexible and may change operational characteristics when flexed. The flexible die may be applied to a mechanical carrier (e.g., a PCB) of a card or device. Detection circuitry may also be provided on the PCB and may be used to detect changed operational characteristics. Such detection circuitry may cause a reaction to the changed characteristics by controlling other components on the card or device based upon the flex-induced changed characteristics. The thinned die may be stacked, interconnected, and encapsulated between sheets of laminate material to form a flexible card or device.
    Type: Application
    Filed: February 19, 2013
    Publication date: August 22, 2013
    Inventors: Jeffrey D. Mullen, Norman E. O'Shea
  • Patent number: 8480319
    Abstract: A process block is formed by arranging a heating-process related block on the side of a carrier block, a group of liquid-process related unit blocks, and a heating block on the side of an interface block, in this order from the side of the carrier block to the side of the interface block. The group of liquid-process related unit blocks is composed of: a group of unit blocks for coating films that is formed by stacking upward a unit block for an antireflection film, a unit block for a resist film, and a unit block for an upper layer film, in this order; and unit blocks for developing that are stacked on one another in the up and down direction with respect to the group of unit blocks for coating films. Liquid process modules of each of the liquid-process related unit blocks are arranged on the right and left sides of a transfer path for a substrate.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: July 9, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Shinichi Hayashi, Yuichi Douki, Akira Miyata, Yuuichi Yamamoto, Kousuke Yoshihara, Nobuaki Matsuoka, Suguru Enokida
  • Patent number: 8475666
    Abstract: A toughening agent composition for increasing the hydrophobicity of an organosilicate glass dielectric film when applied to said film. It includes a component capable of alkylating or arylating silanol moieties of the organosilicate glass dielectric film via silylation, and an activating agent selected from the group consisting of an amine, an onium compound and an alkali metal hydroxide.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: July 2, 2013
    Assignee: Honeywell International Inc.
    Inventors: Teresa A. Ramos, Robert R. Roth, Anil S. Bhanap, Paul G. Apen, Denis H. Endisch, Brian J. Daniels, Ananth Naman, Nancy Iwamoto, Roger Y. Leung
  • Patent number: 8470721
    Abstract: The electronic properties (such as electron mobility, resistivity, etc.) of an electronic material in operation in an electronic device or electronic circuit can be modified/enhanced when subjected to dynamic or stationary magnetic fields with current flowing through the electronic material. Heating or cooling of the electronic material further enhances the electronic properties.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: June 25, 2013
    Inventor: Brian I. Ashkenazi
  • Patent number: 8455375
    Abstract: To provide a glass plate for display panels which has a low 82O3 content and a low compaction and which can be used as a glass substrate for large TFT panels. A glass plate for display panels, which comprises, as a glass matrix composition as represented by mass % based on oxide: SiO2 50.0 to 73.0, Al2O3 6.0 to 20.0, B2O3 0 to 2.0, MgO 4.2 to 9.0, CaO 0 to 6.0, SrO 0 to 2.0, BaO 0 to 2.0, MgO+CaO+SrO+BaO 6.5 to 11.3, Li2O 0 to 2.0, Na2O 2.0 to 18.0, K2O 0 to 13.0, and Li2O+Na2O+K2O 8.0 to 18.0, and has a heat shrinkage (C) of at most 20 ppm.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: June 4, 2013
    Assignee: Asahi Glass Company, Limited
    Inventors: Manabu Nishizawa, Yuya Shimada, Yuichi Kuroki, Kei Maeda
  • Patent number: 8449805
    Abstract: A reticle comprising isolated pillars is configured for use in imprint lithography. In some embodiments, on a first substrate a pattern of pillars pitch-multiplied in two dimensions is formed in an imprint reticle. The imprint reticle is brought in contact with a transfer layer overlying a series of mask layers, which in turn overlie a second substrate. The pattern in the reticle is transferred to the transfer layer, forming an imprinted pattern. The imprinted pattern is transferred to the second substrate to form densely-spaced holes in the substrate. In other embodiments, a reticle is patterned by e-beam lithography and spacer formations. The resultant pattern of closely-spaced pillars is used to form containers in an active integrated circuit substrate.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: May 28, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu