Abstract: Die may be thinned using a thinning and/or a polishing process. Such thinned die may be flexible and may change operational characteristics when flexed. The flexible die may be applied to a mechanical carrier (e.g., a PCB) of a card or device. Detection circuitry may also be provided on the PCB and may be used to detect changed operational characteristics. Such detection circuitry may cause a reaction to the changed characteristics by controlling other components on the card or device based upon the flex-induced changed characteristics. The thinned die may be stacked, interconnected, and encapsulated between sheets of laminate material to form a flexible card or device.

Abstract: A process block is formed by arranging a heating-process related block on the side of a carrier block, a group of liquid-process related unit blocks, and a heating block on the side of an interface block, in this order from the side of the carrier block to the side of the interface block. The group of liquid-process related unit blocks is composed of: a group of unit blocks for coating films that is formed by stacking upward a unit block for an antireflection film, a unit block for a resist film, and a unit block for an upper layer film, in this order; and unit blocks for developing that are stacked on one another in the up and down direction with respect to the group of unit blocks for coating films. Liquid process modules of each of the liquid-process related unit blocks are arranged on the right and left sides of a transfer path for a substrate.

Abstract: A toughening agent composition for increasing the hydrophobicity of an organosilicate glass dielectric film when applied to said film. It includes a component capable of alkylating or arylating silanol moieties of the organosilicate glass dielectric film via silylation, and an activating agent selected from the group consisting of an amine, an onium compound and an alkali metal hydroxide.

Abstract: The electronic properties (such as electron mobility, resistivity, etc.) of an electronic material in operation in an electronic device or electronic circuit can be modified/enhanced when subjected to dynamic or stationary magnetic fields with current flowing through the electronic material. Heating or cooling of the electronic material further enhances the electronic properties.

Abstract: To provide a glass plate for display panels which has a low 82O3 content and a low compaction and which can be used as a glass substrate for large TFT panels. A glass plate for display panels, which comprises, as a glass matrix composition as represented by mass % based on oxide: SiO2 50.0 to 73.0, Al2O3 6.0 to 20.0, B2O3 0 to 2.0, MgO 4.2 to 9.0, CaO 0 to 6.0, SrO 0 to 2.0, BaO 0 to 2.0, MgO+CaO+SrO+BaO 6.5 to 11.3, Li2O 0 to 2.0, Na2O 2.0 to 18.0, K2O 0 to 13.0, and Li2O+Na2O+K2O 8.0 to 18.0, and has a heat shrinkage (C) of at most 20 ppm.

Abstract: A reticle comprising isolated pillars is configured for use in imprint lithography. In some embodiments, on a first substrate a pattern of pillars pitch-multiplied in two dimensions is formed in an imprint reticle. The imprint reticle is brought in contact with a transfer layer overlying a series of mask layers, which in turn overlie a second substrate. The pattern in the reticle is transferred to the transfer layer, forming an imprinted pattern. The imprinted pattern is transferred to the second substrate to form densely-spaced holes in the substrate. In other embodiments, a reticle is patterned by e-beam lithography and spacer formations. The resultant pattern of closely-spaced pillars is used to form containers in an active integrated circuit substrate.

Abstract: In a control device of a plasma processing system, a communication unit is configured to receive processing information related to a carrier of a next processing lot. A determination unit is configured to determine whether the processing information received by the communication unit has pre-treatment information related to one of the plasma processing devices. When it is determined that the processing information has the pre-treatment information by the determination unit, a generation unit is configured to generate an object for declaring execution of the pre-treatment for the carrier of a next processing lot if a desired condition of transferring of the carrier is satisfied. In addition, if the object is generated by the generation unit, a process executing control unit is configured to start the pre-treatment for the target object in the carrier of a next processing lot without any notification that the carrier reaches a destination plasma processing device.

Abstract: The invention is related to a semiconductor chip, at-least also accomplished in a semiconductor installation, containing at-least also a long, relatively narrow semiconductor substrate transfer/processing tunnel-arrangement, wherein during its operation at-least also the taking place of successive semiconductor processings of the successive, typically uninterruptedly displacing semiconductor substrate-sections there through and whereby in a device behind its exit by means of dividing these successive semiconductor substrate-sections the accomplishing thereof.

Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.

Abstract: A chip identification for organic laminate packaging and methods of manufacture is provided. The method includes forming a material on a wafer which comprises a plurality of chips. The method further includes modifying the material to provide a unique identification for each of the plurality of chips on the wafer. The organic laminate structure includes a chip with a device and a material placed on the chip which is modified to have a unique identification mark for the chip.

Abstract: Disclosed is a substrate processing apparatus capable of decreasing the frequency of shutdown of the apparatus due to lack of processing liquid in a processing liquid supply unit, as well as efficiently using the processing liquid to improve a yield ratio. The substrate processing apparatus includes a plurality of liquid processing units to conduct liquid processing of substrates a substrate carrying unit to carry the substrates in and out of the liquid processing units, a processing liquid supply unit to supply the liquid processing units with processing liquid, and a level gauge to detect an amount of the processing liquid remaining in the processing liquid reservoir of the processing liquid supply unit. The carry of the substrates in the liquid processing units is suspended when the level gauge detects that the amount of the processing liquid remaining in the processing liquid reservoir is below a predetermined threshold.

Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.

Abstract: The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing means. The writing means is preferably direct-write lithography. To maintain manufacturing throughput, the total amount of custom data should be less than 1% of the total amount of content data.

Abstract: In accordance with some embodiments described herein, a method for transferring a substrate is provided. The method includes loading one or more substrates into a respective mobile chamber of one or more mobile chambers. The mobile chambers are movable on a first rail positioned adjacent to two or more process modules. Each mobile chamber is configured to maintain a specified gas condition. The respective mobile chamber is moved along the first rail. The respective mobile chamber is docked to a respective process module of the two or more process modules. At least one of the one or more substrates is conveyed from the respective mobile chamber to the respective process module.

Abstract: Method of manufacturing gradient composite material comprises steps of providing plural surface modified inorganic nanoparticles with functional groups or oligomers with functional groups; transferring the surface modified inorganic nanoparticles or oligomers with functional groups into an organic matrix to form a mixture; performing a photo polymerization step or a thermo-polymerization step for polymerizing and generating a gradient distribution of the surface modified inorganic nanoparticles or oligomers with functional groups in the mixture; and curing the mixture to solidify the organic matrix and form a structure with gradient composite, wherein the organic matrix is transferred into an organic polymer after curing.

Abstract: A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to form at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed.

Abstract: A metal recovery apparatus recovers metal components from an exhaust gas exhausted from a processing chamber in which a thin film is formed on the surface of a target substrate by using a source gas formed of an organic metal compound serving as a source, and scrubs the exhaust gas. The metal recovery apparatus 66 includes a trap unit having an adsorption member for attaching thereon metal components included in the source gas by heating the exhaust gas and thus thermally decomposing an unreacted source gas included in the exhaust gas; and the scrubbing unit including a catalyzer for oxidizing and thus scrubbing harmful gas components included in the exhaust gas that has flowed through the trap unit.

Abstract: Disclosed is an coating/developing apparatus and method thereof in which the processing time is shortened and the foot prints is reduced by shortening the travel distance of a wafer transfer arm. The coating/developing apparatus of the present disclosure includes, inter alia, liquid processing part (COT) that processes the substrate using a liquid, a cooling processing part (CA) provided to correspond to the liquid processing part (COT) and perform the cooling process for the substrate, a liquid processing unit (COTU) provided to correspond to the cooling processing part (CA) and equipped with a heating processing part (HP) that performs a heating processing for the substrate. The cooling processing part (CA) transfers the substrate to/from the liquid processing part (COT) and the heating processing part (HP).

Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.

Abstract: An apparatus includes a substrate with a planar surface, a multilayer of semiconductor layers located on the planar surface, a plurality of electrodes located over the multilayer, and a dielectric layer located between the electrodes and the multilayer. The multilayer includes a 2D quantum well. A first set of the electrodes is located to substantially surround a lateral area of the 2D quantum well. A second set of the electrodes is controllable to vary a lateral width of a non-depleted channel between the substantially surrounded lateral area of the 2D quantum well and another area of the 2D quantum well. A third set of the electrodes is controllable to vary an area of a non-depleted portion of the lateral area.

Abstract: A method for delineating a metallization pattern in a layer of sputtered aluminum or sputtered copper using a broad spectrum high intensity light source. The metal is deposited on a polymeric substrate by sputtering, so that it has a porous nanostructure. An opaque mask that is a positive representation of the desired metallization pattern is then situated over the metallization layer, exposing those portions of the metallization layer intended to be removed. The masked metallization layer is then exposed to a rapid burst of high intensity visible light from an arc source sufficient to cause complete removal of the exposed portions of the metallization layer, exposing the underlying substrate and creating the delineated pattern.

Abstract: A dry-in/dry-out system is disclosed for wafer electroless plating. The system includes an upper zone for wafer ingress/egress and drying operations. Proximity heads are provided in the upper zone to perform the drying operations. The system also includes a lower zone for electroless plating operations. The lower zone includes an electroless plating apparatus that implements a wafer submersion by fluid upwelling method. The upper and lower zones of the system are enclosed by a dual-walled chamber, wherein the inner wall is a chemically inert plastic and the outer wall is a structural metal. The system interfaces with a fluid handling system which provides the necessary chemistry supply and control for the system. The system is ambient controlled. Also, the system interfaces with an ambient controlled managed transfer module (MTM).

Abstract: Provided is a functional member 4 comprising a fluororesin containing a carbon material 2 and having surface cleanliness, wherein the content of the carbon material 2 in a surface portion 4a of the functional member 4 is significantly less than the content of the carbon material 2 in an inner portion 4b of the functional member 4.

Abstract: Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.

Abstract: A pixel array in an image sensor includes multiple pixels. The pixel array includes vertical shift registers for shifting charge out of the pixel array. The vertical shift registers can be interspersed between the pixels, such as in an interline image sensor, or the photosensitive areas in the pixels can operate as vertical shift registers. The pixels are divided into blocks of pixels. One or more electrodes are disposed over each pixel. Conductive strips are disposed over the electrodes. Contacts are used to connect selected electrodes to respective conductive strips. The contacts in at least one block of pixels are positioned according to one contact pattern while the contacts in one or more other blocks are positioned according to a different contact pattern. The different contact patterns reduce or eliminate visible patterns in the contact locations.

Abstract: A semiconductor processing tool heats wafers using radiant heat and resistive heat in chamber or in a load lock where pressure changes. The wafers are heated in greater part with a resistive heat source until a transition temperature or pressure is reached, then they are heated in greater part with a radiant heat source. Throughput improves for the tool because of the wafers can reach a high temperature uniformly in seconds.

Abstract: A method of fabricating a metamaterial is provided, comprising providing a sample of engineered microstructured material that is transparent to electromagnetic radiation and comprises one or more voids, passing through the voids a high pressure fluid comprising a functional material carried in a carrier fluid, and causing the functional material to deposit or otherwise integrate into the engineered microstructured material to form the metamaterial. Many microstructured materials and functional materials can be used, together with various techniques for controlling the location of the integration of the functional material within the microstructured material, so that a wide range of different metamaterials can be produced.

Abstract: In accordance with some embodiments described herein, a method for transferring a substrate to two or more process modules is provided, comprising loading at least one substrate into one or more mobile transverse chambers, the mobile transverse chambers being carried on a rail positioned adjacent to the two or more process modules, and wherein each mobile transverse chamber is configured to maintain a specified gas condition during conveyance of the substrate. One or more drive systems are actuated to propel at least one of the one or more mobile transverse chambers along the rail. The at least one mobile transfer chamber docks to at least one of the process modules, and the substrate is conveyed from the mobile transverse chamber to the at least one process modules.

Abstract: A system and method are provided for fabricating a low electric resistance ohmic contact, or interface, between a Carbon Nanotube (CNT) and a desired node on a substrate. In one embodiment, the CNT is a Multiwalled, or Multiwall, Carbon Nanotube (MWCNT), and the interface provides a low electric resistance ohmic contact between all conduction shells, or at least a majority of conduction shells, of the MWCNT and the desired node on the substrate. In one embodiment, a Focused Electron Beam Chemical Vapor Deposition (FEB-CVD) process is used to deposit an interface material near an exposed end of the MWCNT in such a manner that surface diffusion of precursor molecules used in the FEB-CVD process induces lateral spread of the deposited interface material into the exposed end of the MWCNT, thereby providing a contact to all conduction shells, or at least a majority of the conduction shells, of the MWCNT.

Abstract: An integrated processing tool is described comprising a full-wafer processing module and a combinatorial processing module. Chemicals for use in the combinatorial processing module are fed from a delivery system including a set of first manifolds. An output of each first manifold is coupled to at least one mixing vessel. An output of each mixing vessel feeds more than one of a set of second manifolds. An output of each set of second manifolds feeds one of multiple site-isolated reactors of the combinatorial processing module.

Abstract: A pixel array in an image sensor includes multiple pixels. The pixel array includes vertical shift registers for shifting charge out of the pixel array. The vertical shift registers can be interspersed between the pixels, such as in an interline image sensor, or the photosensitive areas in the pixels can operate as vertical shift registers. The pixels are divided into blocks of pixels. One or more electrodes are disposed over each pixel. Conductive strips are disposed over the electrodes. Contacts are used to connect selected electrodes to respective conductive strips. The contacts in at least one block of pixels are positioned according to one contact pattern while the contacts in one or more other blocks are positioned according to a different contact pattern. The different contact patterns reduce or eliminate visible patterns in the contact locations.

Abstract: A method of forming a pattern (700) on a work piece (1260) includes placing a pattern mask (1210) over the work piece, placing an aperture (100, 500, 600, 1220) over the pattern mask, and placing the work piece in a beam of electromagnetic radiation (1240). The aperture includes three adjacent sections. A first section (310) has a first side (311), a second side (312), and a first length (313). A second section (320) has a third side (321) adjacent to the second side, a fourth side (322), a second length (323), and a first width (324). A third section (330) has a fifth side (331) adjacent to the fourth side, a sixth side (332), and a third length (333). The first and third lengths are substantially equal. The first and third sections are complementary shapes, as defined herein.

Abstract: An electronic device (100) is presented, being configured for example as a vertical field effect transistor. The device comprises an electrically-conductive perforated patterned structure (102) which is enclosed between a dielectric layer (105) and an active element (106) of the electronic device (100). The electrically-conductive perforated patterned structure (102) comprises a geometrical pattern defining an array of spaced-apart perforation regions (108) surrounded by continuous electrically conductive regions (110). The pattern is such as to allow the active element (106) of the electronic device (100) to be in direct contact with said dielectric layer (105) aligned with the perforation regions (108). A material composition of the device (100) and features of said geometrical pattern are selected to provide a desired electrical conductance of the electrically-conductive perforated patterned structure (102) and a desired profile of a charge carriers' injection barrier along said structure (102).

Abstract: A coating and developing apparatus has: a treatment block-including a water repellent module performing water repellent treatment on a substrate, a coating module, and a developing module; a substrate side-surface portion water repellent module for performing water repellent treatment on a side surface of a substrate; and a control unit controlling operations of the modules to execute steps of performing water repellent treatment at least on a side surface portion of a substrate and performing a first resist coating on an entire surface of the substrate; performing a first development after a first liquid-immersion exposure is performed; performing a second resist coating on the entire surface, and performing a second development after a second liquid-immersion exposure is performed, and further to execute a step of performing water repellent treatment on the side surface portion of the substrate after the first development and before the second exposure is performed.

Abstract: Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BiFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.

Abstract: The invention relates to a method for picking up semiconductor chips from a wafer table and, optionally, their mounting on a substrate by means of a pick-and-place system. The position and orientation of the semiconductor chip to be mounted next are determined by means of a first camera and made available in the form of positional data relating to a first system of coordinates. The position and orientation of the substrate place on which the semiconductor chip will be mounted are determined by means of a second camera and made available in the form of positional data relating to a second system of coordinates. The conversion of coordinates of the first or second system of coordinates into coordinates of motion of the pick-and-place system occurs by means of two fixed mapping functions and two changeable correction vectors. The correction vectors are readjusted on the occurrence of a predetermined event.

Abstract: A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-charge-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port and a treatment section. The static-charge-eliminated semiconductor substrate is accommodated in the container positioned to the load port. Thus, it is possible to decrease foreign materials adhering to the semiconductor substrate and errors in handling the semiconductor substrate.

Abstract: A method of transferring one or more substrates between process modules or load lock stations while minimizing heat loss is provided. In some embodiments the method comprising the steps of: identifying a destination location D1 for a substrate S1 present at an initial processing location P1; if the destination location D1 is occupied with a substrate S2, maintaining the substrate S1 at the initial processing location P1; and if the destination location D1 is available, transferring the substrate S1 to the destination location D1. In accordance with additional embodiments, the method is carried out on a system for processing substrates which includes two or more process modules, a substrate handling robot, a load lock chamber, and a transverse substrate handler. The transverse substrate handler includes mobile transverse chambers configured to convey substrates to process modules, wherein each mobile transverse chamber is configured to maintain a specified gas condition during the conveyance of the substrates.

Abstract: Methods synthesizing nanowires in solution at low temperatures (e.g., about 400° C. or lower) are provided. In the present methods, the nanowires are synthesized by exposing nanowire precursors to metal nanocrystals in a nanowire growth solution comprising a solvent. The metal nanocrystals serve as seed particles that catalyze the growth of the semiconductor nanowires. The metal nanocrystals may be formed in situ in the growth solution from metal nanocrystal precursors. Alternatively, the nanowires may be pre-formed and added to the growth solution.

Abstract: Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.

Abstract: A hot edge ring with extended lifetime comprises an annular body having a sloped upper surface. The hot edge ring includes a step underlying an outer edge of a semiconductor substrate supported in a plasma processing chamber wherein plasma is used to process the substrate. The step includes a vertical surface which surrounds the outer edge of the substrate and the sloped upper surface extends upwardly and outwardly from the upper periphery of the vertical surface.

Abstract: The present invention provides a method for manufacturing a semiconductor nanowire device in mass production at a low cost without an additional complex nanowire alignment process or SOI substrate by forming a single crystal silicon nanowire with a simple process without forming an ultra fine pattern using an electron beam and transferring the nanowire separated from the substrate to another oxidation layer or insulation substrate. And also, the present invention suggests a method for simply manufacturing a nanowire device transferring the nanowire from a semiconductor substrate formed thereon the nanowire to another substrate formed thereon an insulation layer or the like.

Abstract: A method is for calculating a height of a chuck top. A height of the top surface of the chuck top which corresponds to an arbitrary position specified on the XY coordinate plane by a computer is calculated in each of the four quadrants based on a coordinate transformation formulas. The method includes setting, by using the computer, a conical model in which two adjacent points other than the center point of the chuck top which correspond to the specified coordinates in a predetermined quadrant of the XY coordinate plane are obtained on a circumference having the center point of the chuck top as the origin and specifying an arbitrary point in the predetermined quadrant by using the computer and calculating a height of the arbitrary point of the chuck top based on the conical model, the coordinate transformation formulas and the specified coordinates.

Abstract: A battery can be fabricated from a substrate including silicon. This allows the battery to be produced as an integrated unit. The battery includes an anode formed from an array of spaced elongated structures, such as pillars, which include silicon and which can be fabricated on the substrate. The battery also includes a cathode which can include lithium.

Abstract: A layer of high aspect ratio nanoparticles is disposed on a surface of a substrate under the influence of an electrical field applied on the substrate. To create the electrical field, a voltage is applied between a pair of electrodes arranged near the substrate or on the substrate, and the high aspect ratio nanoparticles disposed on the substrate are at least partially aligned along direction(s) of the applied electrical field. The high aspect ratio nanoparticles are grown from catalyst nanoparticles in an aerosol, and the aerosol is directly used for forming the nanoparticle layer on the substrate at room temperature. The nanoparticles may be carbon nanotubes, in particular single wall carbon nanotubes. The substrate with the layer of aligned high aspect ratio nanoparticles disposed thereon can be used for fabricating nanoelectronic devices.

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

Abstract: A semiconductor processing tool heats wafers using radiant heat and resistive heat in chamber or in a load lock where pressure changes. The wafers are heated in greater part with a resistive heat source until a transition temperature or pressure is reached, then they are heated in greater part with a radiant heat source. Throughput improves for the tool because of the wafers can reach a high temperature uniformly in seconds.

Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.

Abstract: In a patterning process of a semiconductor device having inverted stagger type TFTs, a normal photolithography step using diazo naphthoquinone (DNQ)-Novolac resin based positive photo resist is applied, and a problem of the area dependency of the photo resist pattern side wall taper angle may occur. The problem is critical for the reason of influence on variation of an etching shape in a dry-etching step. The present invention has an object to solve the above problem. In a photolithography step, which is patterning step of a semiconductor device having inverted stagger type TFTs, by adjusting a pre-bake temperature or a PEB (post-exposure-bake) temperature, and positively performing evacuation of solvent in a state of a photo resist film, the volume contraction by evacuation of solvent at the post-bake is reduced, and the problem of the area dependency of the photo resist pattern side wall taper angle is solved, which is deformation due to the volume contraction.