Abstract: A process for preparing smoothened III-N, in particular smoothened III-N substrate or III-N template, wherein III denotes at least one element of group III of the Periodic System, selected from Al, Ga and In, utilizes a smoothening agent comprising cubic boron nitride abrasive particles. The process provides large-sized III-N substrates or III-N templates having diameters of at least 40 mm, at a homogeneity of very low surface roughness over the whole substrate or wafer surface. In a mapping of the wafer surface with a white light interferometer, the standard deviation of the rms-values is 5% or lower, with a very good crystal quality at the surface or in surface-near regions, measurable, e.g., by means of rocking curve mappings and/or micro-Raman mappings.

Abstract: Experiments suggest that the mathematically weakest non-abelian TQFT may be physically the most robust. Such TQFT's—the ?=5/2 FQHE state in particular—have discrete braid group representations, so one cannot build a universal quantum computer from these alone. Time tilted interferometry provides an extension of the computational power (to universal) within the context of topological protection. A known set of universal gates has been realized by topologically protected methods using “time-tilted interferometry” as an adjunct to the more familiar method of braiding quasi-particles. The method is “time-tilted interferometry by quasi-particles.” The system is its use to construct the gates {g1, g2, g3}.

Abstract: A dynamic mask module is disclosed, which comprises a microcomputer system, a mask pattern generator and a light source. The mask pattern generator is disposed over a substrate and electrically connected to the microcomputer system. The microcomputer system transmits an image signal to the mask pattern generator. The light source is disposed over the mask pattern generator to a photo-resist layer on the substrate. The mask pattern generated by the dynamic mask module is a dynamic image and the mask pattern can be changed on anytime. In addition, the manufacturing cost can be and the manufacturing time can be reduced.

Abstract: A semiconductor package, provided with a multilayer interconnect structure, for mounting a semiconductor chip on its top surface, wherein a topmost stacked structure of the multilayer interconnect structure includes a capacitor structure, the capacitor structure having a dielectric layer comprised of a mixed electrodeposited layer of high dielectric constant inorganic filler and insulating resin and including chip connection pads for directly connecting top electrodes and bottom electrodes with electrodes of the semiconductor chip, whereby greater freedom in design of interconnect patterns can be secured, the degree of proximity of the capacitor and semiconductor chip can be greatly improved, and the package can be made smaller and lighter in weight, a method of production of the same, and a semiconductor device using this semiconductor package.

Abstract: The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined.

Abstract: Fluids for use in immersion lithography systems are disclosed. A resistivity-altering substance is introduced into a fluid, making it more conductive. The fluid is then disposed between an immersion head of a projection lens system and a semiconductor wafer during an exposure process. Because the fluid is conductive, electrostatic energy that may develop during the movement of the semiconductor wafer with respect to the projection lens system during the exposure process is discharged through the conductive fluid, preventing damage to an immersion head of the projection lens system, the semiconductor wafer, and sensors of a stage that supports the semiconductor wafer.

Abstract: A method of forming a semiconductor interconnect including, in the order recited: (a) providing a semiconductor wafer; (b) forming bonding pads in a terminal wiring level on the frontside of the wafer; (c) reducing the thickness of the wafer; (d) forming solder bumps on the bonding pads; and (e) dicing the wafer into bumped semiconductor chips.

Abstract: A transfer chamber for a cluster system includes a first body, a second body attached at one side of the first body, and a cover combined with an upper portion of the first body. The transfer chamber further includes a third body at another side of the first body, wherein the third body has the same shape as the second body.

Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five (5) atmospheres to twenty-five (25) atmospheres N2O and a temperature range of 600° C. to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.

Abstract: A gas delivery device useful in material deposition processes executed during semiconductor device fabrication in a reaction chamber, including the gas delivery device of the present invention and a method for carrying out a material deposition process, including introducing process gas into a reaction chamber using the gas delivery device of the present invention. In each embodiment, the gas delivery device of the present invention includes a plurality of active diffusers and a plurality of gas delivery nozzles, which extend into the reaction chamber. Before entering the reaction chamber through one of the plurality of gas delivery nozzles, process gas must first pass through one of the plurality active diffusers. Each of the active diffusers is centrally controllable such that the rate at which process gas flows through each active diffuser is exactly controlled at all times throughout a given deposition process.

Abstract: In a semiconductor integrated circuit device, from a first power source strap supplying a potential to a first standard cell receiving a supply of the potential, the potential is supplied via a first cell power source line having a constant width. The width of the first cell power source line is determined in accordance with power consumed by the first standard cell and with the number of standard cells that can be placed between the first power source strap and a third power source strap.

Abstract: A semiconductor device comprising a vertical stack of layers, comprising: an active layer configured to support a two dimensional carrier gas having an excess of carriers; source and drain contacts provided to said active layer such that a current can flow between said source and drain contacts through said two dimensional carrier gas; a lower conducting region, wherein said lower contact conducting region is a patterned lower conducting region such that said active layer is suspended across gaps in said lower conducting region and said active layer is physically supported by and suspended between parts of said lower conducting region.

Abstract: A surface protective film peeling method for peeling off a surface protective film (11) attached on the surface of a wafer (20) is disclosed. The wafer is supported on a movable table (31) with the surface protective film directed up, and an incision (15) is formed at one end (28) of the surface protective film along the surface of the wafer, the peeling tape is attached on the front surface of the portion in which the incision is formed, at one end of the surface protective film, the movable table is moved in the direction toward the one end from the other end (29) of the wafer, and the surface protective film is thus peeled off from the front surface of the wafer. As a result, the surface protective film can be peeled without causing cuts or cracks, etc. in the wafer. Also, in the case where the movable table is moved while holding the portion in which the incision is formed, the surface protective film can be peeled off without using the peeling tape.

Abstract: A surface treatment method of a compound semiconductor substrate, a fabrication method of a compound semiconductor, a compound semiconductor substrate, and a semiconductor wafer are provided, directed to reducing the impurity concentration at a layer formed on a substrate by reducing the impurity concentration at the surface of the substrate formed of a compound semiconductor. The compound semiconductor substrate surface treatment method includes a substrate preparation step and a first washing step. The substrate preparation step includes the step of preparing a substrate formed of a compound semiconductor containing at least 5 mass % of indium. In the first washing step, the substrate is washed for a washing duration of at least 3 seconds and not more than 60 seconds using washing liquid having a pH of at least ?1 and not more than 3, and an oxidation-reduction potential E (mV) satisfying the relationship of ?0.08333x+0.750?E??0.833x+1.333, where x is the pH value.

Abstract: A method of forming a pattern for a semiconductor device includes forming first pattern data, forming second pattern data, forming third pattern data, forming pattern density measurement data including the first, second, and third pattern data, measuring a pattern density of the pattern density measurement data, adjusting shapes of patterns in the third pattern data based on a comparison of the measured density value and a reference density so as to form fourth pattern data, and forming final pattern data including the first, second, and fourth pattern data.

Abstract: The electronic device includes a plurality of layout regions each including a plurality of patterns defined by a buried structure buried in a substrate. For each of the layout regions, in each of the layout regions, the minimum space between the patterns, and a maximum area percentage allowed for the patterns in the layout region are defined based on a size of the layout region. In larger one of the layout regions, the minimum space between the patterns in the region is set larger.

Abstract: A system for detecting a malfunction of a roughing valve in an ion implantation apparatus, including a valve driving controller, at least one roughing valve having an open-state and a closed-state, at least one solenoid driver electrically connected to the valve driving controller and capable of operating the roughing valve, at least one sensor electrically connected to the valve driving controller, the sensor being capable to determine a state of the roughing valve, a first relay activated by the sensor in response to the state of the roughing valve to transmit a signal, and a main controller electrically connect to the first relay to respond to the transmitted signal.

Abstract: A method for annealing a semiconductor substrate. The method includes turning on at least one heat source, heating a semiconductor substrate in a chamber, turning off the at least one heat source, and cooling the semiconductor substrate in the chamber. The heating a semiconductor substrate includes absorbing an energy from the at least one heat source by the semiconductor substrate. Moreover, the cooling the semiconductor substrate includes flowing a first gas in a vicinity of at least one wall of the chamber, flowing a second gas in a vicinity of the at least one heat source, and flowing a third gas in a vicinity of the semiconductor substrate.

Abstract: Aperture masks and deposition techniques for using aperture masks are described. In addition, techniques for creating aperture masks and other techniques for using the aperture masks are described. The various techniques can be particularly useful in creating circuit elements for electronic displays and low-cost integrated circuits such as radio frequency identification (RFID) circuits. In addition, the techniques can be advantageous in the fabrication of integrated circuits incorporating organic semiconductors, which typically are not compatible with wet processes.

Abstract: A method for using ALD and RVD techniques in semiconductor manufacturing to produce a smooth nanolaminate dielectric film, in particular for filling structures with doped or undoped silica glass, uses dynamic process conditions. A dynamic process using variable substrate (e.g., wafer) temperature, reactor pressure and/or reactant partial pressure, as opposed to static process conditions through various cycles, can be used to minimize film roughness and improve gap fill performance and film properties via the elimination or reduction of seam occurrence. Overall film roughness can be reduced by operating the initial growth cycle under conditions which optimize film smoothness, and then switching to conditions that will enhance conformality, gap fill and film properties for the subsequent process cycles. Film deposition characteristics can be changed by modulating one or more of a number of process parameters including wafer temperature, reactor pressure, reactant partial pressure and combinations of these.

Abstract: A semiconductor device includes alignment marks that are aligned with device features. The semiconductor device includes a device feature, a pair of first alignment marks, a pair of second alignment marks, and a pair of third alignment marks. The first alignment marks are aligned along a first direction with the device feature and adjacent to opposite sides of the device feature. The second alignment marks are aligned along a second direction with the device feature that is substantially perpendicular to the first direction, and adjacent to opposite sides of the device feature. The third alignment marks are aligned with the first alignment marks in the first direction and adjacent to opposite sides of the device feature, wherein the third marks are between the first alignment marks and the device feature, and each of the third marks have a shorter length along the first direction than each of the first alignment marks.

Abstract: A method for fabricating a MEMS device comprises providing a substrate having a back side, a front side opposite to the back side and a periphery portion. A desired microstructure is formed on the back side of the substrate. The substrate is then supported for rotation. A precursor solution is deposited on the front side of the substrate during rotation so that a thin film layer may be formed thereon. During formation of the thin film layer, the substrate is supported and rotated that the microstructure formed on the back side is protected.

Abstract: Nano-scale devices and methods provide reduced feature dimensions of features on the devices. A surface of a device substrate having a pattern of spaced apart first nanowires is consumed, such that a dimension of the first nanowires is reduced. A second nanowire is formed in a trench or gap between adjacent ones of the first nanowires, such that the nano-scale device includes a set of features that includes the first nanowires with the reduced dimension and the second nanowire spaced from the adjacent first nanowires by sub-trenches.

Abstract: A process for producing a nanoelement arrangement and to a nanoelement arrangement. A first nanoelement is at least partially covered with catalyst material for catalyzing the growth of nanoelements. Furthermore, at least one second nanoelement is grown on the catalyst material. Also, a nanoelement arrangement having a first nanoelement on which at least one predetermined region is covered with catalyst material for catalyzing the growth of nanoelements, and at least one second nanoelement grown on the catalyst material.

Abstract: The invention, which relates to a wafer lifting device having a lifting platform arranged under a wafer receptacle, which lifting platform can be moved in the vertical direction and at least three pins which can be moved in through holes in the wafer receptacle. The pins are separately guided in the through holes. A pin is guided and held such that it can be moved longitudinally, and the pin guide is fixedly connected to the wafer receptacle.

Abstract: A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate electrode film provided on the gate insulating film of the N-channel MISFET and composed of a first metal silicide, a second gate electrode film provided on the gate insulating film of the P-channel MISFET and composed of a second metal silicide made of a second metal material different from a first metal material composing the first metal silicide, and a work function of the first gate electrode film being lower than that of the second gate electrode film.

Abstract: A silicon substrate is coated with one or more layers of resist. First and second circuit patterns are exposed in sequence, where the second pattern crosses the first pattern. The patterned resist layers are developed to open holes which extend down to the substrate only where the patterns cross over each other. These holes provide a mask suitable for implanting single phosphorous ions in the substrate, for a solid state quantum computer. Further development of the resist layers provides a mask for the deposition of nanoelectronic circuits, such as single electron transistors, aligned to the phosphorous ions.

Abstract: A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-charge-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port and a treatment section. The static-charge-eliminated semiconductor substrate is accommodated in the container positioned to the load port. Thus, it is possible to decrease foreign materials adhering to the semiconductor substrate and errors in handling the semiconductor substrate.

Abstract: The present invention provides a method for inspecting a connecting surface of a flip chip to solve problems that the grinding, polishing and chemical etching method is used for making a sample. The present invention utilizes ion beam etching technology for making and processing a sample of the flip chip (FC). The ion beam etching technology includes two modes: keeping the energy of ion beam and increasing the etching time; and keeping the etching time and increasing the ion beam energy. The ion beam etching technology can remove a deforming portion between the solder ball and the metal pad, which is connected thereto because of the grinding and polishing. Specially, it is easy to analyse a sample of a scanning electron microscope (SEM) which includes an intermetallic compound formed between the solder ball and the metal pad connected thereto.

Abstract: A method for attaching a workpiece, for example a semiconductor die, to a workpiece holder, for example a lead frame die support, comprises the steps of interposing an uncured adhesive between the semiconductor die and the die support and preheating the adhesive from an ambient temperature to a preheat temperature of between about 150° C. and about 160° C. over a period of about 1.5 seconds. Next, the preheat temperature is maintained for about 1.5 seconds, then the adhesive is further heated to a temperature of between about 190° C. and about 200° C. over a period of about 1.0 second. The inventive method quickly cures the adhesive to secure the die to the support with acceptably low levels of voiding. An apparatus which can be adapted to perform the inventive method is further described.

Abstract: A method for performing immersion lithography on a semiconductor wafer is disclosed. The method includes positioning the semiconductor wafer beneath a lens and applying a fluid between a top surface of the semiconductor wafer and the lens. An additive can be provided to the top surface so that any droplet of the fluid that forms on the top surface of the semiconductor wafer will have a contact angle between about 40° and about 80°.

Abstract: A film surface imprinted with nanometer-sized particles to produce micro- and/or nano-structured electron and hole collecting interfaces, including: at least one substrate; at least one photoabsorbing conjugated polymer (including polybutylthiophene (pbT)) applied on a substrate, nanometer-sized particles including multiwalled carbon nanotubes (MWNT) to produce a charge separation interface; at least one transparent polymerizable layer, wherein the MWNT are embedded in the conjugated polymer to produce mixture and applied on a substrate to form a MWNT bearing surface film layer to form a stamp surface which is imprinted into the surface of the polymerizable film layer to produce micro- and/or nano-structured electron and hole collecting interfaces; polymerizing the polymerizable film layer to form a conformal gap between the MWNT stamp surface and the surface of the polymerizable film layer, and filling the gap with a photoabsorbing material to promote the generation of photoexcited electrons and transport to

Abstract: Semiconductor chip mounting apparatus 90 is provided with semiconductor chip supply unit 10, semiconductor chip carrier unit 20, lead frame carrier unit 30, sensor unit 60 and a control unit 70. Semiconductor chip carrier unit 20 picks up a semiconductor chip 3 from semiconductor chip supply unit 10 and carries the same to mounting position 50 of lead frame 31 and mounts it on mounting position 50. Sensor unit 60 measures first and second positions of semiconductor chip carrier unit 20 before and during mounting operations, respectively. Control unit 70 compares the first position of semiconductor chip carrier unit 20 with the second one of semiconductor chip carrier unit 20 and calculates position deviations. Control unit 70 further provides position adjustment instructions when the position deviations are greater than a predetermined value thereby to improve the throughput and precision of semiconductor chip mounting apparatus 90.

Abstract: A method and apparatus for transporting and dispersing microstructures on a substrate by fluidic self-assembly. The apparatus has an assembly vessel that is tilted and rotated to apply uncaptured microstructures back onto the substrate as the assembly vessel rotates. The assembly vessel has ramp structures that collect the microstructures that have not been captured by the substrate at the lower edge of the assembly vessel, carry the microstructures as the assembly vessel rotates, and release the microstructures back on to the substrate at the upper edge of the assembly vessel. Vibrational energy may also be applied to the assembly vessel to assist in the dispersal and location of the microstructures on the substrate.

Abstract: A method for producing carbon nanotubes, the method comprising: (a) providing a substrate with a top surface, (b) forming an island of catalyst material on the top surface using a tip having a patterning compound thereon, (c) heating the substrate and catalyst island, and (d) contacting the catalyst island with a carbon-containing gas for a period of time sufficient to form the nanotubes on the catalyst island.

Abstract: The conveyance of wafers in bays (equipment groups) of a clean room is performed by RGVs (Rail Guided Vehicles) that linearly travel at high speed on conveying rails laid on the floor of the clean room. A structure is adopted wherein a conveying area, over which the RGV travels, is separated from a human working area by a compartment (partition), and a human is not allowed to enter the conveying area upon operation of a line.

Abstract: A method and apparatus for thermally treating disk-shaped substrates, especially semiconductor wafers, in a rapid heating unit having at least one first radiation source, which is spaced from a given substrate for heating the substrate. The substrate is heated in a heating phase and is cooled in a cooling phase that follows the heating phase. During at least a portion of the cooling phase, the substrate is supported at a distance of from 50 ?m to 1 mm via ultrasonic levitation from a heating/cooling plate. For example by means of an ultrasonic electrode.

Abstract: Method and system for fabricating an electrical interconnect capable of supporting very high current densities (106–1010 Amps/cm2), using an array of one or more carbon nanotubes (CNTs). The CNT array is grown in a selected spaced apart pattern, preferably with multi-wall CNTs, and a selected insulating material, such as SiOw or SiuNv, is deposited using CVD to encapsulate each CNT in the array. An exposed surface of the insulating material is planarized to provide one or more exposed electrical contacts for one or more CNTs.

Abstract: A method of fabricating a nanotube structure which includes providing a substrate, providing a mask region positioned on the substrate, patterning and etching through the mask region to form at least one trench, depositing a conductive material layer within the at least one trench, depositing a solvent based nanoparticle catalyst onto the conductive material layer within the at least one trench, removing the mask region and subsequent layers grown thereon using a lift-off process, and forming at least one nanotube electrically connected to the conductive material layer using chemical vapor deposition with a methane precursor.

Abstract: Chemically assembled electronic nanotechnology (CAEN) provides an alternative to using Complementary Metal Oxide Semiconductor (CMOS) for constructing circuits with feature sizes in the tens of nanometers. A molecular latch and a method using the latch that enables it to act as a state holding device, perform voltage restoration, and to provide I/O isolation is disclosed.

Abstract: A manufacturing technique for a zener diode which includes forming a first semiconductor region in a region such as a well region at a primary face of a semiconductor substrate and then forming a second semiconductor region of opposite conductivity type thereover. The second semiconductor region covers an area greater than the underlying first semiconductor region. The method further calls for forming an insulating film on the primary face of the substrate followed by the forming connection holes in the insulating film to expose an upper part of the second semiconductor region located outside the area covered by the junction affected between the first and second semiconductor regions. This is followed by the formation of a wire at the upper part of the insulating film in which an electrical connection is affected between the wire and the second semiconductor region through the plural connection holes which are distributively arranged.

Abstract: A storage cell that may be a memory cell, and integrated circuit (IC) chip including an array of the memory cells and a method of forming the IC. Each storage cell is formed between a top an bottom electrode. Each cell includes a phase change layer that may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) or GST layer. The cell also includes a stylus with the apex of the stylus contacting the GST layer.

Abstract: The present invention provides a solid state light-emissive display apparatus of high brightness and efficiency, high reliability, and of thin type, and method of manufacturing the same at low cost. Said apparatus has the luminous thin film made up by laminating or mixing crystal fine particle coated with insulator (5) of nm size and fluorescent fine particles (7) of nm size, and the lower electrode and the transparent upper electrode sandwiching said luminous thin film, wherein the electrons injected from said lower electrode are accelerated in the crystal fine particle coated with insulator layer (6) not being scattered by phonons to become high energy ballistic electrons, and form excitons (13) by colliding excitation of fluorescent fine particles. Since said fluorescent fine particles are of nm size, the exciton concentration is high, and luminescence intensity by extinction of excitons is also high.

Abstract: Terminating the ends of passive electronic components entails applying a laser-ablative coating to each of the opposed major surfaces of a substrate. A UV laser beam having a spot size and an energy distribution sufficient to remove the laser-ablative coating from multiple selected regions of the major surfaces is directed for incidence on the substrate. Relative motion between the UV laser beam and substrate effects removal of sufficient amounts of laser-ablative coating to expose the multiple selected regions of the opposed major surfaces. The substrate is then broken into multiple rowbars, each of which includes side margins along which are positioned different spatially aligned pairs of the selected regions of the opposed major surfaces. An electrically conductive material is applied to the side margins to form electrically conductive interconnects between each spatially aligned pair of the selected regions.

Abstract: A method of the production of a nanoparticle dispersed composite material capable of controlling a particle size and a three dimensional arrangement of the nanoparticles is provided. The method of the production of a nanoparticle dispersed composite material of the present invention includes a step (a) of arranging a plurality of core fine particle-protein complexes having a core fine particle, which comprises an inorganic material, internally included within a protein on the top surface of a substrate, a step (b) of removing the protein, a step (c) of conducting ion implantation from the top surface of the substrate, and a step (d) of forming nanoparticles including the ion implanted by the ion implantation as a raw material, inside of the substrate.

Abstract: A deposition member adapted for discharging a deposition material during a deposition process can acquire a coating during the deposition. Such an initial emissivity value is selected for the deposition member, before any of the coating became deposited, that the emissivity of the deposition member remains substantially unchanged during the deposition process. In a representative embodiment the deposition member is coated with an appropriate thin layer for achieving the selected emissivity value.

Abstract: Provided is a phase-change element capable of operating with low power consumption and a method of manufacturing the same. The phase-change element comprises a first electrode used as a heating layer, a second electrode, which is laterally disposed adjacent to the first electrode, and a memory layer made of a phase-change material located between and contacting the side surfaces of the first electrode and the second electrode.

Abstract: A vacuum chuck for holding a semiconductor wafer during high pressure, preferably supercritical, processing comprising: a wafer holding region for holding the wafer; a vacuum region for applying vacuum to a surface of the wafer, the vacuum region within the wafer holding region; and a material, preferably sintered material, applied within the vacuum region, the material configurable to provide a uniform surface between the surface of the wafer and the wafer holding region, wherein the material is configured to allow vacuum to flow therethrough. The vacuum region preferably comprises at least one vacuum groove. Alternatively, the vacuum region includes at least two vacuum grooves that are concentrically configured on the wafer holding region. The vacuum groove alternatively comprises a tapered configuration. Alternatively, a coating material is applied between the wafer surface and the substantially smooth holding region surface, whereby the coating provides a seal between the wafer and the holding region.

Abstract: An apparatus for the treatment of semiconductor wafers, comprising a supportive frame and a process table arranged on the supportive frame. The process table comprises a stationary upper platen and a stationary lower plate. An intermediate indexing plate is rotatively arranged between the upper platen and the lower plate. At least one wafer support pin is attached to the indexing plate for the support of a wafer by the indexing plate. An upper housing is arranged on the upper platen and an outer lower housing is arranged on the lower plate. A displacable lower isolation chamber is disposed within the outer lower housing, being displacable against the indexing plate to define a treatment module between the upper housing and the lower isolation chamber in which the wafer is treated. A wafer supporting treatment plate is arranged within the lower isolation chamber, for controlled rapid treatment of a wafer within the treatment module.

Abstract: The present invention provides a bump forming apparatus (101, 501) which can prevent charge appearance semiconductor substrates (201, 202) from pyroelectric breakdown and physical failures, a method carried out by the bump forming apparatus for removing charge of charge appearance semiconductor substrates, a charge removing unit for charge appearance semiconductor substrates, and a charge appearance semiconductor substrate. At least when the wafer is cooled after the bump bonding is connected on the wafer, electric charge accumulated on the wafer (202) because of the cooling is removed through direct contact with a post-forming bumps heating device (170), or the charge is removed by a decrease in temperature control so that charge can be removed in a noncontact state. Therefore, an amount of charge of the wafer can be reduced in comparison with the conventional art, so that the wafer is prevented from pyroelectric breakdown and damage such as a break or the like to the wafer itself.