Abstract: CMOS logic LSI comprises, as a part thereof, n-channel MISFET's (Qn), p-channel MISFET's (Qp) and a first-layer wiring (11) to a third-layer (13) formed on a main surface of a silicon substrate (1), and as another part, a fourth-layer wiring (14) to a seventh-layer wiring (17) formed on a main surface of a glass substrate (30) different from the silicon substrate (1). The main surface of the silicon substrate (1) and the main surface of the glass substrate (30) are arranged in face-to-face relation with each other, and a plurality of microbumps (20A) formed at the uppermost portion of the silicon substrate (1) and a plurality of microbumps (20B) formed at the uppermost portion of the glass substrate (30) are electrically connected, thereby constituting the CMOS logic LSI as a whole.

Abstract: There is disclosed a method for clamping a semiconductor wafer, preferably suitable for a wafer with a diameter of 300 mm or larger. After depositing at least one encapsulating material layer over the front side and backside of the wafer, the material layer over the front side of the wafer is etched selectively to form a predetermined structure in following process steps. Wafer warpage is caused as a result of unequal wafer bowing stress of the material layer. By removing the material layer over the backside of the wafer partially or completely in accordance with the desired reduction of the bowing stress wafer warpage is reduced. In a further course of the manufacturing process, the semiconductor device is clamped electrostatically, physically or by use of vacuum.

Abstract: Disclosed are a semiconductor device and a method for fabricating the same and, more particularly, a method for decreasing the size of semiconductor devices by stacking two substrates, one of which has only memory cells and the other of which has only logic circuits is disclosed. The disclosed method includes forming memory cells on a first semiconductor substrate; forming logic circuits on a second semiconductor substrate; and stacking the second semiconductor substrate on the first semiconductor substrate in order that the memory cells are electrically operable to the logic circuits on the second semiconductor substrate. In the disclosed stacked semiconductor substrate, the logic circuit area is placed on the memory cell area and these two areas are electrically connected by a metal interconnection, thereby decreasing the size of the semiconductor devices.

Abstract: A thin film transistor of reversed stagger type having improved characteristics and yet obtained by a simple process, which is fabricated by selectively doping the semiconductor region on the gate dielectric to form the source, drain, and channel forming regions by using ion implantation, ion doping, or doping a plasma of ions; and then effecting rapid thermal annealing by irradiating a ultraviolet radiation, a visible light, or a near-infrared radiation for a short period of time. The source, drain, and channel forming regions are formed substantially within a single plane.

Abstract: A process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling are disclosed. The method includes providing a wafer of semiconductor material having a substrate; forming a plurality of first mutually adjacent trenches, open on a first face of the wafer, which have a depth and a width and define walls); by thermal oxidation, completely oxidizing the walls and filling at least partially the first trenches, so as to form an insulating structure of dielectric material; and removing one portion of the substrate comprised between the insulating structure and a second face of the wafer, opposite to the first face of the wafer.

Abstract: A microelectronic device and methods of fabricating the same comprising a microelectronic die having an active surface, a back surface, and at least one side. The microelectronic die side comprises a beveled sidewall and a channel sidewall. A metallization layer is disposed on the microelectronic die back surface and the beveled sidewall.

Abstract: A method for fabricating a memory array includes fabricating a first portion (110, 310, 510) of a memory array on a first side (14, 214, 414) of a substrate (12, 212, 412). A second portion (150, 350, 550) of the memory array is fabricated on a second, opposite side (16, 216, 416) of the substrate (12, 212, 412). The first portion (110, 310, 510) and the second portion (150, 350, 550) of the memory array are coupled to each other through the substrate (12, 212, 412).

Abstract: A method of forming a gate device which includes an elongated projection on a substrate. The elongated projection protrudes from a surrounding area of the substrate and includes an access channel for the gate device. A first terminal and a second terminal are formed and coupled to the access channel in the elongated projection. A gate structure is operable to control the access channel to selectively couple the first terminal to the second terminal.

Abstract: In order to suppress generation of waste matter which results from removing a backside film formed by growing a film on both surfaces of a semiconductor substrate and thereby attain satisfactorily high yield and productivity, on a semiconductor substrate 301, a polycrystalline silicon film 303 is formed through double-sided growth, and only on the obverse surface of the semiconductor substrate 301 a silicide film 304 is formed thereon, and then those polycrystalline silicon film 303 and silicide film 304 are worked into shape to form gate electrodes 303a. After that, on the semiconductor substrate 301, an insulating film for sidewall formation is formed to cover the gate electrodes 303a through double-sided growth, and the insulating film for sidewall formation formed on the obverse surface of the semiconductor substrate 301 is etched to form sidewall films.

Abstract: In a method of manufacturing a semiconductor device, an insulating film is formed on a semiconductor substrate, and a wiring line groove is formed in the insulating film. Then, a conductive film is formed to fill the wiring line groove and to cover the insulating film. The conductive film is removed using a CMP polishing method until the insulating film is exposed, to complete a wiring line. Subsequently, a front side of the semiconductor substrate is rinsed on which the wiring line is formed, and then a back side of the semiconductor substrate is rinsed while supplying to the front side of the semiconductor substrate, a protection solution for forming a protection film in an exposed surface of the wiring line.

Abstract: A method for singulating a semiconductor silicon wafer (10) comprising a plurality of semiconductor dice (20) arranged along a multiplicity of intersecting streets (30). Initially, a layer of photoresist (15)is patterned on the backside of the wafer (10). The semiconductor silicon wafer (10) is then etched using dry etching methods. As such, slots (22) are etched through the silicon of the wafer (10) aligned to the streets (30) forming a perforation. Simultaneously, tethers (40) are formed between the slots (22) interconnecting the adjacent dice (20) in order to maintain the wafer (10) mechanically intact. Furthermore, a membrane comprising integrated circuitry on the silicon wafer (10) is formed. The dice (20) of the wafer (10) are then separated for various purposes along the perforations. This is accomplished by applying pressure, such as manual pressure, to the wafer (10) so as to sever the tethers (40) which interconnect the dice (20) at their region (50) of reduced dimension.

Abstract: A semiconductor wafer processing apparatus grinds a surface of a semiconductor wafer by mechanical grinding, and then removes a damaged layer in the ground surface. In the processing apparatus, a grinding portion, a precenter portion, a wafer cleaning portion, plasma treatment portions, and magazines are arranged radially about an origin of a polar coordinate system of a third wafer transport portion having a robot mechanism, and their positions of arrangement are set such that the origin is located on lines of extension of wafer carry-in and carry-out center lines of the plasma treatment portions. Thus, the number of changed grippings of the semiconductor wafer can be minimized to prevent breakage of the semiconductor wafer. Moreover, transfer of the semiconductor wafer between the respective portions can be covered by the single robot mechanism, and the equipment can be made compact.

Abstract: A thin film transistor of reversed stagger type having improved characteristics and yet obtained by a simple process, which is fabricated by selectively doping the semiconductor region on the gate dielectric to form the source, drain, and channel forming regions by using ion implantation, ion doping, or doping a plasma of ions; and then effecting rapid thermal annealing by irradiating a ultraviolet radiation, a visible light, or a near-infrared radiation for a short period of time. The source, drain, and channel forming regions are formed substantially within a single plane.

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound during encapsulation. The increased adhesion reduces the delamination potential of the die from the package.

Abstract: Charge-up damages to a substrate are reduced in a manufacturing process using plasma, and the reliability of a semiconductor device is improved.

Abstract: A dual-sided semiconductor chip is formed on a wafer to have a low-resistance, electrically-conductive path through the wafer. By forming the conductive path through the wafer, elements on one side of the wafer can exchange signals (voltages and/or currents) with elements on the other side of the wafer.

Abstract: In order to suppress generation of waste matter which results from removing a backside film formed by growing a film on both surfaces of a semiconductor substrate and thereby attain satisfactorily high yield and productivity, on a semiconductor substrate 301, a polycrystalline silicon film 303 is formed through double-sided growth, and only on the obverse surface of the semiconductor substrate 301 a silicide film 304 is formed thereon, and then those polycrystalline silicon film 303 and silicide film 304 are worked into shape to form gate electrodes 303a. After that, on the semiconductor substrate 301, an insulating film for sidewall formation is formed to cover the gate electrodes 303a through double-sided growth, and the insulating film for sidewall formation formed on the obverse surface of the semiconductor substrate 301 is etched to form sidewall films.

Abstract: A method and apparatus for protecting hypersensitive microcircuits on the face of a semiconductor wafer from contamination and mechanical damage during die sawing and subsequent die handling operations include the provision of a plastic sheet having an array of protective domes formed into it, the array corresponding to the array of microcircuits on the wafer, and the temporary adhesion of the sheet to the face of the wafer such that each die in the wafer is covered by a respective one of the domes, with an associated one of the microcircuits protectively sealed therein. Die sawing is performed with the component side of the wafer facing up, the cut passing between the domes and through the thicknesses of both the domed sheet and the wafer such that each die is separated from the wafer, with a corresponding one other domes still attached to it. The domes may be removed later when the dies are located in a more benign environment by simply peeling them off the die.

Abstract: An edge-rounded portion mirror finishing process, which results in low deformation on a wafer, which has undergone a slicing process including a grinding process in which double-sided grinding is performed on the. sliced wafer; a finishing grinding process in which high-precision and low-deformation finish grinding is performed on the wafer; an edge rounding process in which low-deformation grinding is performed on an edge-rounded portion of the wafer; a two-sided primary polishing process in which primary polishing is performed on both sides of the edge-rounded wafer; a one-sided finish polishing process in which finish polishing is performed on one side of the wafer that has been primary polished on both sides; and a process in which finish polishing is performed on the edge-rounded portion of the above-mentioned wafer.

Abstract: A method for fabricating a SOI semiconductor device including providing a semiconductor substrate; forming a device isolation layer in and on a first surface of the semiconductor substrate to define an active region, including a source/drain region, and an inactive region; forming a first gate electrode on the first surface of the substrate; forming a first insulating layer on the first gate electrode; forming a capacitor, electrically connected to the source/drain region, on the first insulating layer; forming a second insulating layer on the capacitor; forming a third insulating layer on the second surface of the substrate; forming a body contact conductor line, electrically connected to the active region of substrate, on and through the third insulating layer; forming a fourth insulating layer on the body contact conductor line; and forming a bit line on the fourth insulating layer to be electrically connected to the source/drain region of the substrate.

Abstract: A surface of a substrate is oxidized at a temperature equal to or higher than 1050° C., or at a oxidation speed equal to or higher than 7.5 nm/min to form an oxide film with a thickness equal to or more than 1500 nm. when the oxide film is removed, a density of pits existent at the surface of a substrate is equal to or less than that prior to the oxidation treatment and a depth of a pit existent there is equal to or less than 50 nm. An element isolation withstand voltage can be prevented from lowering and a fabrication yield of a miniaturized, highly integrated semiconductor device can be improved.

Abstract: A technique for fabricating precision aligned macros (PAMs) with reduced risk of electrostatic discharge damage and thermal damage. An electrical and thermal contact is provided through the back of the individual chips to a supporting silicon substrate. A conductive seed layer for electroplating is formed on a support substrate. A dielectric (preferably, a thermid) layer is formed on the seed layer. Vias are formed in the thermid layer and metal contacts are formed in the vias. The front faces of two or more chips are bonded onto the top surface of an alignment substrate, and the chips are aligned to the alignment substrate. The back faces of the chips are bonded to the metal contacts and thermid layer with heat and pressure. The alignment substrate is removed. The front faces of the chips are planarized. Finally, interconnect wiring is formed over the chips and thermid layer.

Abstract: The present invention provides new and improved methods for making crystalline semiconductor thin films which may be bonded to different kinds of substrates. The thin films may be flexible. In accordance with preferred methods, a multi-layer porous structure including two or more porous layers having different porosities is formed in a semiconductor substrate. A semiconductor thin film is optionally grown on the porous structure. Electrodes and/or a desired support substrate may be attached to the grown film. The grown film or an upper portion of the semiconductor substrate is separated from the semiconductor substrate along a line of weakness defined in the porous structure. The separated thin film attached to the support substrate may be further processed to provide improved film products, solar panels and light emitting diode devices.

Abstract: A method of packaging a chip made in a semiconductor wafer. The method includes providing, on a first surface of the wafer, a conductive area extending beyond the periphery of the chip; adding a first thick plate including an electrically isolating material on the first surface; etching the conductive layer from a second surface of the wafer and depositing a conductive track extending from a contact of the second chip surface to the exposed surface of the conductive area; covering the second surface with a second thick plate forming a rigid cap; and etching the first plate above the conductive layer to deposit thereon a conductive material extending, in the form of a track, to the exposed surface of the first plate.

Abstract: To provide a method and a device for subjecting a film to be treated to a heating treatment effectively by a lamp annealing process, ultraviolet light is irradiated from the upper face side of a substrate where the film to be treated is formed and infrared light is irradiated from the lower face side by which the lamp annealing process is carried out. According to such a constitution, the efficiency of exciting the film to be treated is significantly promoted since electron excitation effect by the ultraviolet light irradiation is added to vibrational excitation effect by the infrared light irradiation and strain energy caused in the film to be treated by the lamp annealing process is removed or reduced by a furnace annealing process.

Abstract: A method for evaluating the concentration of impurities in gases and equipment used in heat treatment of a semiconductor substrate is provided. The method includes processing a semiconductor substrate of known impurity levels in a heat treatment furnace, and measuring the impurity levels after the heat treatment processing by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were transferred to the substrate from the heat treatment process.

Abstract: A method for fabricating a memory array includes fabricating a first portion (110, 310, 510) of a memory array on a first side (14, 214, 414) of a substrate (12, 212, 412). A second portion (150, 350, 550) of the memory array is fabricated on a second, opposite side (16, 216, 416) of the substrate (12, 212, 412). The first portion (110, 310, 510) and the second portion (150, 350, 550) of the memory array are coupled to each other through the substrate (12, 212, 412).

Abstract: Semiconductor processing methods and defect detection methods are described. In one embodiment, a semiconductor wafer in process is provided and a material is formed or deposited over the wafer. The material is discernably deposited over defective wafer surface areas and not appreciably deposited over non-defective wafer surface areas. Subsequently, the wafer surface areas are inspected to identify defective areas. In another embodiment, a substrate is provided having an exposed region containing surface defects. A defect-highlighting material is substantially selectively deposited over surface defects and not appreciably over other exposed regions. The substrate is subsequently inspected for the deposited defect-highlighting material. In yet another embodiment, a dielectric layer is formed over a substrate outer surface and the substrate is processed in a manner which can give rise to a plurality of randomly-distributed dielectric layer features.

Abstract: In a process for treating a workpiece such as a semiconductor wafer, a processing fluid is selectively applied or excluded from an outer peripheral margin of at least one of the front or back sides of the workpiece. Exclusion and/or application of the processing fluid occurs by applying one or more processing fluids to the workpiece while the workpiece and a reactor holding the workpiece are spinning. The flow rate of the processing fluids, fluid pressure, and/or spin rate are used to control the extent to which the processing fluid is selectively applied or excluded from the outer peripheral margin.

Abstract: An anti-reflection film of an organic compound is formed on a substrate. The anti-reflection film is weakened by carrying out plasma processing on the anti-reflection film, and then, a resist film is formed on the weakened anti-reflection film. The resist film is subjected to pattern exposure and development so as to form a resist pattern from the resist film. The anti-reflection film is dry etched by using the resist pattern as a mask, so as to pattern the anti-reflection film.

Abstract: A light absorbing layer composed of intentionally undoped n-type InGaAs and a window layer composed of intentionally undoped n-type InP are formed sequentially on a first principal surface of a semiconductor substrate composed of n-type InP. A cathode is provided on a p-type diffused region forming an island pattern in the window layer, while an anode is provided on a second principal surface of the semiconductor substrate. A side edge portion of the second principal surface of the semiconductor substrate is formed with a gradient portion having an exposed surface with a (112) plane orientation and forming an angle of 35.3° with respect to the second principal surface. The gradient portion is formed to have a mirrored surface by using an etching solution containing hydrochloric acid and nitric acid at a volume ratio of approximately 5:1 to 3:1.

Abstract: A method and apparatus for lapping or polishing a semiconductor silicon single crystal wafer is provided for eliminating the transfer of waviness of a wafer cut by a wire saw apparatus, improving the quality of the wafer, realizing automated lapping or polishing processes, allowing for single crystal processing from a cassette to another cassette, and increasing the workability and labor productivity. A small amount “e” of single-side lapping or single-side polishing is repeated alternately on the two sides “A” and “B” of a semiconductor silicon single crystal wafer “W” to get to a predetermined total lapping or polishing stock removal.

Abstract: A method for manufacturing a micromechanical component, in particular, a surface-micromechanical yaw sensor, includes the following steps: providing a substrate having a front side and a back side; forming a micromechanical pattern on the front side; applying a protective layer on the micromechanical pattern on the front side; forming a micromechanical pattern on the back side, a resting on the micromechanical pattern on the front side taking place at least temporarily; removing the protective layer on the front side; and optionally further processing the micromechanical pattern on the front side and/or the micromechanical pattern on the back side.

Abstract: Obtained is a method of manufacturing a semiconductor device which can take a body contact while electrically isolating an NMOS transistor and a PMOS transistor from each other through a complete isolation. First of all, element isolating films (7a to 7c) of a partial isolation type are formed in a first main surface of a silicon layer (3). Next, a PMOS transistor, an NMOS transistor, a multilayer wiring structure, a spiral inductor (20) and a pad (22) are formed, respectively. Then, a support substrate (23) is formed over the whole surface. Thereafter, a silicon substrate (1) and a BOX layer (2) are removed to expose a second main surface of the silicon layer (3). Subsequently, element isolating films (27a to 27d) connected to the element isolating films (7a and 7b) are formed on the second main surface side of the silicon layer (3). Consequently, a complete isolation can be obtained.

Abstract: After a trench 54 is formed in a conductive foil 60, a circuit element is mounted in a flip chip method. Then, an insulating resin 50 is covered on the conductive foil 60 as a support substrate. After reversion, the conductive foil 60 is polished over the insulating resin 50 as a support substrate at this time to separate the conductive paths. Accordingly, a circuit device having the conductive paths 51 and the circuit elements 52 supported by the insulating resin 50 can be produced without employing the support substrate.

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: Two contradictory problems of the reduction in the thickness of semiconductor chips or package parts including the semiconductor chips and the improvement in mechanical strength are solved. A semiconductor wafer where semiconductor elements are formed on a first surface thereof or semiconductor chips formed by dicing the semiconductor wafer are reduced in thickness by grinding the second surface opposite to the first surface, and grinding scratches formed by the grinding are removed to smooth the second surface. Since dicing scratches are formed on side surfaces of the semiconductor chips by dicing, the side surfaces are etched together with the second surface to remove the dicing scratches as well as the grinding scratches, thereby smoothing the second surface and the side surfaces.

Abstract: A method for developing a pattern, on a photosensitive material of negative type, including the steps of depositing the photosensitive material on a surface of a semiconductor substrate; drying the material to obtain the adherence of the material while maintaining some flexibility to it; exposing, according to a desired pattern, regions of the photosensitive material; and annealing to solidify the photosensitive material.

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound during encapsulation. The increased adhesion reduces the delamination potential of the die from the package.

Abstract: A package for a semiconductor device is formed by a process which includes forming a metal layer in contact with a connection pad on the front side of a semiconductor die while the die is still a part of a wafer. The metal layer extends into the scribe line between the die and an adjacent die. A nonconductive cap is attached to the front side of the wafer, and the wafer is ground from its back side to reduce its thickness. A cut is made from the back side of the wafer, preferably by sawing and etching, to expose the metal layer. A nonconductive layer is formed on the back side of the wafer and a second metal layer is deposited over the nonconductive layer, the second metal layer extending into the scribe line where it makes contact with the first metal layer through an opening in the nonconductive layer. Preferably, a solder post is formed on the second metal layer to allow the finished package to be mounted on a printed circuit board.

Abstract: A light shielding thin metal film is formed over one or back surface of a semiconductor wafer. Material of the film includes aluminum (Al) and gold (Au).

Abstract: Grooves are formed in a surface of a wafer, on which semiconductor elements are formed, along dicing lines or chip parting lines on the wafer. The grooves are deeper than the thickness of a finished chip, and each of them has a curved bottom surface. A holding sheet is attached on the surface of the wafer on which the semiconductor elements are formed. Subsequently, the rear surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. Even after the wafer is divided into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip. The lapping and polishing amount required to attain the thickness of the finished chip after the lapped face of the wafer reaches the bottom surface of the groove, and a depth of a region of the curved bottom surface of the groove define a ratio of not less than 0.3.

Abstract: The present invention removes unwanted deposited material from a substrate backside by chemically dissolving the material, while substantially preventing dissolution of the material from the substrate front side. Preferably, the dissolving process is included with a spin-rinse-dry process and uses a greater flow rate of rinsing fluid directed onto the front side compared to the flow rate of dissolving fluid directed onto a substrate backside to protect the substrate front side while the unwanted backside material is removed. The present invention includes the method of dissolving the unwanted material from the backside and edge and the associated apparatus.

Abstract: A semiconductor device mask and a method for forming the same is provided in which a mask pattern defines dummy active regions in isolating regions. The semiconductor device mask and method reduce surface unevenness and prevent damage to an active region, which have been problems in isolating devices by trenches. The semiconductor device mask includes real active pattern regions formed in regions defined as the active regions in a mask having an isolating region and the active regions. A plurality of dummy active pattern regions preferably spaced at fixed intervals from one another surrounding relatively isolated active regions and excluding gate pattern forming regions. The gate pattern forming regions are preferably formed extending in one direction across the isolating region and the real active pattern regions.

Abstract: A method and apparatus for lapping or polishing a semiconductor silicon single crystal wafer is provided for eliminating the transfer of waviness of a wafer cut by a wire saw apparatus, improving the quality of the wafer, realizing automated lapping or polishing processes, allowing for single crystal processing from a cassette to another cassette, and increasing the workability and labor productivity. A small amount of single-side lapping or single-side polishing is repeated alternately on the two surfaces of a semiconductor silicon single crystal wafer to get to a predetermined total lapping or polishing stock removal.

Abstract: Semiconductor processing methods and defect detection methods are described. In one embodiment, a semiconductor wafer in process is provided and a material is formed or deposited over the wafer. The material is discernably deposited over defective wafer surface areas and not appreciably deposited over non-defective wafer surface areas. Subsequently, the wafer surface areas are inspected to identify defective areas. In another embodiment, a substrate is provided having an exposed region containing surface defects. A defect-highlighting material is substantially selectively deposited over surface defects and not appreciably over other exposed regions. The substrate is subsequently inspected for the deposited defect-highlighting material. In yet another embodiment, a dielectric layer is formed over a substrate outer surface and the substrate is processed in a manner which can give rise to a plurality of randomly-distributed dielectric layer features.

Abstract: A semiconductor wafer etching method is disclosed that allows etching without use of restricted ozone-destroying solvents such as trichloroethane or fluorocarbons. This method involves forming a protective film of silicon resin or alkali resistant resin on a semiconductor wafer. Then, a surface region of the wafer not covered by the protective film is etched. Finally, the protective film is peeled from the semiconductor wafer without damaging the wafer or employing solvents harmful to the environment.

Abstract: A method of processing a semiconductor wafer sliced from a monocrystalline ingot comprises at least the steps of chamfering, lapping, etching, mirror-polishing, and cleaning. In the etching step, alkali etching is first performed and then acid etching, preferably reaction-controlled acid etching, is performed. The etching amount of the alkali etching is greater than the etching amount of the acid etching. Alternatively, in the etching step, reaction-controlled acid etching is first performed and then diffusion-controlled acid etching is performed. The etching amount of the reaction-controlled acid etching is greater than the etching amount of the diffusion-controlled acid etching.

Abstract: The specification describes thin film transistor integrated circuits wherein the TFT devices are field effect transistors with inverted structures. The interconnect levels are produced prior to the formation of the transistors. This structure leads to added flexibility in processing. The inverted structure is a result of removing the constraints in traditional semiconductor field effect device manufacture that are imposed by the necessity of starting the device fabrication with the single crystal semiconductor active material. In the inverted structure the active material, preferably an organic semiconductor, is formed last in the fabrication sequence. In a preferred embodiment the inverted TFT devices are formed on a flexible printed circuit substrate.

Abstract: An alternative to conventional SOI and dielectric filled trenches for electrical isolation of integrated circuits is disclosed. This has been achieved by using proton bombardment to form semi-insulating regions. For all embodiments, the process of the invention begins only after the integrated circuit has been fully formed. In a first embodiment, protons bombard the entire back surface of the wafer thereby forming a substrate of semi-insulating material (resistivity greater than 105 ohm cm) on which the active and passive components rest. In the second embodiment, isolation trenches are formed by bombarding from the top surface through a contact mask formed by means of LIGA or similar technology. The third embodiment is a combination of the first two wherein both isolation regions and the semi-insulating substrate are formed.