Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.
Abstract: A method is provided for optimizing the manufacturing yield of semiconductors. The method provides a backside dielectric layer which protects the semiconductor from electro-static discharge damage during manufacturing. The backside dielectric layer may be a nitride. The backside dielectric layer may be an oxide. The method also provides for optimized ion implantation flood gun current control.
Type:
Grant
Filed:
November 22, 1994
Date of Patent:
August 12, 1997
Assignee:
Lucent Technologies Inc.
Inventors:
Terry Chrapacz, Kenneth Gordon Moerschel, William A. Possanza, Michael Allen Prozonic, Janmye Sung
Abstract: In a vapor phase epitaxial growth process, formation of a silicon nodule on a back side protective film on a wafer is prevented. In the process, a susceptor situated within a reaction chamber is provided with a depression portion for supporting a wafer at a back side peripheral portion thereof. A protection film on a back side peripheral portion of the wafer, which is to be in contact with the susceptor 4 is removed in advance, prior to epitaxial growth. In addition, it is also effective to apply a silicon coating on the surface of the depression portion, prior to the epitaxial growth process.