Abstract: In order to provide a method for fabricating semiconductor devices and a heat treatment apparatus in which stable annealing can be performed without causing harmful effects such as thermal stresses on an insulating substrate and the surface of a semiconductor thin film formed on the insulating substrate, in a heat treatment method for a substrate provided with an amorphous silicon film in the heating step, the substrate is preheated by irradiating the substrate from the side of one surface of the substrate with intermediate infrared rays having a wavelength band of 2.5 to 5 &mgr;m, and then, in the heat-treating step, the amorphous silicon film is annealed for crystallization at temperatures between 800 to 1,000° C. by irradiating the substrate from the side of the other surface of the substrate with near infrared rays having a wavelength band of 2.5 &mgr;m or less.

Abstract: Integrated circuitry and methods of forming integrated circuitry are described. In one aspect, a hole is formed in a semiconductor wafer. In a preferred implementation, the hole extends through the entire wafer. Subsequently, conductive material is formed within the hole and interconnects with integrated circuitry which is formed proximate at least one of a front and back wafer surface. According to one aspect of the invention, integrated circuitry is formed proximate both front and back surfaces. In a preferred implementation, a plurality of holes are formed through the wafer prior to formation of the integrated circuitry. In accordance with a preferred implementation, formation of the conductive material within the hole takes place through formation of a first material within the hole. A second material is formed over the first material, with at least the second material being electrically conductive.

Abstract: Grooves are formed in a surface of a wafer, on which surface semiconductor elements are formed, along dicing lines on the wafer by means of a dicing blade. The grooves are deeper than a thickness of a finished chip. Alternatively, grooves are formed in a surface of a wafer, on which surface semiconductor elements are formed, along chip parting lines on the wafer by etching. Like the grooves described above, the grooves are deeper than a thickness of a finished chip. A holding member is attached on the surface of the wafer on which the semiconductor elements are formed. The bottom surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. When the wafer is divided into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip, even after the wafer has been divided into the chips by the lapping and polishing.

Abstract: A method is described by which the mechanical strength of chips of semiconductor devices can be controlled by appropriate wafer finishing and sorted by knowledge of the finishing method and chip and wafer geometry. The control and sorting derive from a knowledge of the geometry of the striations remaining on the back of chips after the wafer-grinding finishing step.

Abstract: A method for efficiently fabricating semiconductor wafers of good planarization without utilizing chemical solutions of high etching rate is disclosed. The method slices a single-crystal ingot into slices of wafers. The edge of each wafer is chamfered. A lapping or grinding step is carried out to planarize the chamfered wafer. Both side surfaces of the wafer are then polished. Next, the wafer surface is mirror polished. Finally, the wafer is cleaned.

Abstract: An object of the invention is to provide a preparation process of a semiconductor wafer, in which breakage of the wafer on grinding the back surface of the wafer and on peeling the adhesive tape is prevented, and the operation time can be reduced. The preparation process of a semiconductor wafer comprises the steps of: adhering an adhesive tape on a front surface of a semiconductor wafer; grinding a back surface of the semiconductor wafer by a grinding machine; peeling the adhesive tape; and cleaning the front surface of the semiconductor wafer, wherein an adhesive tape having heat shrinkability is used as the adhesive tape, and after grinding the back surface of the semiconductor wafer, warm water at a temperature of from 50 to 99.degree. C. is poured to peel the adhesive tape in a wafer cleaning machine, and the front surface of the semiconductor wafer is cleaned in the wafer cleaning machine.

Abstract: Multichip and single chip modules are presented as well as a chips first fabrication of such modules. The multichip module comprises a plurality of chips affixed in a planar array by a structural material which surrounds the sides of the chips such that the upper surfaces of the chips and an upper surface of the structural material are co-planar and the lower surface of at least one chip and a lower surface of the structural material are co-planar. A photo-patternable dielectric is disposed directly on the upper surfaces of the chips. The photo-patternable dielectric includes vias to at least some contact pads at the upper surfaces of the chips and the module further comprises an intrachip metallization layer on the photo-patternable dielectric layer. Subsequent processing provides a multi-layer chip interconnect structure over the intrachip metallization layer and photo-patternable dielectric.

Abstract: A semiconductor wafer analysis system and method. In various embodiments, methods and systems are described for inspection and review of semiconductor wafers. Wafer inverters are provided, and inspection data is gathered for both the front and back sides of the wafers. The wafer inverters are also available at wafer review stations so that both the front and back sides of the wafers can be reviewed with a microscope.

Abstract: Disclosed is a method for fabricating a silicon-on-insulator wafer, particularly to a cost reductive method.

Abstract: A method of fabricating a SOI wafer using an isolation film as a polishing stopper, comprising the steps of: preparing a first and a second silicon substrates; implanting impurities into selected active regions of the first silicon substrate to a desired depth; etching the portion of the silicon substrate between the active regions to forming trenches having a desired depth; forming a first insulating layer of an oxide film on the first silicon substrate to be filled in the trenches; etching-back the first insulating layer to form a trench type isolation film; forming a second insulating layer of an oxide film on the first silicon substrate including the isolation film; bonding the first and the second silicon substrates to contact the second insulating layer with the second silicon substrate; firstly polishing the first silicon substrate by the vicinity of the portion of the first silicon substrate where the impurities are implanted; etching the polished first silicon substrate by using an etchant until the

Abstract: A method of manufacturing a semiconductor article comprises steps of forming a diffusion region at least on the surface of one of the sides of a silicon substrate by diffusing an element capable of controlling the conduction type, forming a porous silicon layer in a region including the diffusion region, preparing a first substrate by forming a nonporous semiconductor layer on the porous silicon layer, bonding the first substrate and a second substrate together to produce a multilayer structure with the nonporous semiconductor layer located inside, splitting the multilayer structure along the porous silicon layer but not along the diffusion region and removing the porous silicon layer remaining on the split second substrate.

Abstract: Methods are disclosed for depositing an in situ polysilicon layer on the back of a semiconductor wafer to reduce the temperature at the edge of the wafer during rapid thermal annealing (RTA). The reduced temperature results in decreased boron penetration at the edge of the wafer and a more uniform silicide resistance and threshold voltage across the wafer.

Abstract: A method for creating via holes in a chip or a plurality of chips of a wafer is disclosed. The method is performed by using a pre-patterned transparent mask on the back of the chip or chips, and bombarding the chip(s) through the positioning holes on the transparent mask that correspond to the pre-formed pattern, with accelerated particles. According to this method, via holes can be created from the back of the chip(s) without interfering with the existing IC structure of the chip(s). The present method is highly efficient because a number of via holes can be formed simultaneously by using a large pre-pattered mask to cover the entire wafer. In addition, the present method is cost-effective because no precision apparatus is required.

Abstract: A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a covet layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer.

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound during encapsulation. The increased adhesion reduces the delamination potential of the die from the package.

Abstract: A method of fabricating a semiconductor device is provided wherein a first semiconductor substrate is prepared with a first insulating film formed over a first main surface of the first semiconductor substrate, s semiconductor film of n-type conductivity formed over the first insulating film, and a second insulating film formed over the semiconductor film so as to cover the first main surface. A second semiconductor substrate is also prepared with a third insulating film formed over the second semiconductor substrate. Next, the second insulating film and third insulating films are bonded together by thermal processing to join the first semiconductor substrate and the second semiconductor substrate. A portion of a second main surface of said first semiconductor substrate, opposite to said first main surface of the first semiconductor substrate is then removed to expose a portion of the first semiconductor substrate, thereby providing a semiconductor layer.

Abstract: A process for etching and filling a trench prevents the top opening of the trench from being closed off prior to the trench being completely filled. After a masking layer is deposited and patterned, the trench is etched and then the masking layer is removed. A first liner insulating layer is grown or deposited and is then etched anisotropically to remove the layer from the top surface of the substrate as well as from the top portion of the walls of the trench. A second, thinner liner layer is grown or deposited on the exposed portion of the walls of the trench to provide surface and edge protection. A polysilicon layer is then deposited to fill the trench and is planarized to remove the portion deposited on the top surface of the substrate. Alternatively, the thinner oxide liner can be omitted, and the polysilicon is removed by chemical mechanical polishing until the trench liner oxide appears on the top surface. An overlaying insulation layer is then deposited.

Abstract: A serpentine pattern has been found to be effective at interrupting propagation of delamination cracks in thin film layers. The ring is provided on a semiconductor chip to suppress crack propagation from the chip edge. The ring is effective even though it is filled with metal, the serpentine pattern providing significantly increased area as compared with a standard linear crack stop that the energy for crack propagation is dissipated. In addition to serpentines, pattern features such as staggered filled ring patterns and connected rings will also be effective at reducing the propagation of delamination cracks from edge to active area by virtue of the increased area of interaction between the crack and the crack stop.

Abstract: The present invention is a method for preventing backside polysilicon peeling in 4T+2R SRAM process. This invention utilizes forming oxide cap layer on the backside of the wafer to protect the backside polysilicon. Thus, the backside polysilicon is free from peeling and damage.

Abstract: In a method of manufacturing a semiconductor substrate, a first stage semiconductor substrate wafer is cut out from an ingot. Then, a chemical mechanical polishing process is performed to the first stage semiconductor substrate wafer to produce a second stage semiconductor substrate wafer respectively having mirror surfaces on front and rear surfaces of the second stage semiconductor substrate wafer. Subsequently, a third stage semiconductor substrate wafer is produced from the second stage semiconductor substrate wafer without performing an additional chemical mechanical polishing process, to have a blocking film on the rear surface and a mirror surface on the front surface. Finally, an epitaxial layer is grown on the front surface of the third stage semiconductor substrate wafer.

Abstract: A method is provided involving re-slicing a wafer after dual-side alignment and processing has been performed. This procedure provides twice as many processed electronic devices without increasing the number of loading, processing and unloading procedures performed or the total number of substrates used. Another method is provided for creating two processed chips by attaching two conventional substrates, processing IC's on each of the two exposed, polished sides and then detaching the substrates. This technique reduces the number of loading, processing and unloading procedures required to produce a given number of IC chips by half. An apparatus and further method provides two different subsystems of a single IC processed on opposite sides of the same chip. Such a device saves cost by using fewer substrates to make the same number of chips. Also, the method performs loading, processing and unloading procedures half as much to produce a given number of IC's.

Abstract: A semiconductor package comprising multiple stacked substrates having flip chips attached to the substrates with chip on board assembly techniques to achieve dense packaging. The substrates are preferably stacked atop one another by electric connections which are column-like structures. The electric connections achieve electric communication between the stacked substrates, must be of sufficient height to give clearance for the components mounted on the substrates, and should preferably be sufficiently strong enough to give support between the stacked substrates.

Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.

Abstract: Methods of treating wafers for analyzing defects present therein comprise providing wafers having front side surfaces comprising defective portions and a back side surfaces opposite thereto; and decorating the defective portion of the front side of the wafer with copper.

Abstract: This invention provides a method for efficiently making semiconductor wafers having uniform thickness where the thickness of the back side does not influence the front side and where the front side of the wafer is capable of being distinguished from the back side. A semiconductor ingot is sliced to obtain wafers. The sliced surfaces of the wafers are flattened. The flattened wafer is etched in alkaline etching solution. Both the front and back sides of the etched wafer are polished using a double sided polishing apparatus so that the front side is a mirror surface and an unevenness remains on the back side to distinguish the front and back sides, thereof. The polished wafer is cleaned.

Abstract: Our semiconductor device is an IC chip 10 whose back surface is affixed to a mounting section 81 by means of a thermoplastic adhesive (for example, thermoplastic polyimide) 84. Package cracks are eliminated or markedly reduced and the problems with productivity for mounting curing and mounting alleviated. Even when a padless special lead frame or one with a small die pad is used, package cracks are eliminated or markedly reduced, and the lead frame can be mounted easily and with good reliability on top of the lead frame.

Abstract: A method for manufacturing a semiconductor device on a wafer that has a substrate with a front side and a backside, and an accumulation of waste matter on the backside of the substrate. In a method of the invention, a cover layer is deposited over the front side in a normal coating step of a process for fabricating a component on the wafer. The cover layer provides material used in the process for fabricating the component on the front side of the wafer and creates a barrier over the front side. The waste matter is removed from the backside of the wafer by etching the waste matter from the backside of the wafer with a suitable etchant, or by planarizing the backside of the wafer with a chemical-mechanical planarization ("CMP") process. During the removal step, the cover layer protects the front side and any device features on the front side from being damaged while the waste matter is removed from the backside of the wafer.

Abstract: The present invention provides a structure and a method of fabricating a thermoelectric Cooler directly on the backside of a semiconductor substrate. The thermoelectric (TE) cooler (thermoelectric cooler) disperses heat from an integrated circuit (IC) that is formed on the front-side of the silicon substrate. Spaced first bonding pad holes 28 are formed in the backside of a substrate that expose bonding pads 24. Second holes 32 are formed between the spaced first bonding pad holes 28. A first insulating layer 34 is formed over the backside of the substrate, but not over the bonding pad 24. A metal layer is formed lining the first bonding pad holes 28. A polysilicon layer 46 is formed over the surface of the backside of the substrate in the second holes. The polysilicon layer is implanted thereby forming alternating adjacent N and P doped sections 46p 46n in the second holes. The adjacent N and P doped polysilicon sections 46n 46p are electrically connected to the bonding pads 24 by the metal layer 38.

Abstract: The wafer thickness of a CCD front illuminated silicon wafer is reduced to about ten to twenty microns, the Al substrate is removed and a 5-35 nanometer silicon oxide layer is produced on the thinned back of the silicon wafer followed by implanting boron ions within the back surface to a depth up to about ten nanometers. Furnace annealing the wafer is now carried out, and the Al substrate is redeposited to enable the formation of gate contacts.

Abstract: The present invention provides metal layer patterns of a semiconductor device which reduces the effect of the current induced by the plasma in the etching process and prevents the device characteristics from being deteriorated, by a method for forming a photomask to pattern metal layers of a semiconductor device including the steps of: designing base metal line patterns, the base metal line patterns being required for the proper operation of the semiconductor device; expanding the base metal line patterns outwardly by an expanding distance; designing a dummy metal line patterns by reversing the expanded base metal line patterns; and designing a final metal line patterns of the semiconductor device by combining the base metal line patterns and the dummy metal line patterns.

Abstract: A process applicable to the restoration of defective or rejected semiconductor wafers to a defect-free form uses etchants and a variation of the Smart-Cut.RTM. process. Because of the use of the variation on the Smart-Cut.RTM. process, diffusion regions are removed without significantly affecting the specifications of the semiconductor wafer. Therefore, a defective or rejected wafer can be restored to near original condition for use in semiconductor manufacturing.

Abstract: In manufacturing a semiconductor device on a glass substrate, a conductive thin-film (for instance, a conductivity-imparted silicon film) is formed on the bottom surface side of the glass substrate at the initial stage of a manufacturing process. Since the conductive thin film serves as an electrostatic shield, the glass substrate is prevented from being electrified directly, whereby electrostatic breakdown of device elements as would otherwise be caused by electrification of the glass substrate can be avoided.

Abstract: A method for efficiently fabricating semiconductor wafers of good planarization without utilizing chemical solutions of high etching rate is disclosed. The method slices a single-crystal ingot into slices of wafers. The edge of each wafer is chamfered. A lapping step is carried out to planarize the chamfered wafer. Both side surfaces of the wafer are then polished. Next, the wafer surface is mirror polished. Finally, the wafer is cleaned.

Abstract: A wafer processing method which can polish the chamfered portion of a wafer quickly, is disclosed. The processing method comprises the steps of: chamfering a peripheral portion of a wafer obtained by slicing an ingot, by grinding; lapping the wafer; etching the chamfered or lapped wafer; thereafter honing the entirety of the chamfered peripheral portion of the wafer by using a grinding stone while applying a predetermined load to the grinding stone; and thereafter polishing the entirety of the chamfered peripheral portion and the front and rear surfaces of the wafer.

Abstract: Trench structures (12,32,35,46) are formed in single crystal silicon substrates (10,30) that have either a (110) or (112) orientation. A selective wet etch solution is used that removes only the exposed portions of the single crystal silicon substrates (10,30) that are in the (110) or (112) crystal planes. The trench structures (12,32,35,46) are defined by the {111} crystal planes in the single crystal silicon substrate (10,30) that are exposed during the selective wet etch process. Trench structures (32,35) can be formed on both sides of a single crystal silicon substrate (30) to form an opening (34). Opening (34) can be used as an alignment mark to align front side processing to backside and vice versa. Trench structures can also be use to form a microstructure (41,61) for a sensor (40,60).

Abstract: A thick column is formed by masking and etching a substrate, and the column is thinned to a very small diameter (e.g., .ltoreq.5 nm) by oxidizing the column and removing the oxide layer. A metal layer is deposited on the surface of the substrate, and the column and substrate are etched to form a pit. The backside of the substrate is etched to form an aperture surrounded by the metal layer. Alternatively, the metal layer is removed and a dopant layer is implanted into the substrate, followed by the etching of the backside, leaving an aperture surrounded by the dopant layer. In a second alternative, the oxidized column is broken from the substrate, and the backside is etched, leaving an aperture surrounded by an oxide layer. These processes can be used to fabricate apertures of very small and reproducible dimensions for such instruments as near field scanning optical microscopes and scanning ion conductance microscopes.

Abstract: An auxiliary device is constituted by a U-bolt-shaped, pincer-like implement which, during the fabrication of semiconductor devices with a mesa structure from a starting substrate forming a wafer, serves to transfer the outline geometry of the individual semiconductor devices from one side of the wafer to the back of the wafer. The implement has at least one tracer at the end of one of its arms for engaging a sawed groove and for guiding the implement along the sawed groove on one side of the wafer. At the end of the other arm, a marking device with at least one marking stylus is provided whereby the course of the at least one sawed grooved can be transferred from the front side of the wafer to the back, and scribed there in the form of auxiliary lines.

Abstract: There is disclosed a method for making a field oxide, by which wafer warpage is minimized when a local oxidation of silicon process is applied for a large wafer. A material layer having a compressive stress and a nitride are laminated over the back side of a wafer, so that the compressive stress of the material layer complementarily interacts with the tensile stress of the nitride.

Abstract: A method for fabricating a semiconductor wafer to reduce the number of processing steps and produce low-cost wafers in a short time is disclosed. The method involves surface grinding both the front surface and back surface of a single-crystal silicon wafer which has been sliced from a rod and chamfered. In the surface grinding step, the size numbers of abrasive grains are larger than #2000 for front surface grinding, and smaller than #600 for back surface grinding. The front surface is then chemical polished as a mirror surface which satisfies the requirement of a later photolithography step. Moreover, a deformation layer formed on the back surface of the semiconductor wafer is partially etched and left to provide an extrinsic gettering function. An epitaxial layer can be formed on the front surface to make the wafer an epitaxial wafer. The method of the present invention requires fewer process steps as compared with conventional methods, thereby reducing manufacturing time and cost.

Abstract: A layered structure for a semiconductor substrate has a planar surface, lighter weight, and increased flexural rigidity. By decreasing warping in a multilayered recording medium that arises when forming the recording layer, while suppressing an increase in the weight of the memory substrate, a recording medium for a compact, large capacity memory device can be manufactured. The recording medium is positioned opposite a read/write circuit substrate that is provided with a plurality of miniature probes. A recording layer is formed on a front surface of a memory substrate, a beam structure for reinforcing flexural rigidity is formed on a back surface of said memory substrate. A conductive layer may be formed between the memory substrate and the recording layer.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: A method of improving electrostatic chucking efficiency between a silicon wafer which has an oxide layer formed on a back side and a susceptor positioned in a wafer processing chamber wherein the back side is opposite to the side of the wafer to be processed for integrated circuit devices including the steps of first forming an electrically conducting layer on top of the oxide layer by transforming to a more hydrophilic oxide structure and then positioning the wafer on the susceptor with the electrically conducting layer contacting the susceptor.

Abstract: A bonded wafer has a first handle wafer 12, a device layer 10', an interconnect layer 14, and a number of vias filled with conductive material that extends between the surfaces 6, 8 of the device layer 10'. the interconnect layer 14 has conductors that connect internal device contacts to the conductive vias. A second handle wafer 40 of glass is bonded to the interconnect layer 14 and the first handle wafer is removed. Bottom, external contacts 36 are formed on surface 6 of device layer 10'.

Abstract: Uniformity of thin deposited layers on textured surfaces is enhanced by reducing the total surface area available to film deposition. The backside surface area of a semiconductor wafer is reduced prior to film deposition, thereby reducing the available surface to deposition when a deposition process is supply-limited. Reducing the backside surface area suppresses nonuniformities in thin film deposition when the deposition process is substantially supply-limited. The present invention is advantageous for improving uniformity of nitride capacitor dielectric layers deposited on textured electrodes.

Abstract: A product and process for making backside inned semiconductor image sensing devices employing neutral ion beams to reduce substrate volumes so that the image sensor can be illuminated from the backside, or side opposite etched circuitry. A neutral ion beam is contained in a vacuum chamber that has a fixture for holding a semiconductor image sensor, a control mechanism for controlling the neutral ion beam via the raster mechanism, and a map of the semiconductor image sensor. The image sensor is placed on the fixture within the vacuum chamber and the neutral ion beam removes a predetermined amount of substrate from the backside of the sensor. The result is an image sensor than can be backside thinned at the molecular level.

Abstract: A method of manufacturing a semiconductor device which starts with a semiconductor wafer which is provided with a layer of semiconductor material lying on an insulating layer at a first side. Semiconductor elements and conductor tracks are formed on this first side of the semiconductor wafer. Then the semiconductor wafer is fastened with this first side to a support wafer, and material is removed from the semiconductor wafer from its other, second side until the insulating layer has been exposed. The method starts with a semiconductor wafer whose insulating layer is an insulating as well as a passivating layer. The semiconductor device must be provided with a usual passivating layer after its manufacture in order to protect it against moisture and other influences. In the method described here, such a passivating layer is present already before the manufacture of the semiconductor device starts.

Abstract: The present invention provides a method of forming an SOI substrate which causes no variation in thickness of SOI layers formed by polishing the silicon substrate, thereby causing no factor interfering with a reduction in thickness of the SOI layers.In the method of forming an SOI substrate, the surface of a silicon substrate which is form to have unevenness is covered with an insulator serving as a polishing stopper layer, and a polishing substrate is laminated on the insulator. The rear side of the silicon substrate is chemically polished with a polishing solution consisting of an alkali solution to leave as SOI layers the projection portions of the silicon substrate.

Abstract: A simple and low cost ULSI integrated heatsink more efficiently removes heat from a silicon package by integrating the heat sink material into the silicon die, transforming the present two-dimensional art into three dimensions. The fabrication of a high power integrated ULSI package and heatsink begins by fabricating an integrated circuit wafer up to the point of dicing the wafer into individual chips. The front side of the wafer is protected, while the backside of the wafer is exposed. The exposed backside is roughened by chemical and/or mechanical process. Optionally, a gettering process is then performed to remove impurities. The roughened backside is then coated with metal interlayers, preferably aluminum (Al) by chromium (Cr). A layer of copper (Cu) is optionally coated on the metal interlayers. A highly conductive reflowable material, such as solder or gold eutectic, is deposited on the metal interlayers. At this point, the wafer is diced to form chips.

Abstract: A method of manufacturing a device whereby a layer structure with semiconductor elements and conductor tracks is formed on a first side of a semiconductor wafer which is provided with a layer of semiconductor material disposed on an insulating layer. Then the semiconductor wafer is fastened with said first side to a support wafer by means of a glue layer, the support wafer being provided with a metallization. Material is then removed from the semiconductor wafer from the other, second side thereof until the insulating layer is exposed. Contact windows are provided in the insulating layer from the first side of the semiconductor wafer before the latter is refastened on the support wafer. These windows are filled with a material which can be removed selectively relative to the insulating layer. The contact windows are opened from the second side of the semiconductor wafer after the latter has been fastened on the support wafer and after the insulating layer has been exposed.

Abstract: A method for the formation of active devices upon and within exposed surfaces of both sides of a silicon wafer is presented. A dual-sided silicon wafer is provided having a first surface and an opposed second surface prepared similarly to achieve surfaces suitable for fabricating semiconductor devices. The method advantageously integrates the ability to preform wafer processing operations on both exposed surfaces separately or simultaneously. Wafer processing operations are layering, patterning, doping, and heat treatment. The processing sequence is complete when a doped region and a patterened interconnect line electrically coupled thereto (i.e., minimal integrated circuits) are formed upon and within both surfaces of the dual-sided silicon wafer. A wafer handling system and processing station for dual-sided silicon wafers are described. In addition, a technique of applying a protective layer over one surface of a dual-sided silicon wafer is also described.