Silicon Carbide Semiconductor Patents (Class 438/931)
  • Patent number: 9040345
    Abstract: A method of laser ablation for electrical contact to a buried electrically conducting layer in diamond comprising polishing a single crystal diamond substrate having a first carbon surface, implanting the diamond with a beam of 180 KeV followed by 150 KeV C+ ions at fluencies of 4×1015 ions/cm2 and 5×1015 ions/cm2 respectively, forming an electrically conducting carbon layer beneath the first carbon surface, and ablating the single crystal diamond which lies between the electrically conducting layer and the first carbon surface.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 26, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Bradford B. Pate, Matthew P. Ray, Jeffrey W. Baldwin
  • Patent number: 9018101
    Abstract: In a method for making graphitic ribbons in a face of a carbide crystal (110), in which an elongated trench (120) is formed along a predetermined path in the face (112) of the carbide crystal (110), the trench (120) including a horizontal floor (124) coupling two vertical walls (122), the trench (120) following a path on which it is desired to form a graphitic ribbon (130). The carbide crystal (110) and the trench (120) are subjected to an annealing environment for an amount of time sufficient to cause a graphene ribbon (130) having a V-shaped cross section to form along the predetermined path of the trench (120).
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: April 28, 2015
    Assignee: Georgia Tech Research Corporation
    Inventor: Walt A. De Heer
  • Patent number: 9012922
    Abstract: A substrate is provided with a main surface having an off angle of 5° or smaller relative to a reference plane. The reference plane is a {000-1} plane in the case of hexagonal system and is a {111} plane in the case of cubic system. A silicon carbide layer is epitaxially formed on the main surface of the substrate. The silicon carbide layer is provided with a trench having first and second side walls opposite to each other. Each of the first and second side walls includes a channel region. Further, each of the first and second side walls substantially includes one of a {0-33-8} plane and a {01-1-4} plane in the case of the hexagonal system and substantially includes a {100} plane in the case of the cubic system.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: April 21, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada
  • Patent number: 9006748
    Abstract: This semiconductor device includes a silicon carbide layer of a first conductivity type having first and second principal surfaces and including an element region and a terminal region surrounding the element region on the first principal surface. The silicon carbide layer includes a first dopant layer of the first conductivity type contacting with the first principal surface and a second dopant layer of the first conductivity type located closer to the second principal surface than the first dopant layer is. The terminal region has, in its surface portion with a predetermined depth under the first principal surface, a terminal structure including respective portions of the first and second dopant layers and a ring region of a second conductivity type running through the first dopant layer to reach the second dopant layer. The dopant concentration of the first dopant layer is twice to five times as high as that of the second dopant layer 22.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: April 14, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Koutarou Tanaka, Masao Uchida
  • Patent number: 8999854
    Abstract: On a substrate, a silicon carbide layer provided with a main surface is formed. A mask is formed to cover a portion of the main surface of the silicon carbide layer. The main surface of the silicon carbide layer on which the mask is formed is thermally etched using chlorine-based gas so as to provide the silicon carbide layer with a side surface inclined relative to the main surface. The step of thermally etching is performed in an atmosphere in which the chlorine-based gas has a partial pressure of 50% or smaller.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: April 7, 2015
    Assignees: Sumitomo Electric Industries, Ltd., National University Corporation Nara Institute of Science and Technology
    Inventors: Takeyoshi Masuda, Tomoaki Hatayama
  • Patent number: 8993424
    Abstract: Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Wen Liu, Tsung-Hsing Yu, Dhanyakumar Mahaveer Sathaiya, Wei-Hao Wu, Ken-Ichi Goto, Tzer-Min Shen, Zhiqiang Wu
  • Patent number: 8987124
    Abstract: A silicon carbide substrate having a main face is prepared. By applying thermal oxidation to the main face of the silicon carbide substrate at a first temperature, an oxide film is formed on the main face. After the oxide film is formed, heat treatment is applied to the silicon carbide substrate at a second temperature higher than the first temperature. An opening exposing a portion of the main face is formed at the oxide film. A Schottky electrode is formed on the main face exposed by the opening.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomihito Miyazaki, Toru Hiyoshi
  • Patent number: 8981384
    Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: March 17, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takeyoshi Masuda
  • Patent number: 8975642
    Abstract: Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Semiconductor Manufacturing International Corp
    Inventors: Neil Zhao, Mieno Fumitake
  • Patent number: 8969103
    Abstract: A silicon carbide substrate is made of silicon carbide. In the silicon carbide substrate, a normal line of one main surface of the silicon carbide substrate and a normal line of a {03-38} plane form an angle of 0.5° or smaller in an orthogonal projection to a plane including a <01-10> direction and a <0001> direction. In this way, there can be provided the silicon carbide substrate allowing for both improvement of channel mobility of a semiconductor device and stable characteristics thereof.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: March 3, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Makoto Sasaki, Shin Harada, Satomi Itoh, Kyoko Okita
  • Patent number: 8927396
    Abstract: An object of the present invention is to provide a production process of an epitaxial silicon carbide single crystal substrate having a high-quality silicon carbide single crystal thin film reduced in the surface defect and the like on a silicon carbide single crystal substrate with a small off-angle. According to the present invention, in the production process of an epitaxial silicon carbide single crystal substrate having a high-quality silicon carbide single crystal thin film reduced in the surface defect and the like on a silicon carbide single crystal substrate with an off-angle of 4° or less, pretreatment etching to a depth of 0.1 to 1 ?m is performed at a temperature of 1,550 to 1,650° C. by flowing a gas containing silicon and chlorine together with a hydrogen gas such that the silicon atom concentration becomes from 0.0001 to 0.01% based on hydrogen atoms in the hydrogen gas, and thereafter, an epitaxial layer is formed.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: January 6, 2015
    Assignee: Nippon Steel & Sumitomo Metal Corporation
    Inventors: Takashi Aigo, Hiroshi Tsuge, Masakazu Katsuno, Tatsuo Fujimoto, Hirokatsu Yashiro
  • Patent number: 8927368
    Abstract: A trench having a side wall and a bottom portion is formed in a silicon carbide substrate. A trench insulating film is formed to cover the bottom portion and the side wall. A silicon film is formed to fill the trench with the trench insulating film being interposed therebetween. The silicon film is etched so as to leave a portion of the silicon film that is disposed on the bottom portion with the trench insulating film being interposed therebetween. The trench insulating film is removed from the side wall. By oxidizing the silicon film, a bottom insulating film is formed. A side wall insulating film is formed on the side wall.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: January 6, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yu Saitoh, Takeyoshi Masuda, Hideki Hayashi
  • Patent number: 8889533
    Abstract: A method of manufacturing a semiconductor device by using a substrate processing apparatus comprises a reaction chamber configured to process a plurality of substrates stacked at predetermined intervals, wherein a first gas flow from a first gas supply inlet and a second gas flow from a second gas supply inlet are crossed with each other before these gas flows reach the substrates. The method of manufacturing a semiconductor device comprises: loading the plurality of substrates into the reaction chamber; supplying a silicon-containing gas and a chlorine-containing gas from the first gas supply inlet into the reaction chamber, supplying a carbon-containing gas and a reducing gas from the second gas supply inlet into the reaction chamber and supplying a dopant-containing gas into the reaction chamber from the first gas supply inlet or the second gas supply inlet; and unloading the substrates from the reaction chamber.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: November 18, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Takafumi Sasaki, Yoshinori Imai, Koei Kuribayashi, Sadao Nakashima
  • Patent number: 8866156
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a contact electrode. The silicon carbide substrate includes an n type region and a p type region that makes contact with the n type region. The contact electrode makes contact with the n type region and the p type region. The contact electrode contains Ni atoms and Si atoms. The number of the Ni atoms is not less than 87% and not more than 92% of the total number of the Ni atoms and the Si atoms. Accordingly, there can be provided a silicon carbide semiconductor device, which can achieve ohmic contact with an n type impurity region and can achieve a low contact resistance for a p type impurity region, as well as a method for manufacturing such a silicon carbide semiconductor device.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: October 21, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shunsuke Yamada, Hideto Tamaso
  • Patent number: 8859366
    Abstract: Methods of forming silicon carbide power devices are provided. An n? silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n? silicon carbide layer. A buried region of p+ silicon carbide is provided on the p-type silicon carbide well region. An n+ region of silicon carbide is provided on the buried region of p+ silicon carbide. A channel region of the power device is adjacent the buried region of p+ silicon carbide and the n+ region of silicon carbide. An n? region is provided on the channel region and a portion of the n? region is removed from the channel region so that a portion of the n? region remains on the channel region to provide a reduction in a surface roughness of the channel region.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: October 14, 2014
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Michael Laughner
  • Patent number: 8859420
    Abstract: A method of fabricating an interconnect element may include fabricating a metal layer that overlies a carrier layer and that includes a plurality of metal traces; providing a dielectric element to overlie the metal layer and the carrier layer; providing a plurality of metal posts; and removing the carrier layer to expose the first major surface of the dielectric element and the outer surfaces of the plurality of metal traces.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: October 14, 2014
    Assignee: Invensas Corporation
    Inventors: Kimitaka Endo, Norihito Masuda, Tomokazu Shimada
  • Patent number: 8853710
    Abstract: An optically active material is used to create power devices and circuits having significant performance advantages over conventional methods for affecting optical control of power electronics devices and circuits. A silicon-carbide optically active material is formed by compensating shallow donors with the boron related D-center. The resulting material can be n-type or p-type but it is distinguished from other materials by the ability to induce persistent photoconductivity in it when illuminated by electromagnetic radiation with a photon energy in excess of the threshold energy required to photoexcite electrons from the D-center to allowed states close to the conduction band edge, which varies from polytype to polytype.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: October 7, 2014
    Assignee: Power Integrations, Inc.
    Inventor: Michael S. Mazzola
  • Patent number: 8823014
    Abstract: A method of epitaxial growth of a material on a crystalline substrate includes selecting a substrate having a crystal plane that includes a plurality of terraces with step risers that join adjacent terraces. Each terrace of the plurality or terraces presents a lattice constant that substantially matches a lattice constant of the material, and each step riser presents a step height and offset that is consistent with portions of the material nucleating on adjacent terraces being in substantial crystalline match at the step riser. The method also includes preparing a substrate by exposing the crystal plane; and epitaxially growing the material on the substrate such that the portions of the material nucleating on adjacent terraces merge into a single crystal lattice without defects at the step risers.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: September 2, 2014
    Assignees: Kansas State University Research Foundation, State University of New York Stony Brook, The University of Bristol
    Inventors: James Edgar, Michael Dudley, Martin Kuball, Yi Zhang, Guan Wang, Hui Chen, Yu Zhang
  • Patent number: 8822315
    Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: September 2, 2014
    Assignee: Cree, Inc.
    Inventors: Davis Andrew McClure, Alexander Suvorov, John Adam Edmond, David Beardsley Slater, Jr.
  • Patent number: 8803252
    Abstract: A drift layer forms a first main surface of a silicon carbide layer and has a first conductivity type. A source region is provided to be spaced apart from the drift layer by a body region, forms a second main surface, and has the first conductivity type. A relaxing region is provided within the drift layer and has a distance Ld from the first main surface. The relaxing region has a second conductivity type and has an impurity dose amount Drx. The drift layer has an impurity concentration Nd between the first main surface and the relaxing region. Relation of Drx>Ld·Nd is satisfied. Thus, a silicon carbide semiconductor device having a high breakdown voltage is provided.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: August 12, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Toru Hiyoshi
  • Patent number: 8802552
    Abstract: A method for manufacturing a MOSFET includes the steps of: forming a gate oxide film on an active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode in ohmic contact with the active layer, and forming an interlayer insulating film made of silicon dioxide so as to cover the gate electrode after the source contact electrode is formed. The step of forming a source contact electrode includes the steps of forming a metal layer including aluminum so as to be in contact with the active layer, and alloying the metal layer.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: August 12, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Takeyoshi Masuda
  • Patent number: 8796123
    Abstract: An impurity of a first conductivity type is implanted onto a silicon carbide substrate through an opening in a mask layer. First and second films made of first and second materials respectively are formed. It is sensed that etching of the first material is performed during anisotropic etching, and then anisotropic etching is stopped. An impurity of a second conductivity type is implanted onto the silicon carbide substrate through the opening narrowed by the first and second films. Thus, the impurity regions can be formed in an accurately self-aligned manner.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 5, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shunsuke Yamada, Takeyoshi Masuda
  • Patent number: 8795624
    Abstract: Provided is a monocrystalline silicon carbide ingot containing a dopant element, wherein a maximum concentration of the dopant element is less than 5×1017 atoms/cm3 and the maximum concentration is 50 times or less than that of a minimum concentration of the dopant element. Also provided is a monocrystalline silicon carbide wafer made by cutting and polishing the monocrystalline silicon carbide ingot, wherein a electric resistivity at room temperature of the wafer is 5×103 ?cm or more. Further provided is a method for manufacturing the monocrystalline silicon carbide including growing the monocrystalline silicon carbide on a seed crystal from a sublimation material by a sublimation method. The sublimation material includes a solid material containing a dopant element, and the specific surface of the solid material containing the dopant element is 0.5 m2/g or less.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: August 5, 2014
    Assignee: Nippon Steel & Sumitomo Metal Corporation
    Inventors: Masashi Nakabayashi, Tatsuo Fujimoto, Mitsuru Sawamura, Noboru Ohtani
  • Patent number: 8785301
    Abstract: A method of cleaning a SiC semiconductor includes the steps of forming an oxide film at the surface of a SiC semiconductor, and removing the oxide film. At the step of forming an oxide film, an oxide film is formed using ozone water having a concentration greater than or equal to 30 ppm. The forming step preferably includes the step of heating at least one of the surface of the SiC semiconductor and the ozone water. Thus, there can be obtained a method of cleaning a SiC semiconductor that can exhibit cleaning effect on the SiC semiconductor.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: July 22, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Tomihito Miyazaki, Toru Hiyoshi, Satomi Itoh, Hiromu Shiomi
  • Patent number: 8772139
    Abstract: A method of manufacturing a MOSFET includes the steps of preparing a silicon carbide substrate, forming an active layer on the silicon carbide substrate, forming a gate oxide film on the active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode on the active layer, and forming a source interconnection on the source contact electrode. The step of forming the source interconnection includes the steps of forming a conductor film on the source contact electrode and processing the conductor film by etching the conductor film with reactive ion etching. Then, the method of manufacturing a MOSFET further includes the step of performing annealing of heating the silicon carbide substrate to a temperature not lower than 50° C. after the step of processing the conductor film.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: July 8, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Takeyoshi Masuda
  • Patent number: 8765617
    Abstract: A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon nitride on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including a nitrogen atom.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Inc.
    Inventor: Takeyoshi Masuda
  • Patent number: 8765523
    Abstract: A method for manufacturing a semiconductor device includes the steps of preparing a substrate made of silicon carbide and having an n type region formed to include a main surface, forming a p type region in a region including the main surface, forming an oxide film on the main surface across the n type region and the p type region, by heating the substrate having the p type region formed therein at a temperature of 1250° C. or more, removing the oxide film to expose at least a part of the main surface, and forming a Schottky electrode in contact with the main surface that has been exposed by removing the oxide film.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda
  • Patent number: 8753985
    Abstract: Molecular layer deposition of silicon carbide is described. A deposition precursor includes a precursor molecule which contains silicon, carbon and hydrogen. Exposure of a surface to the precursor molecule results in self-limited growth of a single layer. Though the growth is self-limited, the thickness deposited during each cycle of molecular layer deposition involves multiple “atomic” layers and so each cycle may deposit thicknesses greater than typically found during atomic layer depositions. Precursor effluents are removed from the substrate processing region and then the surface is irradiated before exposing the layer to the deposition precursor again.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 17, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Brian Underwood, Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 8748276
    Abstract: A through portion is formed on a semiconductor substrate. Into the semiconductor substrate, a first ion implantation is performed via the through portion. The through portion is at least partially removed in the thickness direction from a region of at least a portion of the through portion when viewed in a plan view. A second ion implantation is performed into the semiconductor substrate at the region of at least the portion thereof. An implantation energy for the first ion implantation is equal to an implantation energy for the second ion implantation.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: June 10, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hideki Hayashi
  • Patent number: 8685848
    Abstract: A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 1, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Matsuno, Yoichiro Tarui
  • Patent number: 8637360
    Abstract: Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: January 28, 2014
    Assignee: Intersil Americas Inc.
    Inventor: Francois Hebert
  • Patent number: 8604459
    Abstract: Electrical devices containing carbon nanotubes can be passivated to protect the carbon nanotubes from degradation while substantially preserving the carbon nanotubes' electrical conductivity and switching characteristics. Such electrical devices can include a first metal contact, a switching layer containing a plurality of carbon nanotubes disposed on the first metal contact, a passivation layer containing amorphous carbon, a metal carbide, or any combination thereof that is disposed on at least a top surface of the switching layer, and a second metal contact disposed upon the passivation layer. Methods for forming the electrical devices can include disposing a passivation layer containing amorphous carbon on at least a top surface of the switching layer, and optionally heating to at least partially convert the amorphous carbon within the passivation layer into a metal carbide.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: December 10, 2013
    Assignee: Lockheed Martin Corporation
    Inventors: Jonathan W. Ward, Garo J. Derderian
  • Patent number: 8586434
    Abstract: A method of manufacturing a semiconductor device may include forming a first n? type epitaxial layer by performing a first epitaxial growth on a first surface of an n+ type silicon carbide substrate, forming a photosensitive layer pattern on the first n? type epitaxial layer, etching the first n? type epitaxial layer by using the photosensitive layer pattern as a mask to form a first trench, forming a buffer layer on the first n? type epitaxial layer after the photosensitive layer pattern may be removed, etching the buffer layer to form a trench passivation layer in the first trench, forming an n? type epitaxial layer by performing a second epitaxial growth on the first n? type epitaxial layer, and forming a p type epitaxial layer by performing a third epitaxial growth on the n? type epitaxial layer other than the portion on which the trench passivation layer may be formed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 19, 2013
    Assignee: Hyundai Motor Company
    Inventors: Youngkyun Jung, Kyoung-Kook Hong, Jong Seok Lee, Dae Hwan Chun
  • Patent number: 8575625
    Abstract: A semiconductor element mounting member is arranged to infiltrate a matrix metal into a porous body that is formed by sintering diamond particles being in direct contact with each other and that has an infiltration auxiliary layer selectively formed only on the exposed surface of each diamond particle. A production method includes a step at which a mixture of diamond particles, a powder of a chemical element out of which the infiltration auxiliary layer is made, and an ammonium chloride powder is compressed and molded, is then heated to 900° C. or more, and is formed into the porous body. A semiconductor device has a semiconductor element mounted on an element mounting surface of the semiconductor element mounting member with a connecting layer therebetween.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: November 5, 2013
    Assignee: A.L.M.T. Corp.
    Inventors: Kouichi Takashima, Yoshifumi Aoi, Eiji Kamijo
  • Patent number: 8569106
    Abstract: A film of an epitaxial layer that allows the reduction in both the height of a bunching step and crystal defects caused by a failure in migration of reactive species on a terrace is formed on a SiC semiconductor substrate having an off angle of 5 degrees or less. A film of a first-layer epitaxial layer is formed on and in contact with a surface of the SiC semiconductor substrate having an off angle of 5 degrees or less. Subsequently, the temperature in a reactor is lowered. A second-layer epitaxial layer is caused to epitaxially grow on and in contact with a surface of the first-layer epitaxial layer. In the above-described manner, the epitaxial layer is structured with two layers, and the growth temperature for the second epitaxial layer is set lower than the growth temperature for the first epitaxial layer.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: October 29, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Hamano, Kenichi Ohtsuka, Nobuyuki Tomita, Masayoshi Tarutani
  • Patent number: 8569123
    Abstract: An object is to provide a method for manufacturing a silicon carbide semiconductor device in which a time required for removing a sacrificial oxide film can be shortened and damage to a surface of the silicon carbide layer can be reduced. The method for manufacturing a silicon carbide semiconductor device includes: (a) performing ion implantation to a silicon carbide layer; (b) performing activation annealing to the ion-implanted silicon carbide layer 2; (c) removing a surface layer of the silicon carbide layer 2, to which the activation annealing has been performed, by dry etching; (d) forming a sacrificial oxide film on a surface layer of the silicon carbide layer, to which the dry etching has been performed, by performing sacrificial oxidation thereto; and (e) removing the sacrificial oxide film by wet etching.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: October 29, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Matsuno, Kenichi Ohtsuka, Naoki Yutani, Kenichi Kuroda, Hiroshi Watanabe, Shozo Shikama
  • Patent number: 8563987
    Abstract: The semiconductor device 100 of this invention includes: a semiconductor layer 2 arranged on the principal surface of a substrate 1 and made of a wide bandgap semiconductor; a trench 5 which is arranged in the semiconductor layer 2 and which has a bottom and a side surface; an insulating region 11 arranged on the bottom and side surface of the trench 5; and a conductive layer 7 arranged in the trench 5 and insulated from the semiconductor layer 2 by the insulating region 11. The insulating region 11 includes a gate insulating film 6 arranged on the bottom and the side surface of the trench 5 and a gap 10 arranged between the gate insulating film 6 and the conductive layer 7 at the bottom of the trench 5. The gate insulating film 6 contacts with the conductive layer 7 on a portion of the side surface of the trench 5 but does not contact with the conductive layer 7 at the bottom of the trench 5.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: October 22, 2013
    Assignee: Panasonic Corporation
    Inventor: Haruyuki Sorada
  • Patent number: 8552435
    Abstract: Electronic device structures that compensate for non-uniform etching on a semiconductor wafer and methods of fabricating the same are disclosed. In one embodiment, the electronic device includes a number of layers including a semiconductor base layer of a first doping type formed of a desired semiconductor material, a semiconductor buffer layer on the base layer that is also formed of the desired semiconductor material, and one or more contact layers of a second doping type on the buffer layer. The one or more contact layers are etched to form a second contact region of the electronic device. The buffer layer reduces damage to the semiconductor base layer during fabrication of the electronic device. Preferably, a thickness of the semiconductor buffer layer is selected to compensate for over-etching due to non-uniform etching on a semiconductor wafer on which the electronic device is fabricated.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: October 8, 2013
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Anant Agarwal
  • Patent number: 8524552
    Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: September 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
  • Patent number: 8507922
    Abstract: Disclosed is a silicon carbide substrate which has less high frequency loss and excellent heat dissipating characteristics. The silicon carbide substrate (S) is provided with a first silicon carbide layer (1), which is composed of a polycrystalline silicon carbide, and a second silicon carbide layer (2), which is composed of polycrystalline silicon carbide formed on the surface of the first silicon carbide layer. The second silicon carbide layer (2) has a high-frequency loss smaller than that of the first silicon carbide layer (1), the first silicon carbide layer (1) has a thermal conductivity higher than that of the second silicon carbide layer (2), and on the surface side of the second silicon carbide layer (2), the high-frequency loss at a frequency of 20 GHz is 2 dB/mm or less, and the thermal conductivity is 200 W/mK or more.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: August 13, 2013
    Assignees: Mitsui Engineering & Shipbuilding Co., Ltd., Admap Inc.
    Inventors: Satoshi Kawamoto, Masaki Nakamura
  • Patent number: 8507978
    Abstract: An integrated structure includes a plurality of split-gate trench MOSFETs. A plurality of trenches is formed within the silicon carbide substrate composition, each trench is lined with a passivation layer, each trench being substantially filled with a first conductive region a second conductive region and an insulating material having a dielectric constant similar to a dielectric constant of the silicon carbide substrate composition. The first conductive region is separated from the passivation layer by the insulating material. The first and second conductive regions form gate regions for each trench MOSFET. The first conductive region is separated from the second conductive region by the passivation layer. A doped body region of a first conductivity type formed at an upper portion of the substrate composition and a doped source region of a second conductivity type formed inside the doped body region.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: August 13, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Madhur Bobde, Lingpeng Guan
  • Patent number: 8492773
    Abstract: Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: July 23, 2013
    Assignee: Intersil Americas Inc.
    Inventor: Francois Hebert
  • Patent number: 8470672
    Abstract: A method of manufacturing a semiconductor device includes forming a drift layer on a substrate; forming a base layer on the drift layer; forming a trench to penetrate the base layer and to reach the drift layer; rounding off a part of a shoulder corner and a part of a bottom corner of the trench; covering an inner wall of the trench with an organic film; implanting an impurity to a surface portion of the base layer; forming a source region by activating the implanted impurity; and removing the organic film after the source region is formed, in which the substrate, the drift layer, the base layer and the source region are made of silicon carbide, and the implanting and the activating of the impurity are performed under a condition that the trench is covered with the organic film.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: June 25, 2013
    Assignees: DENSO CORPORATION, Toyota Jidosha Kabushiki Kaisha
    Inventors: Takeshi Endo, Shinichiro Miyahara, Tomoo Morino, Masaki Konishi, Hirokazu Fujiwara, Jun Morimoto, Tsuyoshi Ishikawa, Takashi Katsuno, Yukihiko Watanabe
  • Patent number: 8470699
    Abstract: Disclosed is a method of manufacturing a silicon carbide semiconductor apparatus which provides a smooth silicon carbide surface while maintaining a high impurity activation ratio. The method of manufacturing a silicon carbide semiconductor apparatus which forms an impurity region in the surface layer of a silicon carbide substrate includes the steps of implanting an impurity into the surface layer of the silicon carbide substrate, forming a carbon film on the surface of the silicon carbide substrate, preliminarily heating the silicon carbide substrate with the carbon film as a protective film, and thermally activating the silicon carbide substrate with the carbon film as a protective film.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: June 25, 2013
    Assignee: Showa Denko K.K.
    Inventor: Kenji Suzuki
  • Patent number: 8470666
    Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: June 25, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8466017
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices are made using selective ion implantation using an implantation mask. The devices have implanted sidewalls formed by scattering of normal or near normal incident ions from the implantation mask. Vertical junction field-effect transistors with long channel length are also described. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: June 18, 2013
    Assignee: Power Integrations, Inc.
    Inventors: David C. Sheridan, Andrew Ritenour
  • Patent number: 8455328
    Abstract: An optically active material is used to create power devices and circuits having significant performance advantages over conventional methods for affecting optical control of power electronics devices and circuits. A silicon-carbide optically active material is formed by compensating shallow donors with the boron related D-center. The resulting material can be n-type or p-type but it is distinguished from other materials by the ability to induce persistent photoconductivity in it when illuminated by electromagnetic radiation with a photon energy in excess of the threshold energy required to photoexcite electrons from the D-center to allowed states close to the conduction band edge, which varies from polytype to polytype.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: June 4, 2013
    Assignee: Power Integrations, Inc.
    Inventor: Michael S. Mazzola
  • Patent number: 8450750
    Abstract: A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface with a trench having a sidewall formed of a crystal plane tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the sidewall of the trench. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the sidewall of the trench and the insulating film is not less than 1×1021 cm?3, and the semiconductor device has a channel direction in a range of ±10° relative to the direction orthogonal to the <?2110> direction in the sidewall of the trench. A method of manufacturing the silicon carbide semiconductor device is also provided.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: May 28, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Misako Honaga, Shin Harada
  • Patent number: 8440524
    Abstract: A method for manufacturing a semiconductor device including a semiconductor substrate composed of silicon carbide, an upper surface electrode which contacts an upper surface of the substrate, and a lower surface electrode which contacts a lower surface of the substrate, the method including steps of: (a) forming an upper surface structure on the upper surface side of the substrate, and (b) forming a lower surface structure on the lower surface side of the substrate. The step (a) comprises steps of: (a1) depositing an upper surface electrode material layer on the upper surface of the substrate, the upper surface electrode material layer being a raw material layer of the upper surface electrode, and (a2) annealing the upper surface electrode material layer.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: May 14, 2013
    Assignees: Toyota Jidosha Kabushiki Kaisha, Denso Corporation
    Inventors: Hirokazu Fujiwara, Masaki Konishi, Jun Kawai, Takeo Yamamoto, Takeshi Endo, Takashi Katsuno, Yukihiko Watanabe, Narumasa Soejima
  • Patent number: 8436366
    Abstract: A substrate achieving suppressed deterioration of processing accuracy of a semiconductor device due to bending of the substrate, a substrate with a thin film and a semiconductor device formed with the substrate above, and a method of manufacturing the semiconductor device above are obtained. A substrate according to the present invention has a main surface having a diameter of 2 inches or greater, a value for bow at the main surface being not smaller than ?40 ?m and not greater than ?5 ?m, and a value for warp at the main surface being not smaller than 5 ?m and not greater than 40 ?m. Preferably, a value for surface roughness Ra of the main surface of the substrate is not greater than 1 nm and a value for surface roughness Ra of a main surface is not greater than 100 nm.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: May 7, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Makoto Sasaki, Takeyoshi Masuda