Abstract: A semiconductor device according to the present invention includes a silicon carbide semiconductor substrate having a silicon carbide semiconductor layer; a p-type impurity region provided in the silicon carbide semiconductor layer and including a p-type impurity; a p-type ohmic electrode electrically connected to the p-type impurity region; an n-type impurity region provided in the silicon carbide semiconductor layer adjacent to the p-type impurity region, and including an n-type impurity; and an n-type ohmic electrode electrically connected to the n-type impurity region. The p-type ohmic electrode contains an alloy of nickel, aluminum, silicon and carbon, and the n-type ohmic electrode contains an alloy of titanium, silicon and carbon.

Abstract: The object is to provide a method for the fabrication of a semiconductor device having undergone an anneal treatment for the purpose of forming such ohmic contact as enables decrease of ohmic contact resistance and being provided on the (000-1) plane of silicon carbide with an insulating film and provide the semiconductor device. The method for the fabrication of a silicon carbide semiconductor device includes the steps of performing thermal oxidation on the (000-1) plane of a silicon carbide semiconductor in a gas containing at least oxygen and moisture, thereby forming an insulating film in such a manner as to contact the (000-1) plane of the silicon carbide semiconductor, removing part of the insulating film, thereby forming an opening part therein, depositing contact metal on at least part of the opening part, and performing a heat treatment, thereby forming a reaction layer of the contact metal and silicon carbide, wherein the heat treatment is implemented in a mixed gas of an inert gas and hydrogen.

Abstract: LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.

Abstract: A silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. A first conductive type impurity is diffused in the silicon carbide substrate. A method of producing a semiconductor device includes preparing the silicon carbide substrate forming a first conductive type impurity diffused region on the first main surface therein; preparing a silicon substrate having a third main surface and a fourth main surface opposite to the third main surface, said silicon substrate including a thermal oxidation film formed on the third main surface; and attaching the third main surface to the first main surface via the thermal oxidation film.

Abstract: Semiconductor devices and methods for making such devices are provided. One such method may include forming an epitaxial layer of single crystal SiC on a single crystal Si growth substrate, forming an epitaxial diamond layer on the layer of SiC, forming a Si layer on the diamond layer, bonding a SiO2 surface of a Si carrier substrate to the Si layer, and removing the Si growth substrate to expose the SiC layer. In yet another aspect, a semiconductor layer may be deposited onto the SiC layer. The semiconductor layer may further be deposited epitaxially.

Abstract: A method of fabricating a silicon carbide (SiC) layer is disclosed, which comprises steps: (S1) heating a silicon-based substrate at a temperature of X ° C.; (S2) carburizating the silicon-based substrate with a first hydrocarbon-containing gas at a temperature of Y ° C. to form a carbide layer on the silicon-based substrate; (S3) annealing the silicon-based substrate with the carbide layer thereon at a temperature of Z ° C.; and (S4) forming a silicon carbide layer on the carbide layer with a second hydrocarbon-containing gas and a silicon-containing gas at a temperature of W ° C.; wherein, X is 800 to 1200; Y is 1100 to 1400; Z is 1200 to 1500; W is 1300 to 1550; and X<Y?Z?W. In the method of the present invention, since no cooling steps between respective steps are required, the full process time can be reduced and the cost is lowered because no energy consumption occurs for the cooling and the re-heating steps.

Abstract: A method for manufacturing a silicon carbide semiconductor apparatus is disclosed. According to the method, an element structure is formed on a front surface side of a semiconductor substrate. A rear surface of the semiconductor substrate is grinded or polished in a direction parallel to a flat surface of a table. A front surface of the semiconductor substrate is grinded and polished in a direction parallel to the rear surface after the rear surface of the semiconductor substrate is grinded or polished.

Abstract: An epitaxial crystal for a field effect transistor which has a nitride-based III-V group semiconductor epitaxial crystal grown on a SiC single crystal base substrate having micropipes by use of an epitaxial growth method, wherein at least a part of the micropipes spreading from the SiC single crystal base substrate into the epitaxial crystal terminate between an active layer of the transistor and the SiC single crystal base substrate.

Abstract: In one aspect the present invention provides a method for manufacturing a silicon carbide semiconductor device. A layer of silicon dioxide is formed on a silicon carbide substrate and nitrogen is incorporated at the silicon dioxide/silicon carbide interface. In one embodiment, nitrogen is incorporated by annealing the semiconductor device in nitric oxide or nitrous oxide. In another embodiment, nitrogen is incorporated by annealing the semiconductor device in ammonia.

Abstract: The invention relates to a method for the treatment of a surface of a silicon carbide (SiC) substrate, said substrate being used in semiconductor manufacturing processes. The invention also relates to a SiC substrate for use in semiconductor manufacturing processes treated with the method according to the invention. According to the invention, said method comprising the steps of selective etching the surface of said SiC substrate using a reactive gas mixture, thereby creating a carbon surface layer on said substrate, and removing said carbon surface layer being created on said substrate. Thus, with the method steps according to the invention, SiC substrates can be obtained with a surface structure that complies with the highest standards as regard to dimensions and purity as required in semiconductor manufacturing processes.

Abstract: The present invention relates to alternative methods for the production of crystalline silicon compounds and/or alloys such as silicon carbide layers and substrates.

Abstract: A silicon carbide semiconductor device includes a substrate and a junction field effect transistor. The transistor includes: a first semiconductor layer disposed on the substrate; a first gate layer disposed on a surface of the first semiconductor layer; a first channel layer adjacent to the first gate layer on the substrate; a first source layer connecting to the first channel layer electrically; a second gate layer adjacent to the first channel layer to sandwich the first channel layer; a second channel layer adjacent to the second gate layer to sandwich the second gate layer; a third gate layer adjacent to the second channel layer to sandwich the second channel layer; and a second source layer connecting to the second channel layer electrically.

Abstract: Methods are provided for forming a structure that includes an air gap. In one embodiment, a method is provided for forming a damascene structure comprises depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and a porogen-providing precursor, depositing a porogen-containing material, and removing at least a portion of the porogen-containing material, depositing an organic layer on the porous low dielectric constant layer by reacting the porogen-providing precursor, forming a feature definition in the organic layer and the porous low dielectric constant layer, filing the feature definition with a conductive material therein, depositing a mask layer on the organic layer and the conductive material disposed in the feature definition, forming apertures in the mask layer to expose the organic layer, removing a portion or all of the organic layer through the apertures, and forming an air gap adjacent the conductive material.

Abstract: A structure is disclosed that reduces the forward voltage across the interface between silicon carbide and Group III nitride layers. The structure includes a conductive silicon carbide substrate and a conductive layer of aluminum gallium nitride on the silicon carbide substrate. The aluminum gallium nitride layer has a mole fraction of aluminum that is sufficient to bring the conduction bands of the silicon carbide substrate and the aluminum gallium nitride into close proximity, but less than a mole fraction of aluminum that would render the aluminum gallium nitride layer resistive.

Abstract: A method of manufacturing an SiC single crystal wafer according to the present invention includes the steps of: (a) preparing an SiC single crystal wafer 10 with a mirror-polished surface; (b) oxidizing the surface of the SiC single crystal wafer 10 with plasma, thereby forming an oxide layer 12 on the surface of the SiC single crystal wafer; and (c) removing at least a portion of the oxide layer 12 by a reactive ion etching process. Preferably, the surface of the wafer is planarized by repeatedly performing the steps (b) and (c) a number of times.

Abstract: Provided is a silicon carbide epitaxial wafer which is formed on a substrate that is less than 1° off from the {0001} surface of silicon carbide having an ?-type crystal structure, wherein the crystal defects in the SiC epitaxial wafer are reduced while the flatness of the surface thereof is improved.

Abstract: A fingerprint detection device has a fingerprint sensor chip and a diamond-like carbon (DLC) film covering the outermost surface of the sensor chip. The DLC film provides sufficient strength and enhanced electrostatic discharge withstand voltage to the fingerprint sensor chip. Thus, the DLC film protects the fingerprint sensor chip without any conventional protective cover. The DLC film is less scratchable and less stainable. Since the fingerprint detection device has no protective cover, the device can be provided in a thin and compact form. In addition, the device has high reliability.

Abstract: A Schottky barrier silicon carbide device has a Re Schottky metal contact. The Re contact 27 is thicker than 250 Angstroms and may be between 2000 and 4000 Angstroms. A termination structure is provided by ion milling an annular region around the Schottky contact.

Abstract: In a semiconductor device having SiC vertical trench MOSFETs, it is aimed to prevent the generation of large scattering in the channel resistance without largely increasing the average value of channel resistance. A 4H-SiC substrate having a major face thereof that is generally a {0001} face and having an off angle ?. The trench is formed with the standard deviation ? in scattering of the angle formed by a trench side wall face and a substrate major face within a wafer face. By setting the designed value of the angle formed by the trench side wall face and the substrate major face at an any angle ranging from [(60 degrees)+2?] to [(90 degrees)?tan?1 (0.87×tan ?)?2?] in forming the trench in the SiC substrate, a semiconductor device in which the angle formed by the trench side wall face and the substrate major face is 60 degrees or more but not more than [(90 degrees)?tan?1 (0.87×tan ?)] can be obtained.

Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.

Abstract: Methods of forming a silicon carbide semiconductor device are disclosed. The methods include forming a semiconductor device at a first surface of a silicon carbide substrate having a first thickness, and mounting a carrier substrate to the first surface of the silicon carbide substrate. The carrier substrate provides mechanical support to the silicon carbide substrate. The methods further include thinning the silicon carbide substrate to a thickness less the first thickness, forming a metal layer on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate, and locally annealing the metal layer to form an ohmic contact on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate. The silicon carbide substrate is singulated to provide a singulated semiconductor device.

Abstract: Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500 ° C. to about 1300 ° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.

Abstract: A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity ion in the SiC layer; forming a carbon layer on the SiC layer; heating the SiC layer for activating the implanted impurity in the SiC layer covered with the carbon layer; and removing the carbon layer from the SiC layer. The forming the carbon layer includes: coating a resist on the SiC layer; and heating the resist for evaporating organic matter in the resist so that the resist is carbonized. The forming the oxide film is performed after the removing the carbon layer.

Abstract: There are provided preflow periods t11, t12 in which group III element materials TMG, TMA and TMI are not supplied from a group III element material container to a reaction region (reactor), while a group V element material PH3 and an Mg dopant material are supplied from a group V element material container and a dopant material container to the reaction region (reactor) after an Mg-undoped group III-V compound semiconductor layer is crystallinically grown and before an Mg-doped group III-V compound semiconductor layer is crystallinically grown. According to the semiconductor manufacturing method, an Mg doping profile can be accurately controlled.

Abstract: Methods of forming a silicon carbide semiconductor device are disclosed. The methods include forming a semiconductor device at a first surface of a silicon carbide substrate having a first thickness, and mounting a carrier substrate to the first surface of the silicon carbide substrate. The carrier substrate provides mechanical support to the silicon carbide substrate. The methods further include thinning the silicon carbide substrate to a thickness less the first thickness, forming a metal layer on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate, and locally annealing the metal layer to form an ohmic contact on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate. The silicon carbide substrate is singulated to provide a singulated semiconductor device.

Abstract: An aluminum gallium nitride/gallium nitride layer (III-V nitride semiconductor layer) is formed on the surface of a silicone carbide substrate. The aluminum gallium nitride/gallium nitride layer is dry-etched from an exposed surface, using a chlorine-based gas (first gas) and a surface via hole is thereby formed. A back via hole, which is to be connected to the surface via hole, is formed by dry-etching the silicon carbide substrate from an exposed back side using a fluorine-based gas (second gas).

Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate having a silicon carbide substrate, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; a trench penetrating the second and the third semiconductor layers to reach the first semiconductor layer; a channel layer on a sidewall and a bottom of the trench; an oxide film on the channel layer; a gate electrode on the oxide film; a first electrode connecting to the third semiconductor layer; and a second electrode connecting to the silicon carbide substrate. A position of a boundary between the first semiconductor layer and the second semiconductor layer is disposed lower than an utmost lowest position of the oxide film.

Abstract: A dual damascene structure comprising a composite barrier/etch stop layer including a lower silicon carbide (SiC) layer and an upper first oxygen doped SiC layer formed over a substrate is provided. A first dielectric layer is formed over the first oxygen doped SiC layer followed by a second oxygen doped SiC etch stop layer, and a second dielectric layer. An opening with a via and an overlying trench extends through the second dielectric layer, the second oxygen doped SiC etch stop layer, the first dielectric layer, the upper first oxygen doped SiC layer and at least a portion of the lower silicon carbide (SiC) layer. The opening is filled with a diffusion barrier layer and a metal layer.

Abstract: A method for producing, on an SiC substrate, SiC homoepitaxial layers of the same polytype as the substrate. The layers are grown on a surface of the SiC substrate, wherein the surface is inclined relative to the (0001) basal plane at an angle higher than 0.1 degree but less than 1 degree. An homoepitaxial growth is started by forming a boundary layer with a thickness up to 1 ?m.

Abstract: A semiconductor device having improved adhesiveness between films composing an interlayer insulating film is presented by providing multilayered films in the interlayer insulating films having film density distribution, in which the film density is gradually changes. A SiOC film is deposited to a thickness of 300 nm via a plasma CVD process, in which a flow rate of trimethylsilane gas is stepwise increased. In this case, the film density of the deposited SiOC film is gradually decreased by stepwise increasing the flow rate of trimethylsilane gas. Since trimethylsilane contains methyl group, trimethylsilane has more bulky molecular structure in comparison with monosilane or the like. Thus, the film density is decreased by increasing the amount of trimethylsilane in the reactant gas.

Abstract: Methods of forming silicon carbide power devices are provided. An n? silicon carbide layer is provided on a silicon carbide substrate. A p-type silicon carbide well region is provided on the n? silicon carbide layer. A buried region of p+ silicon carbide is provided on the p-type silicon carbide well region. An n+ region of silicon carbide is provided on the buried region of p+ silicon carbide. A channel region of the power device is adjacent the buried region of p+ silicon carbide and the n+ region of silicon carbide. An n? region is provided on the channel region and a portion of the n? region is removed from the channel region so that a portion of the n? region remains on the channel region to provide a reduction in a surface roughness of the channel region.

Abstract: An accumulation-mode MISFET comprises: a high-resistance SiC layer 102 epitaxially grown on a SiC substrate 101; a well region 103; an accumulation channel layer 104 having a multiple ?-doped layer formed on the surface region of the well region 103; a contact region 105; a gate insulating film 108; and a gate electrode 110. The accumulation channel layer 104 has a structure in which undoped layers 104b and ?-doped layers 104a allowing spreading movement of carriers to the undoped layers 104b under a quantum effect are alternately stacked. A source electrode 111 is provided which enters into the accumulation channel layer 104 and the contact region 105 to come into direct contact with the contact region 105. It becomes unnecessary that a source region is formed by ion implantation, leading to reduction in fabrication cost.

Abstract: Methods of depositing a dielectric layer in a gap formed on a substrate are described. The methods include introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber. The organo-silicon precursor has a C:Si atom ratio of less than 8, and the oxygen precursor comprises atomic oxygen that is generated outside the deposition chamber. The precursors are reacted to form the dielectric layer in the gap. Methods of filling gaps with dielectric materials are also described. These methods include providing an organo-silicon precursor having a C:Si atom ratio of less than 8 and an oxygen precursor, and generating a plasma from the precursors to deposit a first portion of the dielectric material in the gap. The dielectric material may be etched, and a second portion of dielectric material may be formed in the gap. The first and second portions of the dielectric material may be annealed.

Abstract: Doped silicon carbide structures, as well as methods associated with the same, are provided. The structures, for example, are components (e.g., layer, patterned structure) in MEMS structures. The doped silicon carbide structures may be highly conductive, thus, providing low resistance to electrical current. An in-situ doping process may be used to form the structures. The process parameters can be selected so that the structures have a low residual stress and/or low strain gradient. Thus, the structures may be formed having desired dimensions with little (or no) distortion arising from residual stress and/or strain gradient. The high conductivity and mechanical integrity of the structures are significant advantages in MEMS devices such as sensors and actuators.

Abstract: Fabrication of a light emitting device includes etching of a substrate of the light emitting device. The etch may be an aqueous etch sufficient to increase an amount of light extracted through the substrate. The etch may be a direct aqueous etch of a silicon carbide substrate. The etch may remove damage from the substrate that results from other processing of the substrate, such as damage from sawing the substrate. The etch may remove an amorphous region of silicon carbide in the substrate.

Abstract: A uniform silicon carbide single crystal with either an n-type or a p-type conductivity. The crystal has a net carrier concentration less than 1015 cm?3 and a carrier lifetime of at least 50 ns at room temperature.

Abstract: A method is disclosed for fabricating a silicon nitride regions in silicon carbide. The method includes the steps of implanting a sufficient dose and energy of nitrogen ions into a silicon carbide substrate maintained at a temperature above about 350° C. to produce an as-implanted layer of a silicon nitride composition in the silicon carbide, and annealing the as-implanted layer to form a silicon nitride composition. In some embodiments, the formed region of silicon nitride provides an insulating layer. In some embodiments, the silicon nitride region is buried under a surface layer of silicon carbide. Methods of separating silicon carbide by implantation and lift-off are additionally disclosed.

Abstract: The present invention provides a SiC material, formed according to certain process regimes, useful as a barrier layer, etch stop, and/or an ARC, in multiple levels, including the pre-metal dielectric (PMD) level, in IC applications and provides a dielectric layer deposited in situ with the SiC material for the barrier layers, and etch stops, and ARCs. The dielectric layer can be deposited with different precursors as the SiC material, but preferably with the same or similar precursors as the SiC material. The present invention is particularly useful for ICs using high diffusion copper as a conductive material. The invention may also utilize a plasma containing a reducing agent, such as ammonia, to reduce any oxides that may occur, particularly on metal surfaces such as copper filled features.

Abstract: A silicon carbide semi-insulating epitaxy layer is used to create power devices and integrated circuits having significant performance advantages over conventional devices. A silicon carbide semi-insulating layer is formed on a substrate, such as a conducting substrate, and one or more semiconducting devices are formed on the silicon carbide semi-insulating layer. The silicon carbide semi-insulating layer, which includes, for example, 4H or 6H silicon carbide, is formed using a compensating material, the compensating material being selected depending on preferred characteristics for the semi-insulating layer. The compensating material includes, for example, boron, vanadium, chromium, or germanium. Use of a silicon carbide semi-insulating layer provides insulating advantages and improved thermal performance for high power and high frequency semiconductor applications.

Abstract: Stress is exerted to the SiC crystal in the region, in which the carriers of a SiC semiconductor device flow, to change the crystal lattice intervals of the SiC crystal. Since the degeneration of the conduction bands in the bottoms thereof is dissolved, since the inter-band scattering is prevented from causing, and since the effective electron mass is reduced due to the crystal lattice interval change, the carrier mobility in the SiC crystal is improved, the resistance of the SiC crystal is reduced and, therefore, the on-resistance of the SiC semiconductor device is reduced.

Abstract: Epitaxial silicon carbide layers are fabricated by forming features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. The epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes features therein.

Abstract: Silicon carbide semiconductor devices and methods of fabricating silicon carbide semiconductor devices are provided by successively etching a mask layer to provide windows for formation of a source region of a first conductivity type, a buried silicon carbide region of a second conductivity type opposite to the first conductivity type and a second conductivity type well region in a first conductivity type silicon carbide layer. The source region and the buried silicon carbide region are formed utilizing a first window of the mask layer. Then, the well region is formed utilizing a second window of the mask layer, the second window being provided by a subsequent etch of the mask layer having the first window.

Abstract: A structure for use in a static induction transistor includes a semiconductor body having first and second semiconductor layers on a substrate, with the second layer having a dopant concentration of around an order of magnitude higher than the dopant concentration of the first layer. A plurality of sources are located on the second layer. A plurality of gates are ion implanted in the second layer, an end one of the gates being connected to all of the plurality of gates and constituting a gate bus. The gate bus has an extension connecting the gate bus in the second layer of higher dopant concentration to the first layer of lower dopant concentration. The extension is ion implanted in either a series of steps or a sloping surface which is formed in the first and second layers.

Abstract: A semiconductor device having small electrical contacts to impurity doped regions and a method for fabrication of such a device are provided. In accordance with one embodiment of the invention the semiconductor device comprises a semiconductor substrate having a doped region formed therein. The doped region has a nucleating layer comprising nickel on its surface, and a nanowire structure comprising silicon and carbon electrically contacts the nucleating layer.

Abstract: A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and growing a second epitaxial layer on the boron implanted region of the substrate or on the boron implanted region of the first epitaxial layer to form a semi-insulating epitaxial layer.

Abstract: Copper diffusion barrier films having low dielectric constants are suitable for a variety of copper/inter-metal dielectric integration schemes. Copper diffusion barrier films in accordance with the invention are composed of one or more layers of silicon carbide, at least one of the silicon carbide layers having a composition of at least 40% carbon (C), for example, between about 45 and 60% carbon (C). The films' high carbon-content layer will have a composition wherein the ratio of C to Si is greater than 2:1; or >3:1; or >4:1; or >5.1. The high carbon-content copper diffusion barrier films have a reduced effective k relative to conventional barrier materials.

Abstract: A method is disclosed for preparing a substrate and epilayer for reducing stacking fault nucleation and reducing forward voltage (Vf) drift in silicon carbide-based bipolar devices. The method includes the steps of etching the surface of a silicon carbide substrate with a nonselective etch to remove both surface and subsurface damage, thereafter etching the same surface with a selective etch to thereby develop etch-generated structures from at least any basal plane dislocation reaching the substrate surface that will thereafter tend to either terminate or propagate as threading defects during subsequent epilayer growth on the substrate surface, and thereafter growing a first epitaxial layer of silicon carbide on the twice-etched surface.

Abstract: A method of forming a layer of silicon carbide wherein silicon clusters are dissociated in a gas phase. Silicon clusters may be dissociated by a silicon-etching gas such as a group VII-containing component. A semiconductor device is also disclosed having a layer formed by the methods of the invention.

Abstract: A silicon carbide-based device contact and contact fabrication method employ a layer of poly-silicon on a SiC substrate, with the contact's metal layer deposited on top of the poly-silicon. Both Schottky and ohmic contacts can be formed. The poly-silicon layer can be continuous or patterned, and can be undoped or doped to be n-type or p-type. The present contact and method provide excellent contact adhesion, and can be employed with a number of different device types, to provide electrical contacts for Schottky diodes, pn diodes, and transistors, for example.

Abstract: In one aspect the present invention provides a method for manufacturing a silicon carbide semiconductor device. A layer of silicon dioxide is formed on a silicon carbide substrate and nitrogen is incorporated at the silicon dioxide/silicon carbide interface. In one embodiment, nitrogen is incorporated by annealing the semiconductor device in nitric oxide or nitrous oxide. In another embodiment, nitrogen is incorporated by annealing the semiconductor device in ammonia. In another aspect, the present invention provides a silicon carbide semiconductor device that has a 4H-silicon carbide substrate, a layer of silicon dioxide disposed on the 4H-silicon carbide substrate and a region of substantial nitrogen concentration at the silicon dioxide/silicon carbide interface.