Germanium Or Silicon Or Ge-si On Iii-v Patents (Class 438/933)
  • Patent number: 9136119
    Abstract: Disclosed are a non-polar hetero substrate, a method for manufacturing the same, and a nitride-based light emitting device using the same. The non-polar hetero substrate includes a non-polar base substrate, a nitride base layer disposed on the substrate, a defect reduction layer disposed on the nitride base layer, the defect reduction layer including a plurality of air gaps, and a nitride semiconductor layer disposed on the defect reduction layer.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: September 15, 2015
    Assignee: LG ELECTRONICS INC.
    Inventors: Sukkoo Jung, Younghak Chang, Hyunggu Kim, Kyuhyun Bang
  • Patent number: 8962400
    Abstract: A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor. Arsenic is in-situ doped during the step of epitaxially growing the silicon-containing semiconductor region.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji-Yin Tsai, Yao-Tsung Huang, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8936951
    Abstract: Provided are a semiconductor laser and a method of manufacturing the same. The method includes: providing a substrate including a buried oxide layer; forming patterns, which includes an opening part to expose the substrate, by etching the buried oxide layer; forming a germanium single crystal layer in the opening part; and forming an optical coupler, which is adjacent to the germanium single crystal layer, on the substrate.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: January 20, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: In Gyoo Kim, Gyungock Kim, Sang Hoon Kim, Ki Seok Jang, JiHo Joo
  • Patent number: 8927963
    Abstract: A semiconductor memory cell, a semiconductor memory device, and a method for manufacturing the same are disclosed. The semiconductor memory cell may comprise: a substrate; a channel region on the substrate; a gate region above the channel region; a source region and a drain region on the substrate and at opposite sides of the channel region; and a buried layer, which is disposed between the substrate and the channel region and comprises a material having a forbidden band narrower than that of a material for the channel region material. The buried layer material has a forbidden band narrower than that of the channel region material, so that a hole barrier is formed in the buried layer. Due to the barrier, it is difficult for holes stored in the buried layer to leak out, resulting in an improved information holding duration of the memory cell utilizing the floating-body effect.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: January 6, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zongliang Huo, Ming Liu
  • Patent number: 8895395
    Abstract: A method for forming a fin field-effect transistor (FinFET) device, comprises forming a plurality of silicon fins on a substrate, depositing silicon germanium (SiGe) on the plurality of fins, forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe, removing the SiGe from an area of the fins not covered by the dummy gate stack, forming a merged region in the area of the fins not covered by the dummy gate stack to form a source drain region, removing the dummy gate stack to expose the remaining SiGe in the gate region, mixing the SiGe with the silicon fins in the gate region to form SiGe fins, and depositing a gate dielectric and gate metal on the SiGe fins.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek
  • Patent number: 8883578
    Abstract: Various embodiments form silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is obtained. The semiconductor wafer comprises a substrate, a dielectric layer, and a semiconductor layer including silicon germanium (SiGe). At least one SiGe fin is formed from at least a first SiGe region of the semiconductor layer in at least one PFET region of the semiconductor wafer. Strained silicon is epitaxially grown on at least a second SiGe region of the semiconductor layer. At least one strained silicon fin is formed from the strained silicon in at least one NFET region of the semiconductor wafer.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: November 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Chun-chen Yeh, Tenko Yamashita
  • Patent number: 8871615
    Abstract: According to one embodiment, a method includes forming a first SiGe layer having a first profile of a concentration of Ge on a semiconductor substrate, forming a second SiGe layer having a second profile of a concentration of Ge on the first SiGe layer, the second profile lower than a first peak of the first profile, forming a mask layer on the second SiGe layer, etching the first and second SiGe layers by anisotropic etching using the mask layer as a mask to form trenches, selectively removing the first SiGe layer exposed into the trenches to form a cavity under the second SiGe layer, and oxidizing side and lower surfaces of the second SiGe layer exposed in the trenches and the cavity to increase the concentration of Ge in the second SiGe layer.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinji Mori
  • Patent number: 8865556
    Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph S. Newbury, Kenneth Parker Rodbell, Zhen Zhang, Yu Zhu
  • Patent number: 8841178
    Abstract: Various embodiments form silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is obtained. The semiconductor wafer comprises a substrate, a dielectric layer, and a semiconductor layer including silicon germanium (SiGe). At least one SiGe fin is formed from at least a first SiGe region of the semiconductor layer in at least one PFET region of the semiconductor wafer. Strained silicon is epitaxially grown on at least a second SiGe region of the semiconductor layer. At least one strained silicon fin is formed from the strained silicon in at least one NFET region of the semiconductor wafer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Chun-chen Yeh, Tenko Yamashita
  • Patent number: 8796081
    Abstract: A semiconductor structure is provided, comprising: a Si substrate; a porous structure layer formed on the Si substrate, in which the porous structure layer has a flat surface and comprises a Si1-xGex layer with low Ge content; and a Ge-containing layer formed on the porous structure layer, in which the Ge containing layer comprises a Ge layer or a Si1-yGey layer with high Ge content and x?y. Further, a method for forming the semiconductor structure is also provided.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: August 5, 2014
    Assignee: Tsinghua University
    Inventors: Jing Wang, Jun Xu, Lei Guo
  • Patent number: 8748269
    Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: June 10, 2014
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Robert S. Chau, Matthew V. Metz
  • Patent number: 8741773
    Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Asa Frye, Andrew Simon
  • Patent number: 8609518
    Abstract: A method of forming an n-type metal-oxide-semiconductor (NMOS) field-effect transistor (FET) includes forming a silicon germanium layer, and forming a silicon layer over the silicon germanium layer. A gate stack is formed over the silicon layer. The silicon layer is recessed to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor, wherein the silicon-containing semiconductor region forms a source/drain region the NMOS FET.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Chih-Hsin Ko, Yao-Tsung Huang, Cheng-Ying Huang
  • Patent number: 8536621
    Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: September 17, 2013
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Robert S. Chau, Matthew V. Metz
  • Patent number: 8502284
    Abstract: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in a first direction parallel to the surface of the silicon substrate, and stressor films formed on the silicon substrate between the channel region and the buried semiconductor regions in contact with the silicon substrate, for applying to the silicon substrate a second stress in a second direction which is opposite to the first direction.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: August 6, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8399878
    Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silica particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: March 19, 2013
    Assignee: NanoGram Corporation
    Inventors: Henry Hieslmair, Shivkumar Chiruvolu, Hui Du
  • Patent number: 8373058
    Abstract: The present invention provides a solar cell whose external color can be adjusted so that redness is suppressed. In the case where a photoelectric conversion layer contains amorphous silicon, an optical absorption layer is provided between the photoelectric conversion layer and a reflecting electrode layer. The optical absorption layer has a light absorbing property mainly in a long wavelength range, while the photoelectric conversion layer (amorphous silicon) has a selective light absorbing property mainly in a short/medium wavelength range. Incident light (solar light) passed through the photoelectric conversion layer further passes through the optical absorption layer and, after that, is reflected by the reflecting electrode layer. That is, remaining light of the incident light absorbed by the optical absorption layer and the photoelectric conversion layer is reflected by the reflecting electrode layer.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: February 12, 2013
    Assignees: TDK Corporation, Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisao Morooka, Takeshi Echizenya, Hirokazu Fujioka, Saki Takahashi, Kazuo Nishi
  • Patent number: 8278686
    Abstract: A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: October 2, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James Pan, Qi Wang
  • Patent number: 8263423
    Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silican particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: September 11, 2012
    Assignee: NanoGram Corporation
    Inventors: Henry Hieslmair, Shivkumar Chiruvolu, Hui Du
  • Patent number: 8258543
    Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: September 4, 2012
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Robert S. Chau, Matthew V. Metz
  • Patent number: 8247283
    Abstract: A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: August 21, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8247284
    Abstract: A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: August 21, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8232581
    Abstract: Manufacturing an III-V engineered substrate involves providing a base substrate comprising an upper layer made of a first III-V compound with a <110> or a <111> crystal orientation, forming an intermediate layer comprising at least a buffer layer of a second III-V compound, wherein the intermediate layer is overlying and in contact with the upper layer of the base substrate. Then a pseudomorphic passivation layer made of a group IV semiconductor material is grown so as to be overlying and in contact with the intermediate layer. This can enable an unpinned interface. The substrate surface can be smoother, implying fewer problems from surface stress. It can be used in electronic devices such as metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), tunneling field effect transistors (TFETs), and optoelectronic devices.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: July 31, 2012
    Assignee: IMEC
    Inventors: Geoffrey Pourtois, Clement Merckling, Guy Brammertz, Matty Caymax
  • Patent number: 8232191
    Abstract: A method of manufacturing a semiconductor device including forming a gate insulating film and a gate electrode over a Si substrate; forming a recess in the Si substrate at both sides of the gate electrode; forming a first Si layer including Ge in the recess; forming an interlayer over the first Si layer; forming a second Si layer including Ge over the interlayer; wherein the interlayer is composed of Si or Si including Ge, and a Ge concentration of the interlayer is less than a Ge concentration of the first Si layer and a Ge concentration of the second Si layer.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: July 31, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masahiro Fukuda, Yosuke Shimamune
  • Patent number: 8222657
    Abstract: A light emitting apparatus may include a gate metal positioned between a p-type contact and an n-type contact, a gate oxide or other dielectric stack positioned below and attached to the gate metal, a Ge or Si1-zGez channel positioned below and attached to the gate dielectric stack, a buffer, and a silicon substrate positioned below and attached to the buffer. The light emitting apparatus may alternatively include a gate metal positioned between a p-type contact and an n-type contact, a wide bandgap semiconductor positioned below and attached to the gate metal, a Ge or Si1-zGez channel positioned below and attached to the wide bandgap semiconductor, a buffer, and a silicon substrate positioned below and attached to the buffer. Embodiments of the light emitting apparatus may be configured for use in current-injected on-chip lasers, light emitting diodes or other light emitting devices.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: July 17, 2012
    Assignee: The Penn State Research Foundation
    Inventors: Jian Xu, Somasundaram Ashok
  • Patent number: 8207523
    Abstract: A method of fabrication of a metal oxide semiconductor field effect transistor is disclosed. At first, a substrate on which a gate structure is formed is provided. Afterward, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a plurality of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: June 26, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Chen-Hua Tsai, Bang-Chiang Lan, Yu-Hsin Lin, Yi-Cheng Liu, Cheng-Tzung Tsai
  • Patent number: 8120060
    Abstract: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure also includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based electronic device comprising an element including at least a portion of the monocrystalline silicon layer.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: February 21, 2012
    Assignee: Massachusetts Institute of Technology
    Inventor: Eugene A. Fitzgerald
  • Patent number: 8093143
    Abstract: A method for producing a wafer with a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side, the method using steps in the following order: simultaneously polishing the front and the back side of the silicon single crystal substrate; depositing a stress compensating layer on the back side of the silicon single crystal substrate; polishing the front side of the silicon single crystal substrate; cleaning the silicon single crystal substrate having the stress compensating layer deposited on the back side; and depositing a fully or partially relaxed layer of SiGe on the front side of the silicon single crystal substrate.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: January 10, 2012
    Assignee: Siltronic AG
    Inventors: Peter Storck, Thomas Buschhardt
  • Patent number: 8071435
    Abstract: A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: December 6, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8063413
    Abstract: A semiconductor structure is provided. The semiconductor structure includes one or more III-IV material-based semiconductor layers. A tensile-strained Ge layer is formed on the one or more a III-IV material-based semiconductor layers. The tensile-strained Ge layer is produced through lattice-mismatched heteroepitaxy on the one or more a III-IV material-based semiconductor layers.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: November 22, 2011
    Assignee: Massachusetts Institute of Technology
    Inventors: Yu Bai, Minjoo L. Lee, Eugene A. Fitzgerald
  • Patent number: 8043980
    Abstract: The invention provides compounds of, and methods for the preparation of compounds of, the molecular formula, SixGeyHz—aXa; wherein X is halogen, and x, y, z, and a are defined herein, and methods for the deposition of high-Ge content Si films on silicon substrates using compounds of the invention.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: October 25, 2011
    Assignee: Arizona Board of Regents, A Body Corporate Acting for and on Behalf of Arizona State University
    Inventors: John Kouvetakis, Jesse Tice, Yan-Yan Fang
  • Patent number: 8039880
    Abstract: A switching circuit. The novel switching circuit includes an active device and a first circuit for providing a reactive inductive load in shunt with the active device. In an illustrative embodiment, the first circuit is implemented using a transmission line coupled between an output of the active device and ground, in parallel with the device, to minimize the parasitic effects of the device drain to source capacitance. In a preferred embodiment, the active device includes a silicon-germanium NFET optimized for operation at high frequencies (e.g. up to 20 GHz). The optimization process includes coupling a compact, low-parasitic polysilicon resistor to a gate of the NFET to provide gate RF isolation, and designing the gate manifold, drain manifold, and drain to source spacing of the NFET for optimal high frequency operation.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: October 18, 2011
    Assignee: Raytheon Company
    Inventors: Reza Tayrani, Mary A. Teshiba
  • Patent number: 8034208
    Abstract: A method of transferring a layer of a first material onto a second substrate of a second material includes, a step of forming a first embrittlement plane in a first substrate in first material, by a first ion and/or atom implantation through a first face of said substrate, a step of forming a second embrittlement plane in said first substrate, by a first ion and/or atom implantation through a second face of said substrate, in order to reduce a curvature of this first substrate, a step of assembling the first and second substrates, and a step of separating a layer from the first substrate at the level of the first embrittlement plane, without separation at the level of the second embrittlement plane.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: October 11, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Hubert Moriceau, Jean-Claude Roussin
  • Patent number: 8017504
    Abstract: In a manufacturing flow for adapting the band gap of the semiconductor material with respect to the work function of a metal-containing gate electrode material, a strain-inducing material may be deposited to provide an additional strain component in the channel region. For instance, a layer stack with silicon/carbon, silicon and silicon/germanium may be used for providing the desired threshold voltage for a metal gate while also providing compressive strain in the channel region.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: September 13, 2011
    Assignee: Globalfoundries Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Kai Frohberg
  • Patent number: 7998835
    Abstract: Methods (and semiconductor substrates produced therefrom) of fabricating (n?1) SDOI substrates using n wafers is described. A donor substrate (e.g., silicon) includes a buffer layer (e.g., SiGe) and a plurality of multi-layer stacks formed thereon having alternating stress (e.g., relaxed SiGe) and strain (e.g., silicon) layers. An insulator is disposed adjacent an outermost strained silicon layer. The outermost strained silicon layer and underlying relaxed SiGe layer is transferred to a handle substrate by conventional or known bonding and separation methods. The handle substrate is processed to remove the relaxed SiGe layer thereby producing an SDOI substrate for further use. The remaining donor substrate is processed to remove one or more layers to expose another strained silicon layer. Various processing steps are repeated to produce another SDOI substrate as well as a remaining donor substrate, and the steps may be repeated to produce n?1 SDOI substrates.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: August 16, 2011
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Lee Wee Teo, Chung Foong Tan, Shyue Seng Tan, Elgin Quek
  • Patent number: 7993947
    Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silican particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: August 9, 2011
    Assignee: NanoGram Corporation
    Inventors: Henry Hieslmair, Shivkumar Chiruvolu, Hui Du
  • Patent number: 7989926
    Abstract: A semiconductor device includes a substrate formed of a single crystal. a silicon carbide layer disposed on a surface of the single crystal substrate and an intermediate layer disposed on a surface of the silicon carbide layer and formed of a Group III nitride semiconductor, wherein the silicon carbide layer is formed of a cubic crystal stoichiometrically containing silicon copiously and the surface thereof has a (3×3) reconstruction structure.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: August 2, 2011
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 7968909
    Abstract: Reconditioned donor substrates that include a remainder substrate from a donor substrate wherein the remainder substrate has a detachment surface where a transfer layer was detached and an opposite surface; and an additional layer deposited upon the opposite surface of the remainder substrate to increase its thickness and to form the reconditioned substrate. The reconditioned substrate is recycled as a donor substrate for fabricating compound material wafers and is typically made from gallium nitride donor substrates.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: June 28, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Frederic Dupont
  • Patent number: 7960794
    Abstract: A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-y Gey layer, having the Ge content y higher than the Ge content x in the relaxed Si1-x Gex layer, is epitaxially grown on the fin. The Si1-y Gey layer covers the top and two sidewalls of the fin. The compressive stress in the Si1-y Gey layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: June 14, 2011
    Assignee: Intel Corporation
    Inventors: Brian S Doyle, Suman Datta, Been-Yih Jin, Nancy M Zelick, Robert Chau
  • Patent number: 7927956
    Abstract: A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: April 19, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius K. Orlowski, Alexander L. Barr, Mariam G. Sadaka, Ted R. White
  • Patent number: 7928017
    Abstract: A method of forming a nanowire and a semiconductor device comprising the nanowire are provided. The method of forming a nanowire includes forming a patterned SiyGe1-y layer (where, y is a real number that satisfies 0?y<1) on a base layer, and forming a first oxide layer and at least one nanowire within the first oxide layer by performing a first oxidation process on the patterned SiyGe1-y layer.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: April 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Joong S. Jeong, Eun-ju Bae
  • Patent number: 7910468
    Abstract: The present disclosure describes methods for preparing semiconductor structures, comprising forming a Ge layer on a semiconductor substrate using an admixture of (a) (GeH3)2CH2 and Ge2H6; (b) GeH3CH3 and Ge2H6; or (c) (GeH3)2CH2, GeH3CH3 and Ge2H6, wherein in all cases, Ge2H6 is in excess. The disclosure further provides semiconductor structures formed according to the methods of the invention as well as compositions comprising an admixture of (GeH3)2CH2 and/or GeH3CH3 and Ge2H6 in a ratio of between about 1:5 and 1:30. The methods herein provide, and the semiconductor structures provide, Ge layers formed on semiconductor substrates having threading dislocation density below 105/cm2 which can be useful in semiconductor devices.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: March 22, 2011
    Assignee: Arizona Board of Regents, A Body of the State of Arizona Acting for and on Behalf of Arizona State University
    Inventors: John Kouvetakis, Yan-Yan Fang
  • Patent number: 7906439
    Abstract: The invention provides a method of fabricating and electromechanical device having an active element on at least one substrate, the method having the steps of: a) making a heterogeneous substrate having a first portion, an interface layer, and a second portion, the first portion including one or more buried zones sandwiched between first and second regions formed in a first monocrystalline material, the first region extending to the surface of the first portion, and the second region extending to the interface layer, at least one said buried zone being made at least in part out of a second monocrystalline material so as to make it selectively attackable relative to the first and second regions; b) making openings from the surface of the first portion and through the first region, which openings open out to at least one said buried zone; and c) etching at least part of at least one buried zone to form at least one cavity so as to define at least one active element that is at least a portion of the second regio
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: March 15, 2011
    Assignee: Commissarit a l'Energie Atomique
    Inventors: François Perruchot, Bernard Diem, Vincent Larrey, Laurent Clavelier, Emmanuel Defay
  • Patent number: 7883979
    Abstract: A semiconductor device includes a substrate, a first device situated on the substrate, the first device including a source and a drain each situated extending a first depth within the substrate, and a second device situated on the substrate, the second device including a source and a drain each situated extending a second depth within the substrate, the second depth not equal to the first depth.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: February 8, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Zhong Tang Xuan, Shui-Ming Cheng, Sheng-Da Liu
  • Patent number: 7863650
    Abstract: A process for fabricating a multilayer structure is provided as well as the structure itself. In accordance with one embodiment, the process includes growing a growth layer on a silicon substrate by epitaxial growth, forming at least one pattern from the growth layer, depositing an oxide layer on the silicon substrate, transferring a silicon active layer onto the oxide layer, forming a cavity in the silicon active layer oxide layer above the pattern, and growing a III-V material in the cavity.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: January 4, 2011
    Assignee: S.O.I. TEC Silicon on Insulator Technologies
    Inventor: Fabrice Letertre
  • Patent number: 7825493
    Abstract: A field-effect transistor that increases the operation speeds of complementary field-effect transistors. Each of an nMOSFET and a pMODFET has a Ge channel and source and drain regions formed of an NiGe layer. The height of Schottky barriers formed at a junction between a channel region and the source region of the nMOSFET and at a junction between the channel region and the drain region of the nMOSFET is changed by very thin high-concentration segregation layers formed by making As atoms, Sb atoms, S atoms, or the like segregate at the time of forming the NiGe layer. As a result, Schottky barrier height suitable for the nMOSFET and the pMODFET can be obtained, thus being capable of realizing high-speed CMOSFETs.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: November 2, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Keiji Ikeda
  • Patent number: 7811913
    Abstract: A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the boron-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: October 12, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Jong-Jan Lee, Douglas J. Tweet, Jer-Shen Maa, Sheng Teng Hsu
  • Patent number: 7790566
    Abstract: A method is disclosed for preparing a surface of a Group III-Group V compound semiconductor for epitaxial deposition. The III-V semiconductor surface is treated with boron (B) at a temperature of between about 250° C. and about 350° C. A suitable form for supplying B for the surface treatment is diborane. The B treatment can be followed by epitaxial growth, for instance by a Group IV semiconductor, at temperatures similar to those of the B treatment. The method yields high quality heterojunction, suitable for fabricating a large variety of device structures.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jack Oon Chu, Deborah Ann Neumayer
  • Patent number: 7767541
    Abstract: A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: August 3, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Brian Joseph Greene, Jack Allan Mandelman
  • Patent number: 7749847
    Abstract: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) are formed by patterning of a gate dielectric layer, a thin silicon layer, and a silicon-germanium alloy layer. After formation of the source/drain regions and gate spacers, silicon germanium alloy portions are removed from gate stacks. A dielectric layer is formed and patterned to cover an NFET gate electrode, while exposing a thin silicon portion for a PFET. Germanium is selectively deposited on semiconductor surfaces including the exposed silicon portion. The dielectric layer is removed and a metal layer is deposited and reacted with underlying semiconductor material to form a metal silicide for a gate electrode of the NFET, while forming a metal silicide-germanide alloy for a gate electrode of the PFET.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: July 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Jack O. Chu, Young-Hee Kim