Germanium Or Silicon Or Ge-si On Iii-v Patents (Class 438/933)
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Patent number: 6372981Abstract: A group-IV semiconductor substrate has an inclined front surface, the inclination being toward a direction differing from the <010>crystal lattice direction. The substrate is cleansed by heating in the presence of a gas including a compound of the group-IV substrate element. A source gas of a group-III element is then supplied, forming an atomic film of the group-III element on the substrate surface. Starting at the same time, or shortly afterward, a source gas of a group-V element is supplied, and a III-V compound semiconductor hetero-epitaxial layer is grown. Chemical bonding of the group-III element to the group-IV substrate surface produces a crystal alignment of the hetero-epitaxial layer that leads to improved conversion efficiency when the semiconductor substrate is used in the fabrication of solar cells with compound semiconductor base and emitter layers.Type: GrantFiled: August 8, 2000Date of Patent: April 16, 2002Assignee: Oki Electric Industry Co., Ltd.Inventors: Takashi Ueda, Chouho Yamagishi, Osamu Goto
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Patent number: 6372593Abstract: First, a silicon germanium single-crystalline layer and a silicon single-crystalline layer are formed on a main surface of a bond wafer by epitaxy. The overall surface of the bond wafer is oxidized for forming a silicon oxide layer. Then, a base wafer is bonded to the bond wafer. The bond wafer and the base wafer bonded to each other are heated for reinforcing adhesion therebetween. Then, the bond wafer is removed by plasma etching with chlorine gas while making the silicon germanium single-crystalline layer serve as a stopper. Thereafter the silicon germanium single-crystalline layer is polished by chemical mechanical polishing to have a thickness suitable for forming a device. Thus implemented is a method of manufacturing an SOI substrate by bonding capable of employing a layer having a crystal state with small irregularity for serving as a stopper having selectivity for single-crystalline silicon and effectively using the stopper as a device forming layer.Type: GrantFiled: July 19, 2000Date of Patent: April 16, 2002Assignee: Mitsubishi Denki Kabushika KaishaInventors: Nobuyoshi Hattori, Satoshi Yamakawa, Junji Nakanishi
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Patent number: 6362075Abstract: Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device wafer, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and a deposited oxide.Type: GrantFiled: June 30, 1999Date of Patent: March 26, 2002Assignee: Harris CorporationInventors: Joseph A. Czagas, Dustin A. Woodbury, James D. Beasom
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Publication number: 20020031893Abstract: A semiconductor device comprises an n-conductive type Si substrate, a n-conductive type Si film formed on the n-conductive type Si substrate, a p-conductive type SiGe film formed on the n-conductive type Si film, a p-conductive type Si film formed on the p-conductive type SiGe film, a n-conductive type Si film formed on the p-conductive type Si film, a base electrode formed by removing a part of the n-conductive type Si film or changing the conductive type of a part of the n-conductive type Si film to a p-conductive type, and joining a metal terminal to a part of the p-conductive type Si film exposed by removing the N-type Si film or to the part of the n-conductive type Si film whose conductive type is changed to a p-conductive type, an emitter electrode formed by joining a metal terminal to the n-conductive type Si film, and a collector electrode formed by joining a metal terminal to a back surface of the n-conductive type Si substrate.Type: ApplicationFiled: May 25, 2001Publication date: March 14, 2002Inventor: Koji Nakano
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Patent number: 6340600Abstract: A method for fabricating a large single-grained ferroelectric thin film grown by selectively nucleated lateral crystallization (SNLC) using an artificial nucleation seed, a method for fabricating a ferroelectric capacitor using the same, and a method for fabricating a ferroelectric memory device using the same. The ferroelectric thin film fabrication method includes the steps of forming a first conductive layer on one side of a semiconductor substrate, by using a conductive material, forming an artificial nucleation seed in an island form adjacent a position where a ferroelectric thin film is to be formed in the upper portion of the first conductive layer, forming a ferroelectric thin film on the whole surface of the substrate including the nucleation seed, and thermally annealing the ferroelectric thin film to thereby grow the ferroelectric thin film positioned in the lateral side of the nucleation seed into a single-grained ferroelectric thin film.Type: GrantFiled: April 19, 2001Date of Patent: January 22, 2002Assignee: Seung Kee JooInventors: Seung Ki Joo, Jang Sik Lee
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Publication number: 20010053618Abstract: A nitride semiconductor substrate including (a) a supporting substrate, (b) a first nitride semiconductor layer having a periodical T-shaped cross-section, having grown from periodically arranged stripe-like, grid-like or island-like portions on the supporting substrate, and (c) a second nitride semiconductor substrate covering said supporting substrate, having grown from the top and side surfaces of said first nitride semiconductor layer, wherein a cavity is formed under the second nitride semiconductor layer.Type: ApplicationFiled: June 15, 2001Publication date: December 20, 2001Inventors: Tokuya Kozaki, Hiroyuki Kiyoku, Kazuyuki Chocho, Hitoshi Maegawa
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Patent number: 6326236Abstract: In a method of manufacturing a semiconductor light-emitting device involving the steps of: forming a first semiconductor layer; forming a light-emitting layer of superlattice structure by laminating a barrier layer being made of InY1Ga1−Y1N (Y1≧0) and a quantum well layer being made of InY2Ga1−Y2N (Y2>Y1 and Y2>0) on the first semiconductor layer; and forming a second semiconductor layer on the light-emitting layer, an uppermost barrier layer, which will become an uppermost layer of the light-emitting layer, is made thicker than the other barrier layers. Further, at the time of forming the second semiconductor layer, an upper surface of such uppermost barrier layer is caused to disappear so that the thickness of the uppermost barrier layer becomes substantially equal to those of the other barrier layers.Type: GrantFiled: February 3, 2000Date of Patent: December 4, 2001Assignee: Toyoda Gosei Co., Ltd.Inventors: Norikatsu Koide, Shinya Asami, Junichi Umezaki, Masayoshi Koike, Shiro Yamasaki, Seiji Nagai
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Publication number: 20010036712Abstract: A semiconductor device which does not allow production of leak current or a drop of the Early voltage and includes a diffused layer having a reduced depth. A silicon layer containing an impurity of a second conduction type is formed on a semiconductor substrate of a first conduction type, and a spacer layer formed from a single crystalline silicon layer containing germanium is provided under the silicon layer.Type: ApplicationFiled: May 14, 1999Publication date: November 1, 2001Inventor: TORU YAMAZAKI
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Publication number: 20010036678Abstract: The present invention provides an n-side-up type group III nitride semiconductor light-emitting device fabricated from an epitaxial wafer having group III nitride semiconductor crystal layers with different crystal structures, i.e., cubic and hexagonal systems. A buffer layer of a boron phosphide (BP) based material, a cubic p-type single crystal layer of a BP based material, a cubic p-type group III nitride semiconductor crystal layer, and a hexagonal n-type group III nitride semiconductor crystal layer are successively formed on a substrate of a p-type conduction Si single crystal. The temperatures for the formation of the above-mentioned buffer layer, cubic p-type group III nitride semiconductor crystal layer, and a hexagonal n-type group III nitride semiconductor crystal layer are desirably in preferred ranges.Type: ApplicationFiled: April 20, 2001Publication date: November 1, 2001Inventor: Takashi Udagawa
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Publication number: 20010024835Abstract: A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.Type: ApplicationFiled: March 21, 2001Publication date: September 27, 2001Inventors: Tingkai Li, Fengyan Zhang, Yoshi Ono, Sheng Teng Hsu
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Patent number: 6291352Abstract: Amorphous or polycrystalline silicon layers are sometimes used in the metallization steps of IC processes, for example as antireflex coatings or as etching stopper layers for etching back of tungsten. A problem is that such a layer cannot be provided by CVD or LPCVD on account of the high deposition temperature which is not compatible with standard Al metallizations. Other deposition techniques, such as sputtering or plasma CVD, often lead to a lesser material quality, a longer processing time per wafer, or a worse step covering. According to the invention, the layer is provided by CVD or LPCVD at a temperature below 500° C. under the addition of Ge. The GexSi1−x layer (8) thus obtained is found to have good properties as regards step covering, optical aspects, electrical aspects, and etching aspects, and is compatible with any Al metallization (6) already present.Type: GrantFiled: October 7, 1998Date of Patent: September 18, 2001Assignee: U.S. Philips CorporationInventors: Pierre H. Woerlee, Casparus A. H. Juffermans, Andreas H. Montree
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Patent number: 6210988Abstract: This invention relates to micro-electromechanical systems using silicon-germanium films.Type: GrantFiled: January 14, 2000Date of Patent: April 3, 2001Assignee: The Regents of the University of CaliforniaInventors: Roger T. Howe, Andrea Franke, Tsu-Jae King
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Patent number: 6197634Abstract: Thin film metal-insulator-metal capacitors having enhanced surface area are formed by a substituting metal for silicon in a preformed electrode geometry. The resulting metal structures are advantageous for high-density DRAM applications since they have good conductivity, enhanced surface area and are compatible with capacitor dielectric materials having high dielectric constant.Type: GrantFiled: September 25, 1998Date of Patent: March 6, 2001Assignee: Micron Technology, Inc.Inventor: Klaus F. Schuegraf
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Patent number: 6191006Abstract: Prior to a heat treatment for bonding a III-V group compound semiconductor layer on a silicon substrate, a thermal stress relaxation layer is provided between the silicon layer and the III-V group compound semiconductor layer thermal stress relaxation layer, having a thermal expansion coefficient equal or near to the thermal expansion coefficient of the III-V group compound semiconductor layer and having a rigidity coefficient being sufficiently large to suppress generation of any crystal defects in the III-V group compound semiconductor layer due to a thermal stress generated in the heat treatment and subsequent cooling stage by the difference in the thermal expansion coefficient between the III-V group compound semiconductor layer and the silicon layer.Type: GrantFiled: January 19, 2000Date of Patent: February 20, 2001Assignee: NEC CorporationInventor: Kazuo Mori
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Patent number: 6190925Abstract: The present invention provides a substantially single crystal PGO film with optimal the ferroelectric properties. The PGO film and adjacent electrodes are epitaxially grown to minimize mismatch between the structures. MOCVD deposition methods and RTP annealing procedures permit a PGO film to be epitaxially grown in commercial fabrication processes. These epitaxial ferroelectric have application in FeRAM memory devices. The present invention deposition method epitaxially grows ferroelectric Pb5Ge3O11 thin films along with c-axis orientation.Type: GrantFiled: April 28, 1999Date of Patent: February 20, 2001Assignee: Sharp Laboratories of America, Inc.Inventors: Tingkai Li, Fengyan Zhang, Yoshi Ono, Sheng Teng Hsu
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Patent number: 6184098Abstract: In a field effect transistor, an Si1-xGex layer is provided between a source or drain electrode deriving region and a corresponding metal (interconnection) electrode or between a contact deriving region and a metal layer formed on the upper portions of the contact deriving region to form an ohmic contact to thereby prevent the aluminum metal layer from penetrating into a p-n junction and to reduce a contact resistance.Type: GrantFiled: February 18, 1999Date of Patent: February 6, 2001Assignee: Sony CorporationInventor: Takashi Noguchi
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Patent number: 6043143Abstract: A method of improving contact resistance in a multi-layer heterostructure comprising the steps of providing a substrate, growing a crystalline material on the substrate, and doping close to an interface of the substrate and the crystalline material with n-silicon to provide continuity at the interface.Type: GrantFiled: May 4, 1998Date of Patent: March 28, 2000Assignee: Motorola, Inc.Inventor: Kumar Shiralagi
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Patent number: 5998304Abstract: A liquid phase deposition method involves the use of a supersaturated hydrofluosilicic acid aqueous solution for growing a silicon dioxide film at low temperature (30.degree. C.-50.degree. C.) on a III-V semiconductor, such as a gallium arsenide substrate. The silicon dioxide film may be used in a bipolar transistor or as a field oxide of MOS (metal oxide semiconductor). The III-V semiconductor substrate is chemically treated with an alkaline aqueous solution such as ammonium hydroxide so that the surface of the III-V semiconductor substrate is modified to facilitate the growth of the silicon dioxide film by liquid phase deposition. The growth rate of the silicon dioxide film is as fast as 1265 .ANG./hr. The silicon dioxide film has a refractive index ranging between 1.372 and 1.41.Type: GrantFiled: September 2, 1997Date of Patent: December 7, 1999Assignee: National Science CouncilInventors: Mau-Phon Houng, Yeong-Her Wang, Chien-Jung Huang
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Patent number: 5937273Abstract: A fabricating method of compound semiconductor device is proposed which has a step of varying selective growth ratio of crystal by changing either a mean free path of material gas in gas atmosphere for use in crystal growth or a thickness of a stagnant layer of the material gas, using selective growth mask having opening portion consisting of first region having a narrow width and second region having a wide width.Type: GrantFiled: December 22, 1995Date of Patent: August 10, 1999Assignee: Fujitsu LimitedInventors: Takuya Fujii, Mitsuru Ekawa, Tsuyoshi Yamamoto, Hirohiko Kobayashi
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Patent number: 5915186Abstract: In a semiconductor device manufacturing method for forming first and second bipolar transistors on a semiconductor substrate 1, a link base layer 5 for connecting a graft base layer (graft base layer 8) of the first bipolar transistor and an intrinsic base layer 12 to each other, and at least a part of a base layer 6 of the second bipolar transistor are formed simultaneously with each other, and then the link base layer 5 in a region where the intrinsic base layer 12 will be formed is removed by an etching treatment, and then by a selective epitaxial growth method, the intrinsic base layer 12 is formed in the region where the link base layer 5 is removed.Type: GrantFiled: December 18, 1997Date of Patent: June 22, 1999Assignee: Sony CorporationInventor: Takayuki Gomi
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Patent number: 5891769Abstract: A method for forming a relaxed semiconductor layer (12) includes forming a strained semiconductor layer on a substrate (11). The strained semiconductor layer has a different lattice constant than the substrate (11). Without exposing the strained semiconductor layer to an oxidizing ambient, the strained semiconductor layer is relaxed using thermal stress.Type: GrantFiled: February 27, 1998Date of Patent: April 6, 1999Assignee: Motorola, Inc.Inventors: Hang Ming Liaw, Curtis Lee Burt, Stella Q. Hong, Clifford P. Stein
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Patent number: 5888910Abstract: A method for forming an interlayer insulating film, which involves a first oxide film deposition, a GeBPSG film deposition, a thermal treatment and a second oxide film deposition all being carried out in a continuous manner in an LPCVD device. In accordance with this method, it is possible to form an interlayer insulating film having a superior planarization characteristic in a single pass. The deposition and thermal treatment of the interlayer insulating film are carried out in a continuous manner in a single processing device. Accordingly, it is possible to effectively suppress the degradation of the GeBPSG film caused by a moisture absorption. Since a protective oxide film is deposited over the GeBPSG film in a continuous manner after the thermal treatment of the GeBPSG film, the degradation of the GeBPSG film caused by the moisture absorption can be affectively suppressed.Type: GrantFiled: June 26, 1997Date of Patent: March 30, 1999Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Sang Kyun Park
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Patent number: 5824584Abstract: A non-volatile memory having a control gate (14) and a sidewall select gate (28) is illustrated. The sidewall select gate (28) is formed in conjunction with a semiconductor doped oxide (20) to form a non-volatile memory cell (7). The semiconductor element used to dope the oxide layer (20) will generally include silicon or germanium. The non-volatile memory cell (7) is programmed by storing electrons in the doped oxide (20), and is erased using band-to-band tunneling.Type: GrantFiled: June 16, 1997Date of Patent: October 20, 1998Assignee: Motorola, Inc.Inventors: Wei-Ming Chen, Lee Z. Wang, Kuo-Tung Chang, Craig Swift
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Patent number: 5783839Abstract: Disclosed is a semiconductor device, which is used as an optical detector and has: a photodiode section which has a first silicon layer, a light-absorbing layer and a second silicon layer which are in turn layered on a silicon substrate; wherein the light-absorbing layer is formed as a single silicon-germanium epitaxial layer and the single silicon-germanium epitaxial layer has a germanium concentration distribution which provides germanium concentrations of zero at its interfaces to the first silicon layer and the second silicon layer and provides a triangle-shaped concentration profile that a peak concentration value is provided in the middle of the single silicon-germanium epitaxial layer.Type: GrantFiled: March 21, 1997Date of Patent: July 21, 1998Assignee: NEC CorporationInventors: Takenori Morikawa, Tsutomu Tashiro
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Patent number: 5770492Abstract: A method is provided for forming planar, self-aligned spaced-apart wells without a high temperature oxidation step to form an ion barrier. The method comprises preparing a substrate with a silicon dioxide-polysilicon-silicon dioxide barrier layer that can be etched to expose different sublayers of the barrier at selected junctures in the production process. A single masking step defines the location of a first set of wells on the prepared substrate. The outer silicon dioxide layer is etched to expose the polysilicon layer at the selected locations, and the substrate is implanted to form the first set of wells. Following ion implantation, the substrate photo-resist is removed, and the substrate is exposed to a germanium-silicon mixture under conditions selected to preferentially deposit a germanium-silicon alloy barrier layer on the exposed polysilicon layer.Type: GrantFiled: December 18, 1996Date of Patent: June 23, 1998Assignee: LSI Logic CorporationInventor: Ashok K. Kapoor
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Patent number: 5766999Abstract: A SiGe alloy film containing electrically active impurity in a concentration higher than the intrinsic base layer is formed on the eaves-structured polycrystalline silicon film for base electrode. After that, SiGe only just under the opening is removed completely by dry etching under a condition that etching speed of SiGe is faster than that of Si, and subsequently the intrinsic base layer is formed.Type: GrantFiled: March 28, 1996Date of Patent: June 16, 1998Assignee: NEC CorporationInventor: Fumihiko Sato
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Patent number: 5763302Abstract: A method is provided for forming planar, self-aligned spaced-apart wells without a high temperature oxidation step to form an ion barrier. The method comprises preparing a substrate with a silicon dioxide-polysilicon-silicon dioxide barrier layer that can be etched to expose different sublayers of the barrier at selected junctures in the production process. A single masking step defines the location of a first set of wells on the prepared substrate. The outer silicon dioxide layer is etched to expose the polysilicon layer at the selected locations, and the substrate is implanted to form the first set of wells. Following ion implantation, the substrate photo-resist is removed, and the substrate is exposed to a germanium-silicon mixture under conditions selected to preferentially deposit a germanium-silicon alloy barrier layer on the exposed polysilicon layer.Type: GrantFiled: August 20, 1996Date of Patent: June 9, 1998Assignee: LSI Logic CorporationInventor: Ashok K. Kapoor
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Patent number: 5744396Abstract: A method for fabricating semiconductor substrates with resistivity below 0.02 ohm-cm is provided. This low resistivity is achieved by doping a silicon melt with a phosphorus concentrations above 1.times.10.sup.18. The silicon melt is also doped with a germanium concentration that is 1.5 to 2.5 times that of the phosphorus concentration and a stress and dislocation free crystalline boule is grown. Phosphorus in high concentrations will induce stress in the crystal lattice due to the difference in the atomic radius of silicon atoms versus phosphorus atoms. Germanium compensates for the atomic radius mismatch and also retards the diffusion of the phosphorus as the diffusion coefficient remains relatively constant with a doping of 1.times.10.sup.18 to 1.times.10.sup.21 atoms per cm.sup.3. This will retard phosphorus from diffusing into an overlying epitaxial layer and retard other layers formed on the substrate from being auto-doped.Type: GrantFiled: May 31, 1996Date of Patent: April 28, 1998Assignee: Motorola, Inc.Inventors: Herng-Der Chiou, Geoffrey J. Crabtree
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Patent number: 5659188Abstract: Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs on silicon is accomplished by first growing GaAs (104) on silicon (102), then growing a lattice matched cap of Al.sub.x Ga.sub.1-x As (106), next annealing out defects with the Al.sub.x Ga.sub.1-x As cap (106) limiting desorption of gallium, lastly growing further GaAs (110) directly on the cap. The lattice matched cap is also used as an implant anneal cap.Type: GrantFiled: June 7, 1995Date of Patent: August 19, 1997Assignee: Texas Instruments IncorporatedInventors: Yung-Chung Kao, Donald L. Plumton