Special (e.g., Metal, Etc.) Patents (Class 438/945)
  • Patent number: 9040428
    Abstract: Hemispheres and spheres are formed and employed for a plurality of applications. Hemispheres are employed to form a substrate having an upper surface and a lower surface. The upper surface includes peaks of pillars which have a base attached to the lower surface. The peaks have a density defined at the upper surface by an array of hemispherical metal structures that act as a mask during an etch to remove substrate material down to the lower surface during formation of the pillars. The pillars are dense and uniform and include a microscale average diameter. The spheres are formed as independent metal spheres or nanoparticles for other applications.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Augustin J. Hong, Woo-Shik Jung, Jeehwan Kim, Jae-Woong Nahum, Devendra K. Sadana
  • Patent number: 8906706
    Abstract: A method of fabricating workpieces includes one or more layers on a substrate that are masked with an ion implantation mask comprising two or more layers. The mask layers include a first mask layer closer to the substrate, and a second mask layer on the first mask layer. The method also comprises ion implanting one or more of the layers on the substrate. Ion implantation may form portions with altered physical properties from the layers under the mask. The portions may form a plurality of non-magnetic regions corresponding to apertures in the mask.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: December 9, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Kanaiyalal C. Patel, Kurt A. Rubin
  • Patent number: 8748276
    Abstract: A through portion is formed on a semiconductor substrate. Into the semiconductor substrate, a first ion implantation is performed via the through portion. The through portion is at least partially removed in the thickness direction from a region of at least a portion of the through portion when viewed in a plan view. A second ion implantation is performed into the semiconductor substrate at the region of at least the portion thereof. An implantation energy for the first ion implantation is equal to an implantation energy for the second ion implantation.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: June 10, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hideki Hayashi
  • Patent number: 8747684
    Abstract: A method and apparatus for plasma etching a workpiece, such as a semiconductor wafer, including a thin film stack having a top film disposed over a bottom film with an intervening middle film there between. Etch selectivity between the top and bottom films may be as low as between 1:1 and 2:1 and a first carbon-lean gas chemistry is used to etch through the top film, a second carbon-lean gas chemistry is used to etch through the middle film, and the bottom film is etched through by alternating between depositing a polymer passivation on the top film using a carbon-rich gas chemistry and an etching of the bottom film with a third carbon-lean gas chemistry, which may be the same as the first carbon-lean gas chemistry.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: June 10, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Sunil Srinivasan, Jinhan Choi, Anisul H. Khan
  • Patent number: 8735301
    Abstract: A method for manufacturing a semiconductor integrated circuit includes providing a substrate having at least a metal hard mask formed thereon. Subsequently a patterning step is performed to the metal hard mask to form a patterned metal hard mask and followed by performing a H2O plasma treatment to the patterned metal hard mask.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: May 27, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Chun-Lung Chen
  • Patent number: 8685858
    Abstract: Hemispheres and spheres are formed and employed for a plurality of applications. Hemispheres are employed to form a substrate having an upper surface and a lower surface. The upper surface includes peaks of pillars which have a base attached to the lower surface. The peaks have a density defined at the upper surface by an array of hemispherical metal structures that act as a mask during an etch to remove substrate material down to the lower surface during formation of the pillars. The pillars are dense and uniform and include a microscale average diameter. The spheres are formed as independent metal spheres or nanoparticles for other applications.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Augustin J. Hong, Woo-Shik Jung, Jeehwan Kim, Jae-Woong Nah, Devendra K. Sadana
  • Patent number: 8598038
    Abstract: A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: December 3, 2013
    Inventors: Yves Morand, Thierry Poiroux
  • Patent number: 8575021
    Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 5, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Thomas R. Boussie, Tony P. Chiang, Anh Duong, Zachary Fresco, Nitin Kumar, Chi-I Lang, Sandra G. Malhotra, Jinhong Tong
  • Patent number: 8563433
    Abstract: A process to form a via hole in a semiconductor wafer is disclosed. The process includes steps of, preparing a metal mask and etching the wafer by the metal mask as the etching mask. The preparation of the metal mask includes steps of: coating a nega-resist on the back surface of the wafer, carrying out the photolithography for the coated nega-resist, plating a metal selectively by the patterned photoresist, and removing the patterned photoresist.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: October 22, 2013
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Toshiyuki Kosaka
  • Patent number: 8557128
    Abstract: Methods for fabricating sub-lithographic, nanoscale microchannels utilizing an aqueous emulsion of an amphiphilic agent and a water-soluble, hydrogel-forming polymer, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: October 15, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Patent number: 8486741
    Abstract: The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: July 16, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Pietro Montanini, Giovanna Germani, Ilaria Gelmi, Marta Mottura
  • Patent number: 8324003
    Abstract: A thin film transistor display panel includes gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring; a semiconductor pattern formed over the gate insulation layer; data wiring formed over the gate insulation layer or the semiconductor pattern and including source electrodes, drain electrodes, and data pads; a protection layer including a Nega-PR type of organic insulating layer formed all over the semiconductor pattern and the data wiring, wherein the thickness of the Nega-PR type of organic insulating layer in both the gate and data pad regions is smaller than in the other regions; and a pixel electrode connected to the drain electrode. When exposing the Nega-PR type of passivation layer in the pad region during a photolithography process, a photomask having a lattice pattern made of a metal such as Cr that has a line width of less than the resolution of a light exposer is used.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: December 4, 2012
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hoon Kang, Jin-Ho Ju, Yang-Ho Jung, Jae-Sung Kim
  • Patent number: 8258052
    Abstract: A method of manufacturing a silicon carbide semiconductor device according to the present invention includes the steps of (a) forming an implantation mask made up of a plurality of unit masks on a silicon carbide semiconductor layer, and (b) implanting predetermined ion in the silicon carbide semiconductor layer at a predetermined implantation energy by using the implantation mask. In the step (a), the implantation mask is formed such that a length from any point in the unit mask to an end of the unit mask can be equal to or less than a scattering length obtained when the predetermined ion is implanted in silicon carbide at the predetermined implantation energy and the implantation mask can have a plurality of regions different from each other in terms of a size and an arrangement interval of the unit masks.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: September 4, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koji Okuno, Yoichiro Tarui
  • Patent number: 8232122
    Abstract: A method for fabricating an LED chip is provided. Firstly, a SiO2 pattern layer is formed on a top surface of a substrate. Then, lighting structures are grown on a portion of the top surface of substrate without the SiO2 pattern layer thereon. Thereafter, the SiO2 pattern layer is removed by wet etching to form spaces between bottoms of the lighting structures and substrate. An etching solution is used to permeate into the spaces and etch the lighting structures from the bottoms thereof, whereby the lighting structures each with a trapezoid shape is formed. Sidewalls of each of the lighting structures are inclined inwardly along a top-to-bottom direction.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 31, 2012
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Po-Min Tu, Shih-Cheng Huang
  • Patent number: 8232214
    Abstract: A liquid crystal display device includes a plurality of gate lines and data lines crossing each other to define a plurality of pixel regions, a plurality of thin film transistors, each disposed in one of the pixel regions, and a plurality of pixel electrodes, each disposed in one of the pixel regions, wherein the thin film transistor includes at least one Ti layer.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: July 31, 2012
    Assignee: LG Display Co., Ltd
    Inventors: Gee-Sung Chae, Yong-Sup Hwang
  • Patent number: 8123960
    Abstract: Methods for fabricating sublithographic, nanoscale microchannels utilizing an aqueous emulsion of an amphiphilic agent and a water-soluble, hydrogel-forming polymer, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Patent number: 8030199
    Abstract: A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: October 4, 2011
    Assignee: Agere Systems Inc.
    Inventors: Sailesh Chittipeddi, Taeho Kook, Avinoam Kornblit
  • Patent number: 8026155
    Abstract: A method for producing a semiconductor device includes forming an aluminum layer on a core substrate, anodizing the aluminum layer into an alumina layer having a plurality of nanoholes, forming an n-type GaN layer by growing crystals of a compound semiconductor such as an n-type GaN on the alumina layer and inside the nanoholes, and dissolving the alumina layer with an acid. As a result, gaps are formed and a structure in which the core substrate is joined to the n-type GaN layer through portions, other than the gaps, having a very small area is generated. Then a laser beam is applied to the n-type GaN layer through the core substrate to separate the n-type GaN layer from the core substrate by a laser lift-off technique.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: September 27, 2011
    Assignee: Empire Technology Development LLC
    Inventor: Takahisa Kusuura
  • Patent number: 7981817
    Abstract: A production method for a semiconductor device includes providing a semiconductor substrate having semiconductor layer of a first conductivity type formed on a surface thereof; forming a first mask so as to cover a predetermined region of the semiconductor layer; (c) forming a well region of a second conductivity type by implanting impurity ions of the second conductivity type into the semiconductor layer having the first mask formed thereon; reducing the thickness of the first mask by removing a portion of the first mask; forming a second mask covering a portion of the well region by using photolithography; and forming a source region of the first conductivity type by implanting impurity ions of the first conductivity type into the semiconductor layer having the first mask with the reduced thickness and the second mask formed thereon.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: July 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Koichi Hashimoto, Shin Hashimoto, Kyoko Egashira
  • Patent number: 7977247
    Abstract: The present invention relates to a semiconductor structure such as a field effect transistors (FETs) in which the channel region of each of the FETs is composed of an array of more than one electrically isolated channel. In accordance with the present invention, the distance between each of the channels present in the channel region is within a distance of no more than twice their width from each other. The FETs of the present invention are fabricated using methods in which self-assembled block copolymers are employed in forming the channel.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Charles T. Black, Ricardo Ruiz
  • Patent number: 7857982
    Abstract: The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A feature pattern is formed in such layers. A feature is etched only partially into the substrate material using the hard mask layers with the feature pattern therein as a mask. After the partial etching, at least one of the hard mask layers is etched selectively relative to the substrate material and remaining of the hard mask layers. After etching at least one of the hard mask layers, the feature is further etched into the substrate material using at least an innermost of the hard mask layers as a mask. After the further etching, the innermost hard mask layer and any hard mask layers remaining thereover are removed from the substrate, and at least a portion of the feature is incorporated into an integrated circuit.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: December 28, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, Gurtej S. Sandhu, Aaron R. Wilson, Tony Schrock
  • Patent number: 7855148
    Abstract: Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are wider than middle regions of the features. During the pitch reduction process, spacer sidewalls formed between adjacent ends of the features come into substantial contact with one another, isolating the spaces between the features. In another embodiment, the features have a single width and an additional feature is located near ends of the features. Spacer sidewalls formed between adjacent features and the additional feature come into substantial contact with one another, isolating the spaces between the features.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: December 21, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Adam L. Olson
  • Patent number: 7816238
    Abstract: A GaN substrate having a large diameter of two inches or more by which a semiconductor device such as a light emitting element with improved characteristics such as luminance efficiency, an operating life and the like can be obtained at low cost industrially, a substrate having an epitaxial layer formed on the GaN substrate, a semiconductor device, and a method of manufacturing the GaN substrate are provided. A GaN substrate has a main surface and contains a low-defect crystal region and a defect concentrated region adjacent to low-defect crystal region. Low-defect crystal region and defect concentrated region extend from the main surface to a back surface positioned on the opposite side of the main surface. A plane direction [0001] is inclined in an off-angle direction with respect to a normal vector of the main surface.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: October 19, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideki Osada, Hitoshi Kasai, Keiji Ishibashi, Seiji Nakahata, Takashi Kyono, Katsushi Akita, Yoshiki Miura
  • Patent number: 7767507
    Abstract: A polycrystalline silicon thin film to be used in display devices, the thin film having adjacent primary grain boundaries that are not parallel to each other, wherein an area surrounded by the primary grain boundaries is larger than 1 ?m2, a fabrication method of the polycrystalline silicon thin film, and a thin film transistor fabricated using the method.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: August 3, 2010
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Ji Yong Park, Hye Hyang Park
  • Patent number: 7718498
    Abstract: A semiconductor device suitable for a source-follower circuit, provided with a gate electrode formed on a semiconductor substrate via a gate insulation film, a first conductivity type layer formed in the semiconductor substrate under a conductive portion of the gate electrode and containing a first conductivity type impurity, first source/drain regions of the first conductivity type impurity formed in the semiconductor substrate and extended from edge portions of the gate electrode, and second source/drain regions having a first conductivity type impurity concentration lower than that in the first source/drain regions and formed adjoining the gate insulation film and the first source/drain regions in the semiconductor substrate so as to overlap portions of the conductive portion of the gate electrode.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: May 18, 2010
    Assignee: Sony Corporation
    Inventor: Kazuichiro Itonaga
  • Patent number: 7709390
    Abstract: Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are wider than middle regions of the features. During the pitch reduction process, spacer sidewalls formed between adjacent ends of the features come into substantial contact with one another, isolating the spaces between the features. In another embodiment, the features have a single width and an additional feature is located near ends of the features. Spacer sidewalls formed between adjacent features and the additional feature come into substantial contact with one another, isolating the spaces between the features.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: May 4, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Adam L. Olson
  • Patent number: 7700473
    Abstract: A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: April 20, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chang Liu, Ming-Hui Shen, Chi-Hsin Lo, Chia-Shiung Tsai, Yi-Shin Chu
  • Patent number: 7678693
    Abstract: An exposure method executed after processing a hole in a substrate of a semiconductor device, has an exposure step of transferring a pattern on a mask onto an upper layer of the hole and forming a wiring groove by exposure, wherein a quantity of exposure with which a wiring groove 11 just above the hole or the wiring groove in the vicinity of the hole is exposed to light, is greater than a quantity of exposure with which a wiring groove 11A in a position spaced away from just above the hole is exposed to the light.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: March 16, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Fumitoshi Sugimoto, Kiyoshi Ozawa
  • Patent number: 7670949
    Abstract: A method of manufacturing a semiconductor device includes: forming a first photosensitive material pattern having an opening hole on a work target layer formed on an active surface of a substrate; performing a first etching by performing an etching treatment to the work target layer using the first photosensitive material pattern as a mask, and forming one of a concave and a groove in a tapered shape with a wide opening to the work target layer while enlarging the opening hole, by performing the etching treatment so as to enlarge the opening hole; and filling a metal film into one of the concave and the groove.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: March 2, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Chiharu Iriguchi
  • Patent number: 7635652
    Abstract: A mask with hydrophobic surface. The mask includes a substrate, a plurality of patterns formed on the substrate, and a self-assembled monolayer (SAM) formed on the substrate exposed by the patterns. The self-assembled monolayer includes an alkyltrichlorosilane-based layer such as octadecyltrichlorosilane (OTS) or perfluorodecyltrichlorosilane (FDTS) and formed by vapor process or solution process.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: December 22, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventor: Chih-Wing Chang
  • Patent number: 7612980
    Abstract: A mask for manufacturing integrated circuits and use of the mask. The mask has a mask substrate. The mask also has an active mask region within a first portion of the mask substrate. The active region is adapted to accumulate a pre-determined level of static electricity. The mask also has a first guard ring structure surrounding a portion of the active mask region to isolate the active region from an outer region of the mask substrate and a second guard ring structure having at least one fuse structure surrounding a portion of the first guard ring structure. The fuse structure is operably coupled to the active region to absorb a current from static electricity. The static electricity is accumulated by the active region to the pre-determined level and being discharged as current to the fuse structure while maintaining the active region free from damage from the static electricity.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: November 3, 2009
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Kuei-Chi Kuo
  • Patent number: 7585424
    Abstract: This invention provides a pattern reversal process for self aligned imprint lithography (SAIL). The method includes providing a substrate and depositing at least one layer of material upon the substrate. A pattern is then established upon the layer of material, the pattern providing at least one exposed area and at least one covered area of the layer of material. The exposed areas are treated to toughen the material and reverse the pattern. Subsequent etching removes the un-toughened material. A thin-film transistor device provided by the pattern reversal process is also provided.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: September 8, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Ping Mei
  • Patent number: 7579202
    Abstract: The present invention discloses a method for fabricating a light emitting diode element, which incorporates an epitaxial process with an etching process to etch LED epitaxial layers bottom up and form side-protrudent structures, whereby the LED epitaxial layers have non-rectangular inclines, which can solve the problem of total reflection and promote light-extraction efficiency. Further, the method of the present invention has a simple fabrication process, which can benefit mass production and lower cost.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: August 25, 2009
    Assignee: Tekcore Co., Ltd.
    Inventors: Wen-Chieh Hsu, Yu-Chuan Liu, Jenn-Hwa Fu, Shih-Hung Lee, Tai-Chun Wang
  • Patent number: 7569414
    Abstract: A CMOS imager and non-volatile memory are integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. A protective layer covers the non-volatile memory contained on the substrate for blocking light received by the CMOS imager. The protective layer can be a metal layer used as an interconnect over other areas of the substrate or an opaque layer provided during the fabrication process. Integrating a CMOS imager, non-volatile memory and peripheral circuitry for decoding and processing optical information received by the CMOS imager allows for a single chip image sensing device, such as a digital camera.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: August 4, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Christophe J. Chevallier
  • Patent number: 7563722
    Abstract: A method of micro- and nanotexturing of various solid surfaces in plasma where carbon nanotubes are used as an etch mask. The method allows obtaining textures with feature sizes that can be controlled with the nanotube dimensions and the density of coating the treated surface.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: July 21, 2009
    Assignee: Applied Nanotech Holdings, Inc.
    Inventors: Zvi Yaniv, Igor Pavlovsky, Mohshi Yang
  • Patent number: 7517466
    Abstract: A pattern forming material contains a block copolymer or graft copolymer and forms a structure having micro polymer phases, in which, with respect to at least two polymer chains among polymer chains constituting the block copolymer or graft copolymer, the ratio between N/(Nc?No) values of monomer units constituting respective polymer chains is 1.4 or more, where N represents total number of atoms in the monomer unit, Nc represents the number of carbon atoms in the monomer unit, No represents the number of oxygen atoms in the monomer unit.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: April 14, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Toshiro Hiraoka, Yoshihiro Akasaka, Yasuyuki Hotta
  • Patent number: 7470606
    Abstract: The invention includes masking methods. In one implementation, a masking material which includes boron doped amorphous carbon is formed over a feature formed on a semiconductor substrate. The masking material includes at least about 0.5 atomic percent boron. The masking material is substantially anisotropically etched effective to form an anisotropically etched sidewall spacer which includes the boron doped amorphous carbon on a sidewall of the feature. The substrate is then processed proximate the spacer while using the boron doped amorphous carbon-including spacer as a mask. After processing the substrate proximate the spacer, the boron doped amorphous carbon-including spacer is etched from the substrate. Other implementations and aspects are contemplated.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: December 30, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Zhiping Yin, Gurtej S. Sandhu
  • Patent number: 7322287
    Abstract: Improved apparatus for imprint lithography involves using direct fluid pressure to press a mold into a substrate-supported film. Advantageously the mold and/or substrate are sufficiently flexible to provide wide area contact under the fluid pressure. Fluid pressing can be accomplished by sealing the mold against the film and disposing the resulting assembly in a pressurized chamber. The result of this fluid pressing is enhanced resolution and high uniformity over an enlarged area.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: January 29, 2008
    Assignee: Nanonex Corporation
    Inventors: Hua Tan, Linshu Kong, Mingtao Li, Stephen Y. Chou
  • Patent number: 7282461
    Abstract: Disclosed is a phase-shifting mask having a pattern comprising a plurality of substantially transparent regions and a plurality of substantially opaque regions wherein the mask pattern phase-shifts at least a portion of incident radiation and wherein the phases are substantially equally spaced, thereby increasing resolution of a given lithographic system. Further disclosed is a semiconductor device fabricated utilizing the phase-shifting mask.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: October 16, 2007
    Assignee: Agere Systems, Inc.
    Inventor: Feng Jin
  • Patent number: 7241683
    Abstract: A method for forming features in an etch layer is provided. A first mask is formed over the etch layer where the first mask defines a plurality of spaces with widths. The first mask is laterally etched where the etched first mask defines a plurality of spaces with widths that are greater than the widths of the spaces of the first mask. A sidewall layer is formed over the etched first mask where the sidewall layer defines a plurality of spaces with widths that are less than the widths of the spaces defined by the etched first mask. Features are etched into the etch layer through the sidewall layer, where the features have widths that are smaller than the widths of the spaces defined by the etched first mask. The mask and sidewall layer are removed.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: July 10, 2007
    Assignee: Lam Research Corporation
    Inventors: Eric Hudson, S. M. Reza Sadjadi
  • Patent number: 7205184
    Abstract: A method of crystallizing a silicon film by which it is possible to obtain a polycrystalline silicon thin film having a uniform crystal structure and a good quality, and a method of manufacturing a thin film transistor-liquid crystal display (TFT-LCD) using the same. In the method of crystallizing the silicon film, an amorphous silicon film is formed on a substrate and a reflective film pattern is formed on the amorphous silicon film. The silicon film is crystallized by irradiating a laser onto the amorphous silicon film. The reflective film pattern is formed to expose the channel of the thin film transistor in the amorphous silicon film.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: April 17, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Heon-je Kim
  • Patent number: 7199059
    Abstract: A method for removing polymer as an etching residue is described. A substrate with polymer as an etching residue thereon is provided, and a hydrogen-containing plasma is used to treat the substrate. A wet clean step is then performed to remove the polymer from the substrate. The treatment using hydrogen-containing plasma can change the chemical property of the polymer, so that the polymer can be removed more easily in the subsequent wet clean step.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: April 3, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Fang Cheng, Shan-Jen Yu, Cheng-Kweng Chen, Yu-Ming Huang
  • Patent number: 7172960
    Abstract: A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: February 6, 2007
    Assignee: Intel Corporation
    Inventors: Sanjay S. Natarajan, Sean W. King, Khaled A. Elamrawi
  • Patent number: 7157377
    Abstract: A semiconductor device is made by patterning a conductive layer for forming gates of transistors. The process for forming the gates has a step of patterning photoresist that overlies the conductive layer. The patterned photoresist is trimmed so that its width is reduced. Fluorine, preferably F2, is applied to the trimmed photoresist to increase its hardness and its selectivity to the conductive layer. Using the trimmed and fluorinated photoresist as a mask, the conductive layer is etched to form conductive features useful as gates. Transistors are formed in which the conductive pillars are gates. Other halogens, especially chlorine, may be substituted for the fluorine.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: January 2, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cesar M. Garza, William D. Darlington, Stanley M. Filipiak, James E. Vasek
  • Patent number: 7132361
    Abstract: Via holes are formed in a continuous inline shadow mask production system by depositing a first conductor layer and subsequently depositing a first insulator layer over a portion of the first conductor layer. The first insulator layer is deposited in a manner to define at least one notch along its edge. The second insulator layer is then deposited on another portion of the first conductor layer in a manner whereupon the second insulator layer slightly overlaps each notch of the first insulator layer, thereby forming the one or more via holes. A conductive filler can optionally be deposited in each via hole. Lastly, a second conductive layer can be deposited over the first insulator layer, the second insulator layer and, if provided, the conductive filler.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: November 7, 2006
    Assignee: Advantech Global, Ltd
    Inventors: Thomas P. Brody, Joseph A. Marcanio, Jeffrey W. Conrad, Timothy A. Cowen
  • Patent number: 7119014
    Abstract: A method for fabricating a semiconductor memory device includes the consecutive steps of consecutively depositing metallic, nitride and oxide films on an underlying insulating film, patterning the nitride and oxide films to allow the oxide film to have a patterned area smaller than the patterned area of the nitride film, patterning the metallic film by using the nitride and oxide films as a mask, forming a side-wall film having a tapered mesa structure on the oxide, nitride and metallic films, embedding the side-wall oxide film by an interlayer dielectric film, and forming a contact hole in the interlayer dielectric film and the underlying oxide film while using the side-wall oxide film as an etch stopper.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: October 10, 2006
    Assignee: Elpida Memory, Inc.
    Inventor: Yoshihiro Satoh
  • Patent number: 7105431
    Abstract: The invention includes masking methods. In one implementation, a masking material comprising boron doped amorphous carbon is formed over a feature formed on a semiconductor substrate. The masking material comprises at least about 0.5 atomic percent boron. The masking material is substantially anisotropically etched effective to form an anisotropically etched sidewall spacer comprising the boron doped amorphous carbon on a sidewall of the feature. The substrate is then processed proximate the spacer while using the boron doped amorphous carbon comprising spacer as a mask. After processing the substrate proximate the spacer, the boron doped amorphous carbon comprising spacer is etched from the substrate. Other implementations and aspects are contemplated.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: September 12, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Zhiping Yin, Gurtej S. Sandhu
  • Patent number: 7083994
    Abstract: This invention generally relates to semiconductor devices, for example lasers and more particularly to single frequency lasers and is directed at overcoming problems associated with the manufacture of these devices. In particular, a laser device is provided formed on a substrate having a plurality of layers (1,2,3,4,5), the laser device comprising at least one waveguide (for example a ridge) established by the selective removal of sections of at least one of the layers. Wherein alignment features are provided on the device to facilitate subsequent placement.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: August 1, 2006
    Assignee: Eblana Photonics Limited
    Inventor: James O'Gorman
  • Patent number: 7029592
    Abstract: A process for forming an etch mask having a discontinuous regular pattern utilizes beads, each of which has a substantially unetchable core covered by a removable spacer coating. Beads are dispensed as a hexagonally packed monolayer onto a thermo-adhesive layer. Following a vibrational step which facilitates hexagonal packing of the beads, the resultant assembly is heated so that the beads adhere to the adhesive layer. Excess beads are then discarded. Spacer shell material is then removed from each of the beads, leaving core etch masks. The core-masked target layer is then plasma etched to form a column of target material directly beneath each core. The cores and any spacer material underneath the cores are removed. The resulting circular island of target material may be used as an etch mask during wet isotropic etching of an underlying layer.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: April 18, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Joel M. Frendt
  • Patent number: 6998333
    Abstract: A method for forming first and second linear structures of a first composition that meet at right angles, there being a gap at the point at which the structures meet. The linear structures are constructed on an etchable crystalline layer having the first composition. First and second self-aligned nanowires of a second composition are grown on this layer and used as masks for etching the layer. The self-aligned nanowires are constructed from a material that has an asymmetric lattice mismatch with respect to the crystalline layer. The gap is sufficiently small to allow one of the structures to act as the gate of a transistor and the other to form the source and drain of the transistor. The gap can be filled with electrically switchable materials thereby converting the transistor to a memory cell.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: February 14, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Yong Chen, R. Stanley Williams