Abstract: A process for forming an etch mask having a discontinuous regular pattern utilizes beads, each of which has a substantially unetchable core covered by a removable spacer coating. Beads are dispensed as a hexagonally packed monolayer onto a thermo-adhesive layer. Following a vibrational step which facilitates hexagonal packing of the beads, the resultant assembly is heated so that the beads adhere to the adhesive layer. Excess beads are then discarded. Spacer shell material is then removed from each of the beads, leaving core etch masks. The core-masked target layer is then plasma etched to form a column of target material directly beneath each core. The cores and any spacer material underneath the cores are removed. The resulting circular island of target material may be used as an etch mask during wet isotropic etching of an underlying layer.

Abstract: A method for forming first and second linear structures of a first composition that meet at right angles, there being a gap at the point at which the structures meet. The linear structures are constructed on an etchable crystalline layer having the first composition. First and second self-aligned nanowires of a second composition are grown on this layer and used as masks for etching the layer. The self-aligned nanowires are constructed from a material that has an asymmetric lattice mismatch with respect to the crystalline layer. The gap is sufficiently small to allow one of the structures to act as the gate of a transistor and the other to form the source and drain of the transistor. The gap can be filled with electrically switchable materials thereby converting the transistor to a memory cell.

Abstract: A method of forming a micro groove structure according to the invention has the steps of: (a) forming a mask pattern on a substrate capable of being subjected to dry etching; (b) dry etching the substrate having the mask pattern formed thereon; (c) vapor-phase forming a thin film of a masking material for the dry etching, on a non-etched surface portion of the substrate after the dry etching; and (d) dry etching the substrate having the thin film formed thereon. The steps (a) to (d) are carried out successively.

Abstract: In order to shorten the period for the development and manufacture of a semiconductor integrated circuit device, at the time of transferring integrated circuit patterns onto a wafer by an exposure process, a photomask PM1 is used which is provided partially with light shielding patterns 3a formed of a resist film, in addition to light shielding patterns formed of a metal.

Abstract: On a multilayer film formed on a lower electrode layer, a resist layer having cutaway parts at a lower portion is formed, and on parts of the upper surface of the multilayer film which are not overlapped with the resist layer except for areas inside the cutaway parts, first gap layers are formed. Accordingly, a predetermined gap T1 can be formed between the first gap layers in the track width direction. Next, in the following step, two end surfaces of the multilayer film and the first gap layers in the track width direction are milled. Hence, according to the present invention, compared to the case in the past, the predetermined gap T1 provided between the first gap layers can be formed into a minute size with superior accuracy, the current path-squeezing structure can be easily formed, and a magnetic sensor having superior change in resistance (?R) and reproduction output can be manufactured.

Abstract: A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.

Abstract: A method for estimating relative remaining film thickness distribution (CMP pattern ratio distribution) among sparse and dense active regions after CMP on the basis of the layout of a mask pattern in a one-chip mask region. In each mask pattern, a reduced region is created by removing an area of a predetermined width from the mask pattern along the edge of the mask pattern. Then, the one-chip mask region is segmentalized into predetermined regions to create a plurality of segmentalized regions. On each of the segmentalized regions, the area ratio of all reduced regions occupying a region that includes a segmentalized region at a fixed position and has the same size and shape as those of the foregoing one-chip mask region is acquired. Based on the acquired area ratio, the distribution of remaining film thickness of a surface protection film in the one-chip mask region, i.e., the CMP pattern ratio, is acquired.

Abstract: A semiconductor apparatus fabrication method is capable of effectively suppressing edge roughness when an extremely fine resist pattern is formed. In the semiconductor apparatus fabrication method, the extremely fine resist pattern is covered with a film whose heat-resistance temperature is higher than the softening temperature of the resist pattern. In this state, the resist pattern is heated at a temperature higher than the softening temperature and lower than the heat-resistance temperature in order to cause reflow in the resist pattern.

Abstract: A method of fabricating a vertically profiled electrode like a T-gate 40 on a semiconductor substrate 20 is described. The method comprises providing a resist structure 34 on the substrate 20, the resist structure 34 containing at least a first resist pattern 24? arranged on the substrate 20 and having a first opening 26, the first resist being negative resist, and a second resist pattern 32 having a second opening 30 surrounding the first opening 26. The vertical profile of the gate electrode 40 is defined by the contours and the relative location of the first and the second opening 26, 30. On the resist structure 34 a metal 38 is deposited and lift-off is performed to remove the second resist 32 together with the metal 38 deposited thereon.

Abstract: A conductive pattern is obtained by forming concave-convex on a substrate by using a pattern substrate. A conductive thin layer is formed and then coated with a layer of a photosensitive resin. The photo sensitive resin is exposed and development by using the pattern substrate to bare the conductive thin layer on the convex portion and electrolytic plating. The conductive thin layer and the layer of the photosensitive resin on the concave portion may then be removed.

Abstract: A ball electrode forming method comprises steps of: preparing a semiconductor apparatus having a plurality of electrode pads; arranging a mask having an upper surface and a lower surface, an area in the lower surface being larger than an area in the upper surface, and a plurality of openings extended from the upper surface to the lower surface, on a surface of the semiconductor apparatus having the electrode pads formed thereon so that the surface and the lower surface can face each other; arranging solder balls on the electrode pads arranged in the openings from the upper surface side of the mask; and electrically connecting the solder balls to the electrode pads to form ball electrodes. Thus, regarding a method for forming a ball electrode in a semiconductor apparatus having a BGA structure, an efficient ball electrode forming method is employed to prevent omission of a ball electrode.

Abstract: The invention relates generally to lithographic patterning of very small features. In particular, the invention relates generally to patterning of semiconductor circuit features smaller than lithographically defined using either conventional optical lithography or next generation lithography techniques. The invention relates more particularly, but not by way of limitation, to lateral trimming of photoresist images.

Abstract: According to one embodiment, verifying a reticle may include patterning an inspected layer (102-2) according to a reticle pattern, depositing a contrast enhancing layer (104-0) on a patterned layer (102-2), and inspecting a reticle patterned formed in the inspected layer (102-2).

Abstract: Disclosed is a thin film transistor (TFT) for a liquid crystal display (LCD) and a method for manufacturing the same that allows the number of photomasks used in a photolithography process to be decreased as compared to conventional methods. A passivation film is formed as a single layered organic insulating film, and the number of needed exposure steps is reduced, so as to decrease the number of needed photomask sheets and thereby improve the efficiency of the TFT production process. Applications of the disclosed method include reflection and transmission composite type LCDs as well as a reflection type LCD.

Abstract: A method for making an emitter for a display device, an emitter array produced by such method, an etch mask used during such method, and a method for making such an etch mask. The method for making the emitter comprising providing a substrate, forming a conducting layer on the substrate, forming an emitting layer on the conducting layer, forming an etch mask having a controlled distribution of a plurality of mask sizes over the emitting layer, and forming at least one emitter by removing portions of the emitting layer using the etch mask. The method for making the etch mask comprising forming an etch mask layer over an emitting layer, forming a patterning layer having a controlled distribution of mask sizes over the etch mask layer, and forming the etch mask by removing portions of the etch mask layer using the controlled distribution of mask sizes in the patterning layer.

Abstract: A thin hard mask is formed over a semiconductor substrate. The thin hard mask allows diffusion of a sacrificial material or pore-forming agent therethrough to form an underlying air gap or porous dielectric region. The thin hard mask may be a polymer or an initially porous material that may be later densified. The thin hard mask may be used to prevent etch steps used in forming an unlanded via from reaching layers below the hard mask.

Abstract: In order to shorten the period for the development and manufacture of a semiconductor integrated circuit device, at the time of transferring integrated circuit patterns onto a wafer by an exposure process, a photomask PM1 is used which is provided partially with light shielding patterns 3a formed of a resist film, in addition to light shielding patterns formed of a metal.

Abstract: A method for intra-cell alignment of a substrate and mask comprises providing a substrate comprising an exposed photosensitive material, providing a phase-shift mask, and aligning the phase-shift mask to an intra-cell structure on the substrate.

Abstract: A method for manufacturing an electronic device is provided. In one example of the method, the method prevents deformation of a resist mask caused by the irradiation of exposure light. The resist mask has a resist as an opaque element, and can afford mask patterns undergoing little change even with an increase in the number of wafers subjected to exposure processing. The resist mask maintains a high dimensional accuracy. A photomask pattern is formed using as an opaque element a resist comprising a base resin and Si incorporated therein or a resist with a metal such as Si incorporated thereby by a silylation process, to improve the resistance to active oxygen. The deformation of a resist opaque pattern in a photomask is prevented. The dimensional accuracy of patterns transferred onto a Si wafer is improved in repeated use of the photomask.

Abstract: A method of fabricating an interconnect line comprises forming a wall, depositing an etch mask having a thickness that decreases towards a bottom of the wall, and isotropically etching the wall at the bottom to form the interconnect line having a pre-determined gap between the substrate and a bottom of the line.

Abstract: A method of fabricating a gate structure of a field effect transistor comprising processes of forming an &agr;-carbon mask and plasma etching a gate electrode and a gate dielectric using the &agr;-carbon mask. In one embodiment, the gate dielectric comprises hafnium dioxide.

Abstract: A mask and method for contact hole exposure. First, a mask including a transparent substrate, a phase shift layer installed on the transparent substrate to define a series of patterns having contact hole areas set in array, an a plurality of metal lines installed on the phase shift layer between the adjacent contact hole areas is provided. Then, an exposure is performed by transmitting a light source, such as deep ultraviolet (UV), extreme ultraviolet, or X-ray, through the mask after the metal lines absorb high degree diffraction waves.

Abstract: Polymer blobs that are development related defects are substantially eliminated in patterned photoresist masks by a heat treatment of the wafer performed at a development step in two different manners according to the present invention. In the first method, after the development has been performed as standard, the wafer is heated at 140° C. and before cooling takes place, it is rinsed with deionized water (DIW) at room temperature. In the second method, the wafer is either developed as standard but rinsed with 60° C. DIW instead of 22° C. DIW, or, after standard development, it is submitted to an extra rinse step with 60° C. DIW.

Abstract: A fabrication method of a thin film transistor array substrate includes a step of forming a gate insulation film, a semiconductor layer, an ohmic layer, and a metal film on the insulating substrate on which the gate line is formed, a step of forming a resist pattern on the metal film by a photolithography process so that its thickness is thinner on the corresponding section to the semiconductor active layer than on the other sections, a step of etching the metal film to form the source line, the source electrode, and the drain electrode, a step of removing the ohmic layer and the semiconductor layer after removing the resist on the corresponding section to the semiconductor active layer, a step of removing the metal film, and a step of removing the ohmic layer.

Abstract: Within a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is formed within the microelectronic fabrication a capacitor structure which comprises a first capacitor plate layer having formed thereupon a capacitor dielectric layer in turn having formed thereupon a second capacitor plate layer, wherein each of the foregoing layers having an exposed sidewall to thus form a series of exposed sidewalls. The capacitor structure also comprises a silicon oxide dielectric layer formed passivating the series of exposed sidewalls of the first capacitor plate layer, the capacitor dielectric layer and the second capacitor plate layer a silicon oxide dielectric layer.

Abstract: A method and system for providing a semiconductor device is disclosed. The method and system include providing a semiconductor substrate and providing a plurality of lines separated by a plurality of spaces. Each of the plurality of spaces preferably has a first width that is less than a minimum feature size. In one aspect, the method and system include providing a reverse mask having a plurality of apertures on an insulating layer. In this aspect, the method and system also include trimming the reverse mask to increase a size of each of the plurality of apertures, removing a portion of the insulating layer exposed by the plurality of trimmed apertures to provide a plurality of trenches and providing a plurality of lines in the plurality of trenches. In a second aspect, the method and system include providing a reverse mask on the insulating layer and removing a first portion of the insulating layer exposed by the plurality of apertures to provide a plurality of trenches.

Abstract: In a method for manufacturing an under-bump metallurgy (UBM) layer, a plate having a plurality of openings is prepared. Then, the plate is placed on the wafer. Finally, the material of the under-bump metallurgy layer is sputtered on the wafer using the plate as a sputter mask so as to quickly form the under-bump metallurgy layer.

Abstract: Disclosed is a mask for evaluating selective epitaxial growth process. The disclosed mask comprises a mask pattern for resistance measurement to measure sheet resistance of grown single crystal silicon in a first area, a mask pattern for selectivity evaluation to evaluate selectivity of single crystal silicon growth in a second area diagonal to the first area, mask patterns for facet generation evaluation, having different shapes, to evaluate facet generation of grown single crystal silicon in a third area, mask patterns for loading effect evaluation, having different shapes, to evaluate growth of single crystal silicon by loading effect in the upper part of a fourth area and a mask pattern for uniformity evaluation to evaluate uniformity of grown single crystal silicon in the lower part of the pattern for loading effect evaluation in the fourth area.

Abstract: A method of fabricating a gate structure of a field effect transistor comprising processes of forming an &agr;-carbon mask and plasma etching a gate electrode and a gate dielectric using the &agr;-carbon mask. In one embodiment, the gate dielectric comprises hafnium dioxide.

Abstract: A method for forming first and second linear structures of a first composition that meet at right angles, there being a gap at the point at which the structures meet. The linear structures are constructed on an etchable crystalline layer having the first composition. First and second self-aligned nanowires of a second composition are grown on this layer and used as masks for etching the layer. The self-aligned nanowires are constructed from a material that has an asymmetric lattice mismatch with respect to the crystalline layer. The gap is sufficiently small to allow one of the structures to act as the gate of a transistor and the other to form the source and drain of the transistor. The gap can be filled with electrically switchable materials thereby converting the transistor to a memory cell.

Abstract: A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning.

Abstract: A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.

Abstract: A method for creating deep features in a Si-containing substrate for use in fabricating MEMS type devices is provided. The method includes first forming a thin Ni hardmask on a surface of a Si-containing substrate. The Ni hardmask is patterned using conventional photolithography and wet etching so as to expose at least one portion of the underlying Si-containing substrate. The at least one exposed portion of the Si-containing substrate, not containing the patterned hardmask, is then etched in a plasma that includes free radicals generated from a gaseous mixture of chlorine (Cl2), sulfur hexafluoride (SF6) and oxygen (O2). The interaction of the gas species in the plasma yields a rapid silicon etch rate that is highly selective to the Ni hardmask. The etch rate ratio of Si to Ni using the inventive method is greater than 250:1.

Abstract: A process for forming an etch mask having a discontinuous regular pattern utilizes beads, each of which has a substantially unetchable core covered by a removable spacer coating. Beads which have a core and a spacer coating are dispensed as a hexagonally-packed monolayer onto a thermo-adhesive layer, which is on a target layer. The beads are kept in place by a bead confinement wall. Following a vibrational step which facilitates hexagonal packing of the beads, the resultant assembly is heated so that the beads adhere to the adhesive layer. Excess beads are then discarded. Spacer shell material is then removed from each of the beads, leaving core etch masks. The core-masked target layer is then plasma etched to form a column of target material directly beneath each core. The cores and any spacer material underneath the cores are removed. The resulting circular island of target material may be used as an etch mask during wet isotropic etching of an underlying layer.

Abstract: A method of crystallizing amorphous silicon using a mask having a transmitting portion including a plurality of stripes, wherein end lines of at least two stripes are not collinear; and a blocking portion enclosing the plurality of stripes includes the steps of setting the mask over a substrate having an amorphous silicon layer, applying a first laser beam to a first area of the amorphous silicon layer through the mask, thereby forming a first crystallization region, moving the substrate in a first direction, thereby disposing the blocking portion of the mask over the first crystallization region, and applying a second laser beam to the first area of the amorphous silicon layer through the mask, thereby forming a second crystallization region.

Abstract: A quantum device is constituted from a two-dimensional array of quantum dots formed from metal atom aggregates contained in a metalloprotein complex. The metalloprotein is arranged on the surface of a substrate having an insulation layer with a pitch of the size of the metalloprotein complex. The diameter of the metal atom aggregates used in the quantum device is 7 nm or smaller, and the pitch of the metalloprotein complex is preferably from 11 to 14 nm.

Abstract: A new method is provided for the creation of an attenuated phase shifting mask. A transparent mask substrate is provided, a layer of attenuating phase shifting material is deposited on the surface of said transparent mask substrate, a layer of opaque material is deposited on the surface of said layer of attenuating phase shifting material. A layer of photoresist is deposited over the surface of the layer of opaque material. The photoresist is exposed by E-beam, creating a mask pattern and a guard ring pattern in the photoresist. The (E-beam) exposed photoresist is removed, the pattern created in the layer of photoresist is used to etch a mask pattern in the layer of opaque material and the layer of attenuating phase shifting material. The remaining photoresist is exposed to UV radiation in the region of the mask pattern and partially in the region of the guard ring.

Abstract: A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.

Abstract: Method of producing a structure for III-V semiconductor components in which a mask is applied to a sample in a masking step, characterized in that at least one mask material is a monocrystalline III-V semiconductor material. This makes possible an easy in-situ removal of the mask from the semiconductor material, which in turn makes possible the growing of additional layers.

Abstract: A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.

Abstract: A method is provided for well printing a specified pattern even when the exposure treatment using a resist mask uses exposure light with a wavelength over 200 nm. When exposure treatment is applied to a semiconductor wafer by using exposure light with a wavelength over 200 nm, a photomask is used. The photomask is provided with an opaque pattern of a resist layer on an organic layer which is photoabsorptive in reaction to exposure light.

Abstract: A method for inspecting a pattern defect process is disclosed, in which a layer is formed to raise a signal-to-noise ratio on the substrate. This invention also provides a method for inspecting a pattern defect process. First of all, a substrate is provided. Then, a device profile is formed on the substrate, wherein the device profile comprises a defect portion. Then, a layer is formed on the device profile and the substrate, wherein the layer has an etch selectivity different from the etch selectivity of the device profile. Next, the layer is removed partially to stop on the device profile and to cause a revere mask. Then, the device profile is etched on the substrate by using the revere mask as a mask. Finally, the revere mask is removed.

Abstract: To provide a method of manufacturing a semiconductor device for manufacturing a minute pattern with high accuracy using a stencil mask. An input layout data is classified into rectangles according to pattern width or the like, a boundary is created that divides a periphery or an inside of each classified graphics, an input pattern is fractionized by the boundary, and a complementary mask with fractionized patterns on both sides of the boundary distributed into different layers is used to form a pattern.

Abstract: A modular coating apparatus is disclosed which is adapted to couple to a host system, such as a cluster or in-line type coating system, as well as to operate in stand-alone fashion. The coating apparatus uses extrusion to initially deposit a film having a desired thickness. The substrate upon which the film is deposited may be spun to further distribute the film. Various embodiments of the coating apparatus are disclosed including embodiments utilizing a shim to mask the substrate and embodiments utilizing a rotatable chuck to facilitate cleaning of the substrate and/or the chuck. Preferably the various embodiments are sub-modules which may be interchanged in the main module as desired.

Abstract: The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lover erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole. However, when only some memory cells of a group have a higher erase speed, an excessive erase requiring electric charge supply occurs only in some memories and accordingly, it is possible to rapidly complete the data.

Abstract: High density, photon-gated persistent spectral holeburning is effectuated in rare earth doped II-VI compounds such as MgS, CaS, BaS and SrS. Two-photon ionization of rare earth ions is performed, selected by a narrow band laser, producing narrow regions of reduced absorption (optical holes) in the absorption spectrum of a rare earth ion. These holes are useful for such applications as high density memory (especially, high density re-writable or photo-erasable memory), spectral holographic memory, communication, etc., no and demonstrate great survivability over reading cycles, thermal cycles and elevated temperatures. The embedment of the rare earth doped II-VI compound in a matrix comprising a polymeric material (such as PMMA), prior to the effectuation of the holeburning, may be advantageous for many embodiments. Inventive practice has successfully burned two hundred forty photon gated spectral holes in the zero phonon line (ZPL) of the 4f-5d transition of Eu2+ in a magnesium sulfide host.

Abstract: A method for using intermediate transfer layers for transferring nanoscale patterns to substrates and forming nanostructures on substrates. An intermediate transfer layer is applied to a substrate surface, and one or more mask templates are then applied to the intermediate transfer layer. Holes are etched through the intermediate transfer layer, and material may be deposited into the etched holes.

Abstract: An improved method of imprint lithography involves using direct fluid pressure to press the mold into a substrate-supported film. Advantageously the mold and/or substrate are sufficiently flexible to provide wide area contact under the fluid pressure. Fluid pressing can be accomplished by sealing the mold against the film and disposing the resulting assembly in a pressurized chamber. It can also be accomplished by subjecting the mold to jets of pressurized fluid. The result of this fluid pressing is enhanced resolution and high uniformity over an enlarged area.

Abstract: A method of fabricating a semiconductor device is provided that includes forming first and second gate electrodes on a substrate via a first photo mask, in which the first and second gate electrodes are in a longitudinal direction parallel to respective channels arranged in x-axis y-axis directions, measuring and comparing the lengths of the first and second gate electrodes on the substrate, estimating a mask bias on the basis of the difference between the actually measured lengths of the gate electrodes, and forming patterns of the first and second gate electrodes of which lengths are adjusted with the estimated mask bias on a new second photo mask, so that the first and second gate electrodes of the same length are formed on the same substrate via the new, second photo mask, regardless of the arrangement directions of the gate electrodes in parallel to channels. This has the effect of improving the processing speed of high CPU or logic element and the yield of products manufactured by this process.

Abstract: The present invention relates to lithographic methods for forming a dual relief pattern in a substrate, and the application of such methods to fabricating multilevel interconnect structures in semiconductor chips by a Dual Damascene process in which dual relief cavities formed in a dielectric are filled with conductive material to form the wiring and via levels. The invention comprises a twice patterned single mask layer Dual Damascene process modified by the addition of an easy-to-integrate sidewall liner to protect organic interlevel and intralevel dielectrics from potential damage induced by photoresist stripping steps during lithographic rework. The invention further comprises a method for forming a dual pattern hard mask which may be used to form dual relief cavities for use in Dual Damascene processing, said dual pattern hard mask comprising a first set of one or more layers with a first pattern, and a second set of one or more layers with a second pattern.