Abstract: A method of forming a micro pattern of a semiconductor device may include forming an acid-extinguisher containing film on a substrate, forming a photoresist film containing a potential acid on the acid-extinguisher containing film, forming an exposed area containing acids by exposing a portion of the photoresist film to light, forming an insoluble polymer thin film between the acid-extinguisher containing film and the exposed area by extinguishing the acids of the exposed area at an interface between the acid-extinguisher containing film and the exposed area, developing the photoresist film to form a space exposing the insoluble polymer thin film in the exposed area and a photoresist pattern integrally connected to the insoluble polymer thin film, exposing the acid-extinguisher containing film through the space by removing the insoluble polymer thin film, and removing the acid-extinguisher containing film exposed through the space.

Abstract: A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P1 is formed on the second material layer. The second material layer is etched by using the patterned mask layer as a mask to form the first features in the second material layer. The patterned mask layer is trimmed. A plurality of dopants is introduced into the second material layer not covered by the trimmed patterned mask layer. The trimmed patterned mask layer is removed to expose un-doped second material layer. The un-doped second material layer is selectively removed to form a plurality of second features with a second pitch P2. P2 is smaller than P1.

Abstract: An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.

Abstract: A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.

Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.

Abstract: A method of fabricating a semiconductor device and a fabrication system of the semiconductor device are provided. The method includes sequentially forming a film to be etched and a dielectric film and measuring a thickness of the dielectric film, forming a photoresist film on the dielectric film, performing a lithography process using the measured thickness of the dielectric film to form a photoresist film pattern, and etching the dielectric film and the film to be etched using the photoresist film pattern.

Abstract: The present disclosure provides a method for making a semiconductor device. The method includes forming a sacrificial layer on a substrate; forming a patterned resist layer on the sacrificial layer; performing an ion implantation to the substrate; applying a first wet etch solution to remove the patterned photoresist layer; and applying a second wet etch solution to remove the sacrificial layer.

Abstract: A direct write lithography system. The system includes a converter having an array of light controllable electron sources, each field emitter being arranged for converting light into an electron beam, the field emitters having an element distance between each two adjacent field emitters, each filed emitter having an activation area. A plurality of individually controllable light sources, each light source arranged for activating one field emitter. A controller controls each light source individually. Each electron beam is focused from the field emitters with a diameter smaller than the diameter of a light source on an object plane.

Abstract: A drain port and an exhaust port arranged at the bottom of a cup surrounding a substrate holding unit. A drainage tray is arranged below the cup so as to cover the moving area of the drain port when the substrate holding unit and the cup move in X-directions and Y-directions. An exhaust unit is arranged at a position corresponding to the position of the exhaust port of the cup when the substrate holding unit is in its spin-drying position. The exhaust unit is connected to the exhaust port to suck the interior of the cup when the spin-drying of the substrate is executed. The use of a flexible tube which is always connected to the exhaust port is no longer necessary.

Abstract: A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.

Abstract: An apparatus for manufacturing a liquid crystal display device is disclosed. A first robot arm at a loading side of the thru-conveyor receives a substrate coated with photoresist and conveys the substrate to a thru-conveyor. A softbake hot plate (SHP) at the unloading side of the thru-conveyor removes solvent from the substrate. A cool plate lowers the substrate temperature from which the solvent is removed. A buffer temporarily stores the substrate having the lowered temperature. A second robot arm between the thru-conveyor, the SHP, the cool plate and a loading side of the buffer, loads/unloads the substrate. A temperature control unit adjusts the substrate temperature unloaded from the buffer. A third robot arm between the unloading side of the buffer, the temperature control unit and an exposure unit that exposes the substrate, loads/unloads the substrate.

Abstract: The present invention relates to a semiconductor structure such as a field effect transistors (FETs) in which the channel region of each of the FETs is composed of an array of more than one electrically isolated channel. In accordance with the present invention, the distance between each of the channels present in the channel region is within a distance of no more than twice their width from each other. The FETs of the present invention are fabricated using methods in which self-assembled block copolymers are employed in forming the channel.

Abstract: A technique for fabricating an array of imaging pixels includes fabricating front side components on a front side of the array. After fabricating the front side components, a dopant layer is implanted on a backside of the array. A mask is formed over the dopant layer to selectively expose portions of the dopant layer. Next, the exposed portions of the dopant layer are laser annealed. Alternatively, the mask may be disposed over the backside prior to the formation of the dopant layer and the dopants implanted through the exposed portions and subsequently laser annealed.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.

Abstract: A processing method for selectively reducing or removing the region to be exposed with energy ray in a film formed on a substrate, comprising relatively scanning a first exposure light whose shape on the substrate is smaller than the whole first region to be exposed against the whole first region to be exposed to selectively remove or reduce the first region to be exposed, and exposing a whole second region to be exposed inside the whole first region to be exposed with a second exposure light to selectively expose the whole second region to be exposed.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A method and an apparatus for forming a polycrystalline layer using laser annealing for preventing damage to the peripheral region of the substrate during laser annealing. The laser annealing comprises a shadow mask structure. When crystallizing an amorphous layer by laser annealing, the shadow mask structure shields the peripheral region of the amorphous layer from laser irradiation. A method for forming a polycrystalline layer using the laser annealing apparatus is also provided in the invention.

Abstract: A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed.

Abstract: Only a region where TFTs constituting a high-performance circuit will be disposed in a precursor semiconductor film PCS on an insulating substrate GLS with an insulating layer UCL serving as an undercoat is irradiated with a first energy beam LSR so as to be poly-crystallized while growing crystal grains laterally. Further a second rapid thermal treatment is performed all over the panel so as to reduce defects in the crystal grains in a region PSI poly-crystallized by the aforementioned energy beam. Thus, a high-quality polycrystalline semiconductor thin film serving as TFTs for a high-performance circuit and having a high on-current, a low threshold value, a low variation and a sharp leading edge characteristic is obtained.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: In an electron beam lithography apparatus, when a plotting pattern is an isolated fine pattern, an exposure energy upon plotting lacks. In the prior art set forth above, dimension dependent exposure energy correction is performed as a measure, however, a problem is encountered in that excessive exposure is caused in regions where the exposure area ratio is high. The present invention solves the problem in the foregoing prior art and provides an electron beam lithography apparatus and a lithography method using an electron beam which achieves good plotting dimension accuracy even for a fine pattern plotting where regions having different exposure area ratios are present in an admixing manner.

Abstract: Masks for fabricating a semiconductor device and methods of forming mask patterns are provided which are capable of enhancing the breakdown voltage of the fabricated semiconductor device by accurately correcting a line width pattern error of a semiconductor substrate due to a mask error during a process for forming a well ion implantation mask pattern. A disclosed mask used to manufacture a semiconductor device having complementary N-well and P-well includes: a master mask for the complementary N-well and P-well; and a light-blocking pattern on the master mask, wherein a region of the master mask, which is not a portion of the master mask adjacent to the light-blocking pattern, is etched by a predetermined thickness to have a phase shifting function.

Abstract: The present disclosure relates generally to the manufacturing of semiconductor devices, and more particularly to semiconductor manufacturing using a vacuum chamber. In one example, a method for semiconductor manufacturing includes: providing a photoresist layer for a wafer; removing solvent residues from the photoresist layer by using a vacuum chamber; and exposing the wafer.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A high-precision patterning is conducted with a half-tone resist thickness being prevented from varying due to the presence/absence of a base film. A transmitting portion and two kinds of semi-transmitting portions, providing different quantities of transmitted light, are provided in a photomask for exposing a resist, and a smaller-transimitting-light-quantity semi-transmitting portion is used in a base film-present area and a large-transmitting light-quantity semi-transmitting portion is used in a base-film-free area to regulate luminous exposure while exposing, thereby forming a half-tone resist having uniform thickness.

Abstract: An advantage of the present invention is to provide a method of manufacturing an array substrate for a liquid crystal display device in which a mask that has double slits in it is used in the photolithographic masking process for the pixel electrode to reduce the distance between a pixel electrode and a neighboring pixel electrode and thus reduce the width of a data line, which results in an improvement of the aperture ratio.

Abstract: In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.

Abstract: A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask has a plurality of thicknesses and blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semiconductor substrate. The second mask covers the semi-insulating region. The semi-insulating region is implanted with a high energy beam of particles by utilizing the second mask and the first mask as particle hindering masks. Finally, the second mask is removed.

Abstract: A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit region has transistors. A precise layer having a plurality of first openings is formed in the memory cell region. The first openings are above the channel region of each memory cell in the memory cell array and the critical dimension of the first openings is identical. A mask layer having second openings and third openings is formed on the substrate. The second openings locate over a pre-coding memory cell region, and the third openings locate over the transistor gates. An ion implantation is performed to code the memory cell in the pre-coding memory cell region and to adjust the threshold voltage of the transistor, using the precise layer and the mask layer as a mask.

Abstract: After forming a resist film made from a chemically amplified resist material, pattern exposure is carried out by selectively irradiating the resist film with exposing light while supplying, onto the resist film, water that includes triphenylsulfonium nonaflate, that is, an acid generator, and is circulated and temporarily stored in a solution storage. After the pattern exposure, the resist film is subjected to post-exposure bake and is then developed with an alkaline developer. Thus, a resist pattern made of an unexposed portion of the resist film can be formed in a good shape.

Abstract: In an electron beam lithography apparatus, when a plotting pattern is an isolated fine pattern, an exposure energy upon plotting lacks. In the prior art set forth above, dimension dependent exposure energy correction is performed as a measure, however, a problem is encountered in that excessive exposure is caused in regions where the exposure area ratio is high. The present invention solves the problem in the foregoing prior art and provides an electron beam lithography apparatus and a lithography method using an electron beam which achieves good plotting dimension accuracy even for a fine pattern plotting where regions having different exposure area ratios are present in an admixing manner.

Abstract: An exposure apparatus for irradiating exposure light onto a surface of an object to be exposed applied with a resist to form a pattern on the surface, wherein near-field light is used as the exposure light. The apparatus includes an alignment system for performing alignment using the near-field light, the alignment system detecting position information of the object to be exposed by irradiating light from an illumination device onto an alignment mark formed on the surface of the object to be exposed, and an alignment probe for detecting near-field light in the vicinity of the alignment mark.

Abstract: A method for forming a minute pattern includes forming a mask layer on an object being patterned. The mask layer is patterned to form a first mask pattern having a first width larger than a predetermined width. The first mask pattern is thermally treated to form a second mask pattern having a second width smaller than the first width. A polymer layer is formed on the second mask pattern. The polymer layer reacts with the second mask pattern to form a hardened layer on a boundary surface between the polymer layer and the second mask pattern, thereby forming a third mask pattern having a third width substantially identical to the predetermined width. The limits of the present photolithography equipment are overcome. Also, a semiconductor device having a CD of below about 100 nm is manufactured.

Abstract: In a semiconductor integrated circuit device including a plurality of semiconductor devices formed on a substrate, the principal plane of the substrate is partitioned into a plurality of device regions and into a plurality of routing regions each crossing a boundary between the plural device regions. A device group including one or more semiconductor devices among the plural semiconductor devices and a local interconnect for connecting the semiconductor devices included in the device group are disposed within the plural device regions. A global routing for connecting the device groups to each other is disposed within each of the plural routing regions.

Abstract: A method of forming a dual-layer resist and application thereof. With respect to the method of forming a dual-layer resist, first, a patterned first resist layer is formed on a substrate. Next, the first resist layer is cured so that the first resist layer does not dissolve in a resist solvent. Finally, a patterned second resist layer is formed on the cured first resist layer. The method of forming a dual-layer resist can be applied to mask ROM coding, hole formation and a dual damascene structure.

Abstract: A resist pattern for fabricating a microelectronic device is irradiated with an energy beam, raising the glass transition temperature of the upper parts of the resist pattern, then baked, causing a transition to a glassy state in lower parts of the resist pattern, which flow viscously so that the resist pattern assumes a tapered cross sectional shape. When this tapered resist pattern is used as an etching mask, tapered features can be formed in the device. In particular, tapered contact holes can be formed, providing an increased alignment tolerance and enabling the size of the device to be reduced.

Abstract: A method of fabricating a surface-emission type light-emitting device which emits light in a direction perpendicular to a semiconductor substrate, includes the following steps (a) to (e). (a) A step of forming a column-shaped section by etching at least a part of a multilayer film. (b) A step of forming a first resin layer so as to cover the column-shaped section. (c) A step of forming a second resin layer by changing the solubility of the first resin layer in a liquid. (d) A step of immersing, for a specific period of time, at least the column-shaped section and the second resin layer in a liquid in which the second resin layer dissolves, thereby removing the second resin layer at least in the area formed over the column-shaped section. (e) A step of forming an insulating layer by curing the second resin layer.

Abstract: The invention relates generally to lithographic patterning of very small features. In particular, the invention relates generally to patterning of semiconductor circuit features smaller than lithographically defined using either conventional optical lithography or next generation lithography techniques. The invention relates more particularly, but not by way of limitation, to lateral trimming of photoresist images.

Abstract: Disclosed is a method of forming the dual damascene pattern in the semiconductor device. After forming the trench, a photoresist pattern in which a via hole region is defined is formed by exposure and development processes in a state that a photoresist is thinly coated, in a dual damascene process for first forming the trench than a via hole. Therefore, the present invention can prevent degradation of resolution due to a thickness of a photoresist pattern in a trench region and improve reliability of the entire process by simultaneously smoothly performing an etching process even with a thin photoresist pattern due to a good etching tolerance property.

Abstract: A resist film is formed from a chemically amplified resist material including a base polymer having a protecting group released by a function of an acid, an acrylic compound and an acid generator that generates an acid when irradiated with light. The resist film is selectively irradiated with exposing light for pattern exposure, and is developed after the pattern exposure so as to form a resist pattern having a hole or groove opening. The size of the opening is reduced by irradiating the resist pattern with light with annealing.

Abstract: The manufacturing time of a mask is shortened. In a defect inspection of a mask having a light-shielding portion composed of a resist film, the presence or absence of defects, such as burr and film loss of a resist pattern on the mask, and foreign matters, etc. is inspected by reading optical information on either or both of reflection light and transmission light with respect to inspection light irradiated to the mask by the use of a foreign-matter inspection system. More specifically, in the inspection of the mask, it is possible to perform the defect inspection without performing a comparison inspection that requires a great amount of measuring time and advanced techniques. Therefore, the inspecting process of the mask can be simplified, and also the inspecting time of the mask can be shortened.

Abstract: Disclosed is a thin film transistor (TFT) for a liquid crystal display (LCD) and a method for manufacturing the same that allows the number of photomasks used in a photolithography process to be decreased as compared to conventional methods. A passivation film is formed as a single layered organic insulating film, and the number of needed exposure steps is reduced, so as to decrease the number of needed photomask sheets and thereby improve the efficiency of the TFT production process. Applications of the disclosed method include reflection and transmission composite type LCDs as well as a reflection type LCD.

Abstract: The present invention provides a method of forming a TFT and a reflective electrode having recesses or projections with reduced manufacturing cost and a reduced number of manufacturing steps, and provides a liquid crystal display device to which the method is applied. A photosensitive film 8 is formed on a metal film 7. Then, remaining portions 81, 82 and 83 are formed from the photosensitive film 8. Then, the metal film 7 is etched by using the remaining portions 81, 82 and 83 as masks. And then, a photosensitive film 9 and a reflective electrode film 10 are formed without removing the remaining portions 81, 82 and 83.

Abstract: To provide a chemical amplification type positive photoresist composition suited to resist patterning of a substrate presenting surface step differences, a method for manufacturing the semiconductor device employing this composition, and a semiconductor substrate. In a method for manufacturing a semiconductor device, a resist film is formed using a chemical amplification type positive photoresist composition, comprised of a base resin and a basic compound added to the base resin at a rate of 1 to 100 mmol to 100 g of the base resin, on a substrate halving surface step differences and into which the organic removing solution is deposited or oozed, and a predetermined area of the resist film is exposed to light to form a resist pattern.

Abstract: An ITO (indium tin oxide) layer and a negative photoresist are deposited sequentially on the substrate 100 having a gate wire, a storage wire, a data wire and a storage electrode. The negative photoresist is developed through front exposure and the ITO layer is etched to form a pixel electrode. Because the portions of negative photoresist exposed to light remain after development, pixel defects due to particles placed between pixel regions are reduced. Both the rear exposure and the front exposure may be used. In the rear exposure, it is difficult to remain the portions of the ITO layer at the positions corresponding to the contact portion of the drain electrode and the pixel electrode, the storage line, the gate pads and the data pads. Accordingly, the front exposure is then executed by using the first mask having openings thereon. The negative photoresist is developed, and the ITO layer is patterned.

Abstract: The invention is a process for reducing variations in CD from wafer to wafer. It begins by increasing all line widths in the original pattern data file by a fixed amount that is sufficient to ensure that all lines will be wider than the lowest acceptable CD value. Using a reticle generated from this modified data file, the pattern is formed in photoresist and the resulting CD value is determined. If this turns out be outside (above) the acceptable CD range, the amount of deviation from the ideal CD value is determined and fed into suitable software that calculates the control parameters (usually time) for an ashing routine. After ashing, the lines will have been reduced in width by the amount necessary to obtain the correct CD. A fringe benefit of this trimming process is that edge roughness of the photoresist lines is reduced and line feet are removed.

Abstract: An ITO (indium tin oxide) layer and a negative photoresist are deposited sequentially on the substrate 100 having a gate wire, a storage wire, a data wire and a storage electrode. The negative photoresist is developed through front exposure and the ITO layer is etched to form a pixel electrode. Because the portions of negative photoresist exposed to light remain after development, pixel defects due to particles placed between pixel regions are reduced. Both the rear exposure and the front exposure may be used. In the rear exposure, it is difficult to remain the portions of the ITO layer at the positions corresponding to the contact portion of the drain electrode and the pixel electrode, the storage line, the gate pads and the data pads. Accordingly, the front exposure is then executed by using the first mask having openings thereon. The negative photoresist is developed, and the ITO layer is patterned.