Abstract: A method for forming an etching mask structure on a substrate includes etching the substrate, laterally expanding the etching mask structure, and depositing a self-aligned metal layer that is aligned to the originally masked area. The etching can be isotropic or anisotropic. The self-aligned metal layer can be distanced from the original etching masked area based on the extent of the intentionally laterally expanded etching mask layer. Following metal deposition, the initial mask structure can be removed, thus lifting off the metal atop it. The etching mask structure can be a resist and can be formed using conventional photolithography materials and techniques and can have nearly vertical sidewalls. The lateral extension can include a silylation technique of the etching mask layer following etching. The above method can be utilized to form bipolar, hetero-bipolar, or field effect transistors.

Abstract: A process of fabricating a molecular electronic device that preserves the integrity of the active molecular layer of the electronic device during processing is described. In one aspect, a barrier layer is provided to protect a molecular layer sandwiched between a bottom wire layer and a top wire layer from degradation during patterning of the top wire layer. A molecular electronic device structure and a memory system that are formed from this fabrication process are described.

Abstract: Disclosed is a method for forming contact by using the ArF lithography technology using a low-k dielectric sacrifice layer. The method comprises forming a layer to be etched on the semiconductor substrate, successively forming a low-k dielectric sacrifice layer and a hard mask on the etched layer, forming an anti-reflective layer and a photoresist pattern on the hard mask by using ArF lithography technology, selectively etching the anti-reflective layer and the hard mask and simultaneously removing the photoresist pattern when etching the hard mask, forming a contact hole exposing a surface of the semiconductor substrate by etching the low-k dielectric sacrifice layer and the layer by using the hard mask as a mask and removing the hard mask and the low-k dielectric sacrifice layer.

Abstract: A process for the formation of a wiring pattern, which includes the steps of: exposing a resist through a photomask, the photomask having a pattern whose line width is equal to or less than a resolution limit; and developing the exposed resist to form a resist pattern having groove depressions on the surface thereof, the depressions not reaching the back of the resist pattern. The resist may be a positive resist in which case the resist pattern is formed on an underplate feed film; a plating metal is precipitated on the feed film in a region not covered by the resist pattern; the resist pattern is stripped after the precipitation; and the feed film is selectively removed in a region not covered by the plating metal. Alternatively, the resist may be a negative resist in which case the resist pattern is formed on a substrate; a metallic material is deposited on the resist pattern and the substrate; and the resist is stripped from the substrate to remove the overlying metallic material.

Abstract: The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of an dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane (CH3F)/oxygen (O2) etch chemistry is used to selectively remove the ARC layer without scratching and/or degradation of the dielectric layer, source/drain regions formed over the substrate, and a silicide layer formed atop stacked gate structures. The CH3F/O2 etch chemistry etches the ARC layer at a rate which is significantly faster than the etch rates of the dielectric layer, the source/drain regions and the silicide layer. In addition, by removing the ARC layer prior to the formation of tungsten contacts by filling of contact openings formed in the dielectric layer with tungsten, potential scratching of tungsten contacts due to ARC layer removal is eliminated.

Abstract: Polysilicon gates are formed with greater accuracy and consistency by depositing an antireflective layer of silicon oxime on the polysilicon layer before patterning. Embodiments also include depositing the polysilicon layer and the silicon oxime layer in the same tool.

Abstract: Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by reducing ARC loss during photoresist stripping associated with plural mask formation in the core memory cell region during patterning and ion implantations. Embodiments include sequentially etching the stacked gate electrode structure in the core memory cell region, photoresist stripping and etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, plural maskings and ion implantations are implemented in the core memory cell region with attendant photoresist strippings.

Abstract: A dual-gate cell structure with self-aligned gates. A polysilicon spacer forms a second gate (213) separated from a first gate (201), which is also polysilicon, by a dielectric layer (207). A drain region (219) and a source region (221) are formed next to the gates. In one embodiment, the second gate (213) acts as a floating gate in a flash cell. The floating gate may be programmed and erased by the application of appropriate voltage levels to the first gate (201), source (221), and/or drain (219). The self-aligned nature of the second gate (213) to the first gate (201) allows a very small dual-gate cell to be formed.

Abstract: Transparent electrodes of a plasma display panel is patterned from a transparent conductive layer by using a lift-off technique; a photo-resist mask is roughened through exposure to oxygen plasma before the deposition of the transparent conductive layer, and the rough surface causes the photo-resist mask to be partially uncovered with the transparent conductive layer, thereby allowing photo-resist remover to rapidly penetrate into the boundary between the photo-resist mask and a glass substrate.

Abstract: A method of forming a dielectric thin film pattern, comprises the steps of: depositing a dielectric thin film on a substrate having a resist pattern thereon by a vapor deposition method, wherein as a material for the dielectric thin film, at least one of CeO.sub.2, Sm.sub.2 O.sub.3, Dy.sub.2 O.sub.3, Y.sub.2 O.sub.3, TiO.sub.2, Al.sub.2 O.sub.3, and MgO is used; and removing the resist pattern whereby the dielectric thin film is patterned.

Abstract: A gate is formed by creating a wafer stack, that includes a gate conductive layer over a substrate layer, depositing a SiO.sub.x N.sub.y layer over the conductive layer to act as a bottom anti-reflective coating (BARC), and forming a resist mask on the SiO.sub.x N.sub.y layer. Next, the resist mask is isotropically etched to further reduce the critical dimensions of the gate pattern formed therein, and then the underlying BARC and wafer stack are etched to form a gate out of the conductive layer.

Abstract: A method of forming a bump electrode, comprises the steps of preparing an Si-substrate having a plurality of bonding pads, forming a core on a substantially central portion of the bonding pad on the substrate, forming a resist layer around the core, which has a greater plan-view shape than the core and is provided with an opening portion through which that portion of the bonding pad, which is located around the core, is exposed, and coating an electric conduction strip having a uniform thickness on peripheral and upper surfaces of the core and on that portion of the bonding pad, which is located around the core, by a plating method.

Abstract: A relatively simple method for providing relatively close spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) on a relatively uniform basis. An emitter and base layer are epitaxially grown on a substrate. An emitter mesa is patterned with an i-line negative photoresist using conventional photolithography. Baking before and after exposure is used to form a resist pattern with a re-entrant profile having about a 0.1 .mu.m resist overhang. The emitter layer is then etched with a wet etch and or isotropic dry etch to expose a portion of the base ohmic metal to make contact with the base. A second layer of an i-line negative photoresist is applied over the first photoresist. The second layer is used to pattern the base ohmic metal mask. The base ohmic metal is deposited by evaporation.

Abstract: A method for fabricating a CCD image sensor includes the steps of forming a P type well in a surface of a semiconductor substrate, forming a buried CCD (BCCD) in a surface of the P type well, forming an offset gate and a reset gate on the BCCD at a predetermined interval, forming a floating diffusion region in the BCCD between the offset gate and the reset gate, forming a mask layer on an entire surface of the semiconductor substrate to form a contact hole in the floating diffusion region, forming a metal layer on the entire surface of the semiconductor substrate including the contact hole, and selectively removing the metal layer on the mask layer together with the mask layer to form a floating gate in the contact hole.

Abstract: A method of forming an isolating region of a semiconductor device including the steps of: forming first insulating layers which vary in width on a substrate; forming trenches which vary in width on the substrate by using the first insulating layers as a mask; forming second insulating layers on the trenches and the first insulating layers; exposing the predetermined portions of the first insulating layers by etching the second insulating layers; and wet-etching the first insulating layers and the non-etched portions of the second insulating layers. In the present invention, an isolating region in the narrow trench is formed without voids by regulating the deposition/etching ratio during the formation of an insulating layer in a trench.

Abstract: A method for fabricating a periodic table group III-IV field-effect transistor device is described. The disclosed fabrication arrangement uses a single metallization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent semiconductor material secondary mask element, a mask element which can be grown epitaxially during wafer fabrication. The invention includes provisions for both an all optical lithographic process and a combined optical and electron beam lithographic process These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

Abstract: The present invention advantageously provides a method for forming a transistor in which silicide contact areas are formed to the junctions during fabrication of the transistor. The silicide contact areas may be formed using a single high temperature anneal since silicide forming near sidewalls of the gate oxide is prevented. In one embodiment, dopants are first forwarded into a lateral region of a silicon-based substrate to form an implant region. Then a silicide layer is formed across the implant region using a high temperature anneal. A sacrificial material is deposited across the silicide layer and the substrate. A contiguous opening is formed vertically through the sacrificial material and the silicide layer, exposing a portion of the substrate. Dopants of the type opposite to the dopants implanted previously are then implanted into the exposed substrate region to form a channel. Thus, the implant region is separated into source and drain regions having a channel interposed between them.

Abstract: Disclosed is a metal layer pattern forming method which easily allows lift-off. The thickness of the photoresist layer is not less than double the thickness of the metal layer, and the maximum temperature that the surface of the substrate to be processed attains ranges from 100.degree. C. to 150.degree. C. Through appropriate improvement of the quality of the photoresist layer, bonding to the background is prevented and the lift-off is facilitated.

Abstract: A device having, at least, a first film having a surface on which neither a natural oxide film nor impurity grains caused by a resist residue is or are present, and a conductive material layer formed on a surface adjacent to the surface of the first film, wherein an insulative compound film is formed on a surface of the conductive material layer by a surface reaction with the conductive material layer, and a predetermined second film required for an arrangement is formed on the surface of the first film.

Abstract: A method for controlling the spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) to obtain a relatively high gain (.beta.) with a low-parasitic base resistance. In a first method, after the emitter, base and collector layers are epitaxially grown on a substrate, a sacrificial layer is deposited on top of the emitter layer. The emitter mesa is patterned with a photoresist using conventional lithography. Subsequently, the sacrificial layer is etched to produce an undercut. The emitter layer is then etched and a photoresist is applied over the first photoresist used to pattern the emitter mesa, as well as the entire device. The top layer of photoresist is patterned with a conventional process for lift-off metalization, such that the final resist profile has a re-entrant slope. The base ohmic metal is deposited and then lifted off by dissolving both the second layer of photoresist, as well as the original photoresist over the emitter mesa.

Abstract: A method for forming a V-shaped gate electrode on a semiconductor substrate includes the following steps: A first gate opening is formed in a first resist between a source and a drain formed on a semiconductor substrate, and dummy openings are formed near both sides of the first gate opening. By baking the first resist, convex portions thereof which rise steeply are formed between the first gate opening and the dummy openings. A second resist is formed to overlay the first resist convex portions and the first gate opening. The second resist is removed from the first gate opening, and a second gate opening larger than the first gate opening is formed in the second resist above the first gate opening. Metal for the V-shaped gate electrode is deposited through the second gate opening on the sides of the first resist convex portions rising steeply from the bottom of the first gate opening.

Abstract: A method of forming a T-type gate electrode of a high-frequency transistor having excellent high-frequency power transfer characteristic with no concave portions and protrusions. A first resist pattern having a first relatively narrow opening is formed on a semiconductor substrate and a leg portion of the electrode is formed in the first opening by depositing electrode metal on the substrate. A second resist pattern having a second relatively wide opening is formed over the electrode leg portion for locating an exposed tip of the electrode leg portion in the bottom of the second opening and forming a head portion of the electrode by depositing electrode metal in the second opening. The head portion is etched for removing any protrusions formed on the head portion.

Abstract: A method of forming a high resolution metal pattern on a substrate. A temporary polyvinyl alcohol (10) layer underneath the photoresist layer (20) aids in removing the photoresist layer after plating. The photoresist is photodelineated in conventional manner to form a pattern (40). During photodelineation, the developing process for the resist does not completely remove the PVA (45) that lies directly under the removed resist, but instead reveals those portions of the polyvinyl alcohol layer. The substrate is then rinsed in a hot aqueous solution to effect removal of the revealed PVA portions, now exposing portions (40) of the substrate (15). Metal (50) is then electroplated to build up a metal circuitry pattern. The remaining portions of the photoresist and the PVA are then removed by a hot aqueous solution.

Abstract: A new method for forming an array of high aspect ratio field emitter for flat panel Field Emission Displays (FEDs) was accomplished. The method involves forming on an insulated substrate an array of parallel cathodes and then depositing a dielectric layer and forming a array of parallel gate electrodes essentially orthogonal to the array of cathode electrodes. Opening are then made in the upper gate electrodes and dielectric layer over the lower cathode electrodes. The field emitters with high aspect-ratios are then formed on the cathode by depositing an emitter material, such as molybdenum, in the opening while heating the substrate to high temperatures. The emitter material is removed elsewhere on the substrate by utilizing a release layer and thereby completing the gated field emitter. This high temperature method results in high aspect-ratio gated emitters that allow the inter-electrode dielectric layer to be increased and thereby improving the circuit performance.

Abstract: A liquid crystal display device is produced by effecting in the course of its production steps a resist-peeling method including the steps of (a) changing the quality of a resist layer on a substrate, (b) contacting the changed resist with a liquid containing 2-amino-1-ethanol, and (c) removing the liquid containing the thus peeled resist from the surface of the etched resist, and optionally, (d) regenerating a liquid containing 2-amino-1-ethanol by distillation from the liquid used in step (c) and reusing the regenerated liquid in step (b).

Abstract: A thin conformal passivating dielectric film is deposited by ECR-CVD on an IC chip comprising semiconductor devices each of which includes a sub-micron-width irregularly shaped gate electrode. A protective layer of patterned resist is formed overlying each passivated device. Additional dielectric material is then deposited by ECP-CVD, at a temperature below the glass transition temperature of the resist, on the surface of the chip. Subsequently, in a lift-off step, the patterned resist together with the additional dielectric material overlying the resist is removed from the chip.