Making Oxide-nitride-oxide Device Patents (Class 438/954)
  • Patent number: 9608091
    Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: March 28, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsuyoshi Mihara
  • Patent number: 8642374
    Abstract: An image sensor is described in which the imaging pixels have reduced noise by blocking nitridation in selected areas. In one example, a method includes forming a first and second gate oxide layer over a substrate, forming a layer of photoresist over the first gate oxide layer, applying nitridation to the photoresist and the second gate oxide layer such that the first gate oxide layer is protected from the nitridation by the photoresist, and forming a polysilicon gate over the first and second gate oxide layers.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: February 4, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Jeong-Ho Lyu, Sohei Manabe, Howard Rhodes
  • Patent number: 8441063
    Abstract: A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: May 14, 2013
    Assignee: Spansion LLC
    Inventors: Shenqing Fang, Tung-Sheng Chen, Chun Chen
  • Patent number: 8350344
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: January 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Min Son, Woon-Kyung Lee
  • Patent number: 8304352
    Abstract: According to an embodiment, there is provided a method of manufacturing a semiconductor device, including forming a nitride film by nitriding a surface of an underlying region having a semiconductor region containing silicon as a main component and an insulating region containing silicon and oxygen as a main component and adjacent to the semiconductor region, carrying out oxidation with respect to the nitride film to convert a portion of the nitride film which is formed on the insulating region into an oxide film and to leave a portion of the nitride film which is formed on the semiconductor region as at least part of a charge storage insulating film, forming a block insulating film on the charge storage insulating film, and forming a gate electrode film on the block insulating film.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: November 6, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Kazuhiro Matsuo, Yoshio Ozawa
  • Patent number: 8264088
    Abstract: A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: September 11, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sin Leng Lim, In Ki Kim, Jong Sung Park, Min Hwan Kim, Wei Lu
  • Patent number: 8198671
    Abstract: A flash memory device comprises a substrate comprising silicon with a silicon dioxide layer thereon. A silicon-oxygen-nitrogen layer is on the silicon dioxide layer, and the silicon-oxygen-nitrogen layer comprises a shaped concentration level profile of oxygen through the thickness of the layer. A blocking dielectric layer is on the silicon-oxygen-nitrogen layer, and a gate electrode is on the blocking dielectric layer. Oxygen ions can be implanted into a silicon nitride layer to form the silicon-oxygen-nitrogen layer.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: June 12, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Christopher Sean Olsen, Tze Wing Poon, Udayan Ganguly, Johanes Swenberg
  • Patent number: 8148770
    Abstract: A memory device includes a number of memory cells and a bit line structure coupled to a group of the memory cells. The bit line structure includes an upper portion having a first width, and a lower portion having a second width, where the first width is less than the second width.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: April 3, 2012
    Assignee: Spansion LLC
    Inventors: Shankar Sinha, Timothy Thurgate
  • Patent number: 8129243
    Abstract: Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Such memory cells also allow multiple bit storage. These characteristics allow such memory cells to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: March 6, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 8125012
    Abstract: Performance of a non-volatile semiconductor storage device which performs electron writing by hot electrons and hole erasure by hot holes is improved. A non-volatile memory cell which performs a writing operation by electrons and an erasure operation by holes has a p-type well region, isolation regions, a source region, and a drain region provided on an Si substrate. A control gate electrode is formed via a gate insulating film between the source region and the drain region. In a left-side side wall of the control gate electrode, a bottom Si oxide film, an electric charge holding film, a top Si oxide film, and a memory gate electrode are formed. The electric charge holding film is formed from an Si nitride film stoichiometrically excessively containing silicon.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: February 28, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiyuki Mine, Kan Yasui, Tetsuya Ishimaru, Yasuhiro Shimamoto
  • Patent number: 7998831
    Abstract: A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: August 16, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Sin Leng Lim, In Ki Kim, Jong Sung Park, Min Hwan Kim, Wei Lu
  • Patent number: 7947607
    Abstract: A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: May 24, 2011
    Assignee: Macronix International Co., Ltd.
    Inventor: Chao-I Wu
  • Patent number: 7943495
    Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate, and forming a recess over the semiconductor substrate by etching the ONO layer, forming a vertical structure pattern being higher than the ONO layer over the recess, sequentially forming a spacer oxide film and a first gate poly over the side wall of the vertical structure pattern, and forming a nitride film spacer at a partial region of the side wall of the first gate poly, removing the nitride film spacer, and forming a second gate poly in a spacer shape over the side wall of the first gate poly, and forming a first split gate and a second split gate, symmetrically divided from each other, by removing the vertical structure pattern.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: May 17, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Hee-Don Jeong
  • Patent number: 7923363
    Abstract: Method of manufacturing a non-volatile memory device on a semiconductor substrate in a memory area, said non-volatile memory device comprising a cell stack of a first semiconductor layer, a charge trapping layer and an electrically conductive layer, the charge trapping layer being the intermediate layer between the first semiconductor layer and the electrically conductive layer, the charge trapping layer comprising at least a first insulating layer; the method comprising: —providing the substrate having the first semiconductor layer; —depositing the charge trapping layer; —depositing the electrically conductive layer; —patterning the cell stack to form at least two non-volatile memory cells, and —creating a shallow trench isolation in between said at least two non-volatile memory cells.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: April 12, 2011
    Assignee: NXP B.V.
    Inventors: Pierre Goarin, Robertus Theodorus Fransiscus Van Schaijk
  • Patent number: 7919372
    Abstract: A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: April 5, 2011
    Assignee: Macronix International, Co. Ltd.
    Inventors: Chih-Hao Wang, Hsin-Huei Chen, Chong-Jen Huang, Kuang-Wen Liu, Jia-Rong Chiou, Chong-Mu Chen
  • Patent number: 7915123
    Abstract: A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: March 29, 2011
    Assignee: Spansion LLC
    Inventors: Chungho Lee, Hiroyuki Kinoshita, Kuo-Tung Chang, Amol Joshi, Kyunghoon Min, Chi Chang
  • Patent number: 7829450
    Abstract: In a method of processing a contact pad, a passivation layer stack including at least one passivation layer is formed on at least an upper surface of a contact pad region. A first portion of the passivation layer stack is removed from above the contact pad region, wherein a second portion of the passivation layer remains on the contact pad region and covers the contact pad region. An adhesion layer is formed on the passivation layer stack. The adhesion layer is patterned, wherein the adhesion layer is removed from above the contact pad region. Furthermore, the second portion of the passivation layer stack is removed.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: November 9, 2010
    Assignee: Infineon Technologies AG
    Inventors: Markus Hammer, Guenther Ruhl, Andreas Strasser, Michael Melzl, Reinhard Goellner, Doerthe Groteloh
  • Patent number: 7824991
    Abstract: A MOSFET fabrication process comprises nitridation of the dielectric silicon interface so that silicon-dangling bonds are connected with nitrogen atoms creating silicon—nitrogen bonds, which are stronger than silicon-hydrogen bonds. A tunnel dielectric is formed on the substrate. A nitride layer is then formed over the tunnel dielectric layer. The top of the nitride layer is then converted to an oxide and the interface between the substrate and the tunnel dielectric is nitrided simultaneously with conversion of the nitride layer to oxide.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: November 2, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Yen-Hao Shih, Shih-Chin Lee
  • Patent number: 7799638
    Abstract: The invention is directed to a method for forming a memory array. The method comprises steps of providing a substrate having a charge trapping structure formed thereon. A patterned material layer is formed over the substrate and the patterned material layer having a plurality of trenches expose a portion of the charge trapping structure. Furthermore, a plurality of conductive spacers are formed on the sidewalls of the trenches of the patterned material layer respectively and a portion of the charge trapping structure at the bottom of the trenches is exposed by the conductive spacers. An insulating layer is formed over the substrate to fill up the trenches of the patterned material layer. Moreover, a planarization process is performed to remove a portion of the insulating layer until a top surface of the patterned material layer and a top surface of each of the conductive spacers are exposed.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: September 21, 2010
    Assignee: MACRONIX International Co., Ltd
    Inventors: I-Chen Yang, Yao-Wen Chang, Tao-Cheng Lu
  • Patent number: 7781291
    Abstract: A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: August 24, 2010
    Assignee: Panasonic Corporation
    Inventors: Nobuyoshi Takahashi, Satoshi Iwamoto, Fumihiko Noro, Masatoshi Arai
  • Patent number: 7745349
    Abstract: A method for fabricating a semiconductor transistor which eliminates device defects generated during an etching process for forming gates. The method may include laminating an ONO layer on and/or over a semiconductor substrate, and then coating a polysilicon layer on and/or over the ONO layer, and then forming a photoresist pattern on and/or over the polysilicon layer, and then sequentially performing a first etching of the polysilicon layer using the photoresist pattern as an etching mask so as to maintain a predetermined thickness of the polysilicon layer and then a second etching to remove the polysilicon layer remaining from the first etching.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: June 29, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jeong-Yel Jang
  • Patent number: 7709321
    Abstract: A flash memory and a flash memory fabrication method for increasing the coupling ratio by HSG including forming a STI region on a silicon substrate to define an active region, forming a tunneling oxide layer on the active region, and depositing an amorphous silicon layer on the silicon substrate. The method also includes patterning the amorphous silicon layer along a bit line direction, forming an embossed silicon layer including HSGs on the patterned amorphous silicon layer, and sequentially depositing an ONO layer and a polysilicon layer for a control gate on the resulting structure. The method further includes forming a photoresist pattern on the polysilicon layer, and forming a control gate by etching the polysilicon layer using the photoresist pattern as a mask, and simultaneously forming a floating gate along the bit line.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: May 4, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jin Hyo Jung
  • Patent number: 7700437
    Abstract: In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: April 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-chul Kim, Geum-jong Bae, In-wook Cho, Byoung-jin Lee, Jin-hee Kim
  • Patent number: 7682905
    Abstract: A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: March 23, 2010
    Assignee: Spansion LLC
    Inventor: Suketu Arun Parikh
  • Patent number: 7670963
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: March 2, 2010
    Assignee: Cypress Semiconductor Corportion
    Inventors: Krishnaswamy Ramkumar, Sagy Levy
  • Patent number: 7629640
    Abstract: Charge migration in a SONOS memory cell is eliminated by physically separating nitride layer storage sites with dielectric material. Increased storage in a cell is realized with a double gate structure for controlling bit storage in line channels between a source and a drain, such as with a FinFET structure in which the gates are folded over the channels on sides of a fin.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: December 8, 2009
    Assignee: The Regents of the University of California
    Inventors: Min She, Tsu-Jae King
  • Patent number: 7618853
    Abstract: A field effect transistor (FET) device includes a gate conductor and gate dielectric formed over an active device area of a semiconductor substrate. A drain region is formed in the active device area of the semiconductor substrate, on one side of the gate conductor, and a source region is formed in the active device area of the semiconductor substrate, on an opposite side of the gate conductor. A dielectric halo or plug is formed in the active area of said semiconductor substrate, the dielectric halo or plug disposed in contact between the drain region and a body region, and in contact between the source region and the body region.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: November 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Belyansky, Dureseti Chidambarrao, Oleg Gluschenkov
  • Patent number: 7611948
    Abstract: A method of forming a non-volatile memory device includes forming first mask patterns, which can have relatively large distances therebetween. A distance regulating layer is formed that conformally covers the first mask patterns. Second mask patterns are formed in grooves on the distance regulating layer between the first mask patterns.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: November 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hwang Sim, Yong-Sik Yim, Ki-Nam Kim, Jae-Kwan Park
  • Patent number: 7592232
    Abstract: A method for manufacturing a semiconductor device, includes the steps of forming a dummy gate insulating film and a dummy gate electrode, forming source and drain regions, forming a first insulating film, forming a second insulating film, removing the second insulating film, simultaneously removing the first insulating film and the second insulating film that remains, while planarizing the first insulating film and the second insulating film that remains, forming a gate electrode trench by removing the dummy gate electrode and the dummy gate insulating film, forming a gate insulating film, and forming a gate electrode, wherein a field effect transistor is formed by the method.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: September 22, 2009
    Assignee: Sony Corporation
    Inventor: Tomoyuki Hirano
  • Patent number: 7566660
    Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a gate on a semiconductor substrate; sequentially stacking a first oxide layer, a nitride layer and a second oxide layer on the semiconductor substrate including the gate; forming a first photoresist layer pattern on the second oxide layer; forming a second oxide layer pattern by wet etching the second oxide layer by using the first photoresist layer pattern as a mask; forming a nitride layer pattern by dry etching the nitride layer using the second oxide layer pattern as a mask; and forming a first oxide layer pattern by etching the first oxide layer using the nitride layer pattern as a mask.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: July 28, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Keun Soo Park
  • Patent number: 7560386
    Abstract: A method of manufacturing a nonvolatile semiconductor memory device may include forming a pad oxide layer pattern and a mask pattern on a semiconductor substrate, forming a trench within the semiconductor substrate with the mask pattern functioning as an etching mask, sequentially forming a first device isolation layer and a second device isolation layer that may fill the trench, forming an opening by removing the mask pattern to expose an upper surface of the pad oxide layer pattern and a sidewall of the second device isolation layer, and forming a floating gate forming region having a width wider than the opening by simultaneously removing the pad oxide layer pattern and a sidewall portion of the second device isolation layer exposed by the opening.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: July 14, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-hoon Cha, Woo-gwam Shim, Dong-gyun Han, Chang-ki Hong, Seung-pil Chung
  • Patent number: 7538385
    Abstract: A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: May 26, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoo-Cheol Shin, Jeong-Hyuk Choi, Sung-Hoi Hur
  • Patent number: 7528038
    Abstract: The invention relates to a nonvolatile semiconductor memory cell and to an associated fabrication method, a source region (7), a drain region (8) and a channel region lying in between being formed in a substrate (1). In order to realize locally delimited memory locations (LB, RB), an electrically non-conductive charge storage layer (3) situated on a first insulation layer (2) is divided by an interruption (U), thereby preventing, in particular, a lateral charge transport between the memory locations (LB, RB) and significantly improving the charge retention properties.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: May 5, 2009
    Assignee: Infineon Technologies AG
    Inventors: Franz Schuler, Georg Tempel
  • Patent number: 7510935
    Abstract: In an embodiment, a method of manufacturing a charge-trapping dielectric and a silicon-oxide-nitride-oxide-silicon (SONOS)-type non-volatile semiconductor device includes forming the charge-trapping dielectric, and a first oxide layer including silicon oxide. A silicon nitride layer including silicon-rich nitride is formed by a cyclic chemical vapor deposition (CVD) process using a silicon source material and a nitrogen source gas. A second oxide layer is formed on the silicon nitride layer. Hence, the charge-trapping dielectric having good erase characteristics is formed. In the SONOS-type non-volatile semiconductor device including the charge-trapping dielectric, a data erase process may be stably performed.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: March 31, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hae Lee, Ju-Wan Lim, Jae-Young Ahn, Sang-Ryol Yang, Ki-Hyun Hwang
  • Patent number: 7482236
    Abstract: A gate stack is formed on a substrate. The gate stack has a sidewall. An oxide-nitride-oxide material is deposited on the gate stack. Portions of the oxide-nitride-oxide material are removed to form an oxide-nitride-oxide structure. The oxide-nitride-oxide structure has a generally L-shaped cross-section with a vertical portion along at least part of the gate stack sidewall and a horizontal portion along the substrate. A top oxide material is deposited over the substrate. A silicon nitride spacer material is deposited over the top oxide material. Portions of the top oxide material and the silicon nitride spacer material are removed to form a silicon nitride spacer separated from the oxide-nitride-oxide stack by the top oxide material. Source/drain regions are formed in the substrate.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: January 27, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzyh-Cheang Lee, Fu-Liang Yang, Jiunn-Ren Hwang, Tsung-Lin Lee
  • Patent number: 7482623
    Abstract: An organic semiconductor device includes a substrate, a gate electrode formed directly on the substrate , gate insulating film formed directly on the gate electrode, a source electrode and a drain electrode formed directly on the gate insulating film, an organic semiconductor layer formed directly on the source electrode and the drain electrode, and a voltage control layer disposed directly between the gate insulating film and the organic semiconductor layer and directly contacting the source electrode and the drain electrode, wherein the voltage control layer gives an ambipolar characteristic to the organic semiconductor layer.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: January 27, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Takao Nishikawa, Yoshihiro Iwasa, Shin-ichiro Kobayashi, Taishi Takenobu
  • Patent number: 7452775
    Abstract: A non-volatile memory device having a substrate, an n type well, a p type well, a control gate, a composite dielectric layer, a source region and a drain region is provided. A trench is formed in the substrate. The n type well is formed in the substrate. The p type well is formed in the substrate above the n type well. The junction of p type well and the n type well is higher than the bottom of the trench. The control gate which protruding the surface of substrate is formed on the sidewalls of the trench. The composite dielectric layer is formed between the control gate and the substrate. The composite dielectric layer includes a charge-trapping layer. The source region and the drain region are formed in the substrate of the bottom of the trench respectively next to the sides of the control gate.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: November 18, 2008
    Assignee: Powership Semiconductor Corp.
    Inventors: Wei-Zhe Wong, Ching-Sung Yang, Chih-Chen Cho
  • Patent number: 7405119
    Abstract: A system and method for a sidewall SONOS memory device is provided. An electronic device includes a non-volatile memory. A substrate includes source/drain regions. A gate stack is directly over the substrate and between the source/drain regions. The gate stack has a sidewall. A nitride spacer is formed adjacent to the gate stack. A first oxide material is formed directly adjacent the spacer. An oxide-nitride-oxide structure is formed between the spacer and the gate stack. The oxide-nitride-oxide structure has a generally L-shaped cross-section on at least one side of the gate stack. The oxide-nitride-oxide structure includes a vertical portion and a horizontal portion. The vertical portion is substantially aligned with the sidewall and located between the first oxide material and the gate sidewall. The horizontal portion is substantially aligned with the substrate and located between the first oxide and the substrate.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: July 29, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzyh-Cheang Lee, Fu-Liang Yang, Jiunn-Ren Hwang, Tsung-Lin Lee
  • Patent number: 7374635
    Abstract: A gate insulation film (104) of a MISFET (100) is constituted of a silicon oxide film (106), silicon nitride film (107), and high-permittivity film (108). The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: May 20, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Shigemi Murakawa, Toshikazu Kumai, Toshio Nakanishi
  • Publication number: 20080076254
    Abstract: Yield loss in semiconductor processing is mitigated by forming a resist over an active side of a semiconductor workpiece or wafer, as well as around the edge of the wafer. The resist mitigates the creation of contaminants, such as nitride flakes, for example, that can develop when an oxide, nitride, oxide (ONO) layer is removed from the back or in-active side of the wafer. In the absence of the resist, such flakes may migrate to the front or active side of the wafer and cause defects to form therein, which can result in yield loss.
    Type: Application
    Filed: September 27, 2006
    Publication date: March 27, 2008
    Inventors: Scott Cuong Nguyen, Keith David Fenstermacher, David Michael Smith, Courtney Michael Hazelton
  • Patent number: 7338850
    Abstract: A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to prevent the generation of a electron trap which causes trapping of electrons at the interface of the oxide film and the nitride film resulting in a HEIP phenomenon.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: March 4, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Don Lee
  • Publication number: 20080042191
    Abstract: A method of fabricating a non-volatile memory device is provided. The method includes forming a plurality of trenches in a substrate. The trenches are filled with first conducting layers to serve as buried bit lines. Thereafter, a charge storage layer is formed on the substrate to cover the surface of the substrate and the first conducting layers. A plurality of second conducting layers is formed on the charge storage layer to serve as word lines.
    Type: Application
    Filed: August 21, 2006
    Publication date: February 21, 2008
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Cheng-Wei Lin, Kuang-Wen Liu, Hsin-Huei Chen
  • Patent number: 7323384
    Abstract: A method of manufacturing a semiconductor memory device comprises the steps of: preparing a semiconductor substrate having a gate insulation film and a gate electrode, the gate insulation film being formed on a predetermined active region in the semiconductor substrate, and the gate electrode being formed on the gate insulation film; forming a first insulation film covering the gate electrode and at least a part of the semiconductor substrate; charging the first insulation film; and forming a second insulation film for charge storage on the first insulation film.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: January 29, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Keiichi Hashimoto
  • Patent number: 7303959
    Abstract: A bottom-gate thin film transistor having a silicide gate is described. This transistor is advantageously formed as SONOS-type nonvolatile memory cell, and methods are described to efficiently and robustly form a monolithic three dimensional memory array of such cells. The fabrication methods described avoid photolithography over topography and difficult stack etches of prior art monolithic three dimensional memory arrays of charge storage devices. The use of a silicide gate rather than a polysilicon gate allows increased capacitance across the gate oxide.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: December 4, 2007
    Assignee: Sandisk 3D LLC
    Inventor: S. Brad Herner
  • Patent number: 7288452
    Abstract: A method of manufacturing a semiconductor device including forming an ONO film on a semiconductor substrate and a hard mask layer on the ONO film, forming a trench by etching the hard mask layer and the ONO film on a field region of the semiconductor substrate using a photo etch process and etching the field region of the semiconductor substrate, and forming a device separator at the trench. The method also includes exposing the ONO film by removing the hard mask layer on the ONO film, and leaving the ONO film only on a prospective SONOS gate in a cell region of the semiconductor substrate and removing the ONO film the remainder region thereof. The method further includes forming a gate oxide film on the semiconductor substrate at an outside of the ONO film, and forming a gate electrode on the gate oxide film and the ONO film, respectively.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: October 30, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Kae Hoon Lee
  • Patent number: 7262103
    Abstract: Disclosed is a method for forming salicide in a semiconductor device. The method comprises the steps of: forming a first and a second gate oxide film and in a non-salicide region and a salicide region, the first gate oxide film being thicker than the second gate oxide film; forming a conductive layer and a nitride based hard mask layer, and then selectively removing the conductive layer, the hard mask layer, the first gate oxide film, and the second gate oxide film, thereby forming gate electrodes and simultaneously exposing an active region of the salicide region; forming a spacer oxide film on an upper surface, except for the hard mask layer, of a second resultant structure; selectively removing the spacer oxide film, thereby forming a spacer and simultaneously exposing the active region of the salicide region; removing the hard mask layer; and forming a salicide film on the upper surfaces of the gate electrodes and on the surface of the active region in the salicide region.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: August 28, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Joon Hyeon Lee, Woon Yong Kim
  • Patent number: 7250337
    Abstract: A nonvolatile memory device and a method for fabricating the same is disclosed, to prevent a “smiling” phenomenon in an ONO layer, thereby improving the programming and erasing characteristics, reliability and yield. The device generally includes a semiconductor substrate; a gate insulating layer, a selection gate and a first insulating layer on the semiconductor substrate; an ONO layer formed on the semiconductor substrate including the selection gate; and a control gate formed on the ONO layer at least partially overlapping with the selection gate.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: July 31, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sang Bum Lee
  • Patent number: 7223658
    Abstract: A flash memory structure comprises a semiconductor substrate having a V-groove, a first doped region positioned in the semiconductor substrate, two second doped regions positioned in the semiconductor substrate and at two sides of the V-groove, a dielectric stack having trapping sites interposed therein positioned on the V-groove, and a conductive layer positioned on the surface of the dielectric stack above the V-groove. A method for forming the V-groove comprises steps of forming a mask layer on the surface of the semiconductor substrate, forming an opening in the mask layer, etching a portion of the semiconductor substrate below the opening to form the V-groove, and removing the mask layer. The semiconductor substrate can be a (100)-oriented silicon substrate, and the V-groove has inclined surface planes with (111) orientation.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: May 29, 2007
    Assignee: Promos Technologies, Inc.
    Inventors: Jason Chen, Chien Kang Kao
  • Patent number: 7223659
    Abstract: A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: May 29, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoo-Cheol Shin, Jeong-Hyuk Choi, Sung-Hoi Hur
  • Patent number: 7205186
    Abstract: A system and method for suppressing sub-oxide formation during the manufacturing of semiconductor devices (such as MOSFET transistor) with high-k gate dielectric is disclosed. In one example, the MOSFET transistor includes a gate structure including a high-k gate dielectric and a gate electrode. In this example, the gate structure is covered with a nitride layer that is used to prevent oxygen from entering the structure during processing, yet is sufficiently thin to be effectively transparent to the processing.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: April 17, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Shang-Chih Chen