Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

Abstract: A method of forming a composite silicon oxide layer over a semiconductor device. The composite silicon oxide layer is formed between the semiconductor device and a doped silicate glass layer. The composite silicon oxide layer comprises two silicon oxide layers, each having a different silicon/oxide composition. The oxygen-rich oxide layer or silicon dioxide layer is formed directly above the semiconductor device, and the silicon-rich oxide layer is formed above the silicon dioxide layer next to the doped silicate glass layer. Both the silicon dioxide layer and the silicon-rich oxide layer are formed in the same plasma deposition chamber.

Abstract: A method of fabricating a preserve layer. A top metallic layer is formed over the substrate. Portions of the metallic layer and the substrate are removed to form a trench. A conformal pad oxide layer is formed over the substrate. A conformal first nitride layer is formed on the pad oxide layer. A spin-on glass layer is formed on the first nitride layer to fill the trench. An etching back step is performed to remove a portion of the spin-on glass layer. The remaining spin-on glass layer fills the trench to the surface of the first nitride layer above the top metallic layer. An oxide layer is formed over the substrate. A second nitride layer is formed on the oxide layer. A preserve layer comprising the pad oxide layer, the first nitride layer, the oxide layer, and the second nitride layer is formed.

Abstract: In one aspect, the current invention provides a method for reducing the source leakage of a semiconductor device. The method comprises the steps of stacked gate etch, thin oxide formation, SAS etch, spacer formation and source implant on the semiconductor substrate. In a second aspect, the current invention provides another method for reducing the source leakage of a semiconductor device. The method comprises the steps of stacked gate etch, first oxide layer formation, first source implant, annealing, SAS etch, second oxide layer formation, spacer formation, and second source implant. In yet another aspect, the current invention provides a novel semiconductor device. The semiconductor device is comprised of a stacked gate provided on a portion of a semiconductor substrate, a first oxide layer appended to the stacked gate, a second oxide layer formed on the first oxide layer and a spacer formed on the second oxide layer.

Abstract: A method of fabricating a semiconductor device includes nitriding a native oxide layer on a pattern of polysilicon layers to be used as the lower electrode of a capacitor in LPCVD equipment at a constant temperature in an environment of ammonia gas. A nitride layer is then deposited onto the nitrided native oxide layer in the in-situ state. An oxide layer is then deposited onto the entire nitride layer, and thereafter a pattern of upper electrodes are formed on the oxide layer, thereby shortening the period of time required for forming the entire nitride layer of the NO dielectric layer without any deterioration in the product quality.

Abstract: A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming an ONO structure to overlie the semiconductor substrate. Thereafter, a thin mask layer is formed to overlie the ONO structure to protect the ONO structure during a selective etch of a thick mask layer. The thick mask layer is formed to overlie the thin mask layer to protect the ONO structure during boron and arsenic implants. Thereafter, an etch process is performed in the ONO structure and a silicon oxide layer is formed to fill the etched area. A chemical-mechanical-polishing process is performed to planarize the silicon oxide layer and to form a planar surface continuous with an upper surface of the thick mask layer. The planarized silicon oxide layer functions as a bit-line oxide layer.

Abstract: A method of fabricating a dielectric layer is provided. A first oxide layer is formed on a polysilicon layer. A silicon-rich nitride layer is formed on a first oxide layer. A silicon-poor nitride layer is formed on the silicon-rich nitride layer. An oxidation step is performed on the silicon-poor nitride layer. A second oxide layer is formed on the silicon-poor nitride layer. The dielectric layer comprising a multiple nitride layer structure is formed.

Abstract: A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vapor deposition at a pressure of at least 1 Torr, a temperature of less than 700° C. and using feed gases comprising a silicon hydride and ammonia. The substrate with silicon nitride layer is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride over the doped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed over the silicon dioxide layer and the first electrode. In another implementation, a layer comprising undoped oxide is formed over a doped oxide layer.

Abstract: A floating memory device utilizing a composite oxide/oxynitride or oxide/oxynitride/oxide interpoly dielectric.

Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to an improved, graded, silicon oxynitride process step, in order to form an unconventional dielectric layer, having an adjustable effective dielectric constant, for the purpose of fabricating capacitors for both DRAM and Logic technologies. During the special CVD process for the oxynitride layer, its composition is varied such that three distinct regions are created in the direction of film growth. The dielectric property of the lower region is close to silicon oxide, the dielectric property of the upper region is close to silicon oxynitride and the dielectric property of the intermediate transition zone is between that of silicon oxide and oxynitride.

Abstract: The present invention provides a method for enhancing the reliability of a dielectric layer of a semiconductor wafer. The dielectric layer is formed above a silicon element. First, the method implants argon ions with a dosage of around 1015˜1016 ions/cm3 and an energy of around 3˜50 KeV into the silicon element to form an ion implantation layer. Then, the dielectric layer is formed on a predetermined area of the silicon element. The ion implantation layer prevents oxygen ions, impurities and charge carriers from converging on the surface of the silicon element so as to enhance the reliability of the dielectric layer.

Abstract: The present invention provides a process for forming a dopant barrier layer in a gate stack in a semiconductor device. In one advantageous embodiment, the process includes forming a gate oxide on a semiconductor substrate, forming a gate layer on the gate oxide, and forming an ultra thin (less than about 2.5 nm) silicon nitride dopant barrier layer between the gate oxide and the gate layer. The dopant barrier layer provides an excellent barrier to inhibit dopant diffusion through the gate oxide and into the p-channel during the formation of the source/drain areas. Moreover, the formation of this dopant barrier layer and the formation of the gate layer can easily be achieved in a single furnace, if so desired.

Abstract: A new method of forming differential gate oxide thicknesses for both high and low voltage transistors is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas by shallow trench isolation regions. A polysilicon layer is deposited overlying a tunneling oxide layer on the surface of the substrate. The polysilicon and tunneling oxide layers are removed except in the memory cell area. An ONO layer is deposited overlying the polysilicon layer in the memory cell area and on the surface of the substrate in the low voltage and high voltage areas. The ONO layer is removed in the high voltage area. The substrate is oxidized in the high voltage area to form a thick gate oxide layer. Thereafter, the ONO layer is removed in the low voltage area and the substrate is oxidized to form a thin gate oxide layer.

Abstract: The present invention relates to a semiconductor device and, more particularly, to a short-wavelength optoelectronic device and a method for fabricating the same. The optoelectronic device according to the present invention doesn't have to employ an ion implantation process and an ohmic contact to make the n-p junction in the WB compound semiconductor, providing a sufficient efficiency for display. The method according to the present invention comprises the step of a) forming a SiC:AlN super lattice multilayer by alternately forming a SiC epitaxial film and an AlN epitaxial film on a substrate, wherein the AlN film is formed and the SiC film is formed using a single source gas of 1,3disilabutane in an nitrogen plasma-assisted metalorganic molecular beam epitaxy system; and b) applying a thermal treatment to the SiC:AlN super lattice multilayer, thereby a mixed crystal compound having (SiC).sub.x (AlN).sub.1-x quantum wells obtained by a diffusion of SiC film and AlN.

Abstract: A process for fabricating an ONO structure for a MONOS type Flash cell having a core and a periphery includes providing a semiconductor substrate. A first silicon oxide layer is grown overlying the semiconductor substrate, and a silicon nitride layer is deposited overlying the silicon oxide layer. Before depositing a second silicon oxide layer of the ONO structure, a bit-line mask is performed for forming at least one bit-line at the core. Thereafter, an ONO mask is formed to protect the ONO structure during an etch of the periphery. After depositing and cleaning the masks for the bit-line formation and the periphery etch, the second silicon oxide layer is deposited to overlie the silicon nitride layer using an HTO deposition process. By depositing the second silicon oxide layer after forming the ONO and bit-line masks, degradation of the second silicon oxide layer is prevented, and the top silicon oxide layer maintains a high quality.

Abstract: In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer, wherein the second oxide layer is made by forming the second oxide layer by low pressure chemical vapor deposition at a temperature from about 600.degree. C. to about 850.degree. C. using SiH.sub.4 and N.sub.2 O and annealing in an N.sub.2 O atmosphere at a temperature from about 700.degree. C. to about 950.degree. C.

Abstract: In one embodiment, the present invention relates to a method of forming a flash memory cell involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer, wherein the second oxide layer is made by forming the second oxide layer by rapid thermal chemical vapor deposition at a temperature from about 780.degree. C. to about 820.degree. C. using SiH.sub.4 and N.sub.2 O and annealing in an N.sub.2 O atmosphere a temperature from about 980.degree. C. to about 1020.degree. C.

Abstract: The present invention intends to form multilayer interconnects without deteriorating the advantage of an organosiloxane film (an interlayer dielectric), i.e., the low dielectric constant. According to the present invention, an organosiloxane film, a silicon nitride film, an inorganic SOG film, and a photoresist pattern are formed on a first metal layer, in series. The inorganic SOG film is then etched with use of the photoresist pattern as a mask to transfer the photoresist pattern to the inorganic SOG film. The photoresist pattern is then removed by oxygen plasma treatment with use of the silicon nitride film as a protection mask for protecting the organosiloxane film. Subsequently thereto, the silicon nitride film and the organosiloxane film are etched with use of the inorganic SOG film to form a contact hole reaching the first metal layer. After removing the inorganic SOG film, a second metal layer is formed to contact with the first metal layer through the contact hole.

Abstract: A method for forming a silicon nitride/silicon oxide (NO) layer within a microelectronics fabrication, and the microelectronics fabrication having the silicon nitride/silicon oxide (NO) layer formed therein. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a first silicon nitride layer through a first deposition method. There is then formed upon the first silicon nitride layer a second silicon nitride layer through a second deposition method. Finally, there is annealed thermally in an oxidizing environment the first silicon nitride layer and the second silicon nitride layer to form therefrom a silicon nitride/silicon oxide (NO) layer.

Abstract: Dielectric structures of the type that might be used in DRAMs, other memory devices, and integrated thin film transistors include repeated silicon oxide/silicon nitride layers. For example, the dielectric structure may have a silicon oxide/silicon nitride/silicon oxide/silicon nitride/silicon oxide or "ONONO" layer structure. Such repeated layer structures exhibit higher levels of breakdown voltage than more conventional "ONO" structures. Most of the growth of the five layer ONONO or more complicated dielectric structure can be accomplished in a single furnace through a series of temperature steps performed under different gas ambients. A substrate having a polysilicon lower electrode is introduced to a furnace and a lowest layer of silicon oxide is grown on the polysilicon electrode in an ammonia ambient. A first silicon nitride layer is grown in NH.sub.3 and SiH.sub.2 Cl.sub.

Abstract: A method is provided for forming an improved device dielectric of a semiconductor integrated circuit, and an integrated circuit formed according to the same. For scaling geometries for use in the submicron regime, a composite dielectric layer used as a device dielectric is formed over a plurality of active areas adjacent to a field oxide region. The composite dielectric layer is formed before the field oxide region is formed and comprises a non-porous silicon nitride layer. The non-porous silicon nitride layer preferably comprises a thin deposited silicon nitride layer overlying a thin nitridized region of the substrate. The silicon nitride layer is partially oxidized during the subsequent formation of a field oxide region between the plurality of active areas. An oxide layer may be formed over the silicon nitride layer before the formation of the field oxide region which will then be densified during the field oxide formation.

Abstract: A flash memory cell, comprising: a composite insulating film formed on a substrate at a predetermined size which charges are trapped or detrapped; a drain formed at one side of the composite insulating film; a source formed a predetermined distance away the other side of the composite insulating film; a program/erasure gate formed on the composite insulating film; an interlayer insulating film for covering the drain, the source and the program/erasure gate; a selecting gate formed on the interlayer insulating film, which is programmable and erasable at low voltages and operable by application of a single power system. In the cell, the low voltages allow peripheral circuit to be designed easily and the chip size to be reduced. Further, the repeating number of the programming and erasing can be markedly increased since the flash memory cell employs a channel erasure manner as well as low powers. It is preventive of overerasure and thus can erase information more quickly.

Abstract: A tunnel oxide film is formed on the surface of a p-type silicon substrate, and a floating gate electrode made from a polysilicon film is formed on the surface of the tunnel oxide film. On the surface of the floating gate electrode, a control gate electrode is formed via an NON film formed by sequentially stacking a silicon nitride film, a silicon oxide film, and a silicon nitride film. A side oxide film is formed on the side surfaces of the floating gate electrode and the control gate electrode. Source and drain regions made from an n-type diffused layer are formed on the surfaces of element regions of the silicon substrate on the two sides of the floating gate electrodes.

Abstract: An improved antifuse design has been achieved by using a structure including a region of heavily doped N type silicon coated with a layer of ONO (oxide-nitride-oxide). Top contact to the ONO is made through a layer of tungsten silicide sandwiched between two layers of N type polysilicon. A cost effective method for manufacturing said antifuse structure is described.

Abstract: The present invention is directed to providing an electrostatic discharge ("ESD") protection cell for use in an integrated circuit device including antifuses. The ESD protection cell is formed simultaneously with the antifuses that it protects and provides protection from ESD during the fabrication of the antifuses. The concept is to use thin undoped or doped polysilicon on top of antifuse material as a block etching mask for the formation of the ESD protection cells by using common etching techniques. This polysilicon mask is placed where the antifuses will be and not where the ESD protection cells will be. The polysilicon mask is then merged with a top polysilicon electrode during later processing. During the block etching process, the antifuse material layer is compromised in the region about the ESD protection cells.

Abstract: An insulating layer in a semiconductor device and a process for forming the insulating layer is described. The insulating layer comprises of a nitride layer over the substrate having a residual stress of between -8.times.10.sup.9 dynes/cm.sup.-2 and -3.times.10.sup.10 dynes/cm.sup.-2. The insulating layer can further comprise a doped oxide layer under the nitride layer and can further comprise an interlevel dielectric layer over the nitride layer. Moreover, the nitride layer can be formed by bringing the temperature in a chemical vapor deposition reactor to below 550 degrees Celsius, placing the substrate into the reactor at the temperature, and forming the nitride layer on the substrate. Alternatively, the nitride layer can be formed by pushing the substrate into a chemical vapor deposition reactor at a speed greater than 300 millimeters per minute, and forming the nitride layer on the substrate.