Mechanical Polishing Of Wafer Patents (Class 438/959)
  • Patent number: 9023712
    Abstract: By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: May 5, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Roman Boschke, Markus Forsberg
  • Patent number: 9018024
    Abstract: An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Nathaniel C. Berliner, Kangguo Cheng, Jason E. Cummings, Toshiharu Furukawa, Jed H. Rankin, Robert R. Robison, William R. Tonti
  • Patent number: 9006010
    Abstract: Radiation detectors and methods of fabricating radiation detectors are provided. One method includes mechanically polishing at least a first surface of a semiconductor wafer using a polishing sequence including a plurality of polishing steps, wherein a last polishing step of the polishing sequence includes polishing with a slurry having a grain size smaller than about 0.1 ?m to create a polished first surface. The method also includes applying (i) an encapsulation layer on a top of the polished first surface to seal the polished first surface and (ii) a photoresist layer on top of the encapsulation layer on the polished first surface. The method further includes creating undercuts of the encapsulation layer under the photoresist layer. The method additionally includes partially etching the polished first surface of the semiconductor via the openings in the photoresist layer and in the encapsulation layer to partially etch the semiconductor creating etched regions.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: April 14, 2015
    Assignee: General Electric Company
    Inventors: Arie Shahar, Eliezer Traub, Diego Sclar, Peter Rusian
  • Patent number: 8999061
    Abstract: The method for producing a silicon epitaxial wafer according to the present invention has: a growth step G at which an epitaxial layer is grown on a silicon single crystal substrate; a first polishing step E at which, before the growth step G, both main surfaces of the silicon single crystal substrate are subjected to rough polishing simultaneously; and a second polishing step H at which, after the growth step G, the both main surfaces of the silicon single crystal substrate are subjected to finish polishing simultaneously.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: April 7, 2015
    Assignee: Sumco Corporation
    Inventors: Masayuki Ishibashi, Tomonori Miura
  • Patent number: 8884288
    Abstract: The present invention provides a semiconductor structure for testing MIM capacitors. The semiconductor structure comprises: a first metal layer comprising at least a first circuit area and a second circuit area; a second metal layer located below the first metal layer with a first dielectric layer lying therebetween and connected with the second circuit area; a top plate located within the first dielectric layer closer to the first metal layer and connected with the first circuit area; a bottom plate located within the first dielectric layer closer to the second metal layer and separated from the top plate with an insulation layer therebetween and connected with the second circuit area. The second metal layer is connected with the substrate through a first electric pathway so as to form a second electric pathway from the top plate to the substrate when an electric leakage region exists in the insulation layer.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 11, 2014
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Qiang Li, Zhuanlan Sun, Changhui Yang
  • Patent number: 8877643
    Abstract: This invention is to provide a method of polishing a silicon wafer wherein a high flatness can be attained likewise the conventional polishing method and further the occurrence of defects due to the remaining of substances included in the polishing solution on the surface of the wafer can be suppressed as well as a polished silicon wafer. The method of polishing a silicon wafer by supplying a polishing solution containing abrasive grains onto a surface of a polishing pad and then relatively sliding the polishing pad to a silicon wafer to polish the surface of the silicon wafer, is characterized in that the number of abrasive grains included in the polishing solution is controlled to not more than 5×1013 grains/cm3.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: November 4, 2014
    Assignee: Sumco Corporation
    Inventors: Shuhei Matsuda, Tetsuro Iwashita, Ryuichi Tanimoto, Takeru Takushima, Takeo Katoh
  • Patent number: 8846534
    Abstract: Embodiments of the present invention relate to reducing the size variation on a wafer fabrication. In some embodiments, at least a portion the backfill material over features larger than a threshold size is etched or milled to provide backfill protrusions over those features. The backfill protrusions are configured to reduce the size variation across the fabrication. Embodiments of the invention may be used in fabrication of many types of devices, such as tapered wave guides (TWG), near-field transducers (NFT), MEMS devices, EAMR optical devices, optical structures, bio-optical devices, micro-fluidic devices, and magnetic writers.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: September 30, 2014
    Assignee: Western Digital (Fremont), LLC
    Inventors: Yunfei Li, Ge Yi, Dujiang Wan, Guanghong Luo, Lijie Zhao, Yanfeng Chen, Lily Yao, Ming Jiang
  • Patent number: 8592316
    Abstract: A nitride semiconductor substrate includes two principal surfaces including an upper surface that is a growth face and a lower surface on its opposite side. An FWHM in a surface layer region at depths of from 0 to 250 nm from the upper surface is narrower than an FWHM in an inner region at depths exceeding 5 ?m from the upper surface, where the FWHMs are obtained by X-ray rocking curve measurement using diffraction off a particular asymmetric plane inclined relative to the upper surface.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: November 26, 2013
    Assignee: Hitachi Cable, Ltd.
    Inventors: Yuichi Oshima, Takehiro Yoshida
  • Patent number: 8552510
    Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: October 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Takamitsu Onda
  • Patent number: 8546244
    Abstract: A method includes the steps of: (a) fixing a front surface of a wafer (semiconductor wafer) having the front surface, a plurality of chip regions formed on the front surface, a dicing region formed between the chip regions, and a rear surface opposite to the front surface to the supporting member; (b) in a state of having the wafer fixed to the supporting member, grinding the rear surface of the wafer to expose the rear surface; (c) in a state of having the wafer fixed to the supporting member, dividing the wafer into the chip regions; (d) etching side surfaces of the chip regions to remove crushed layers formed in the step (c) on the side surfaces and obtain a plurality of semiconductor chips. After the steps (e) and (d), the plurality of divided chip regions are peeled off from the supporting member to obtain a plurality of semiconductor chips.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: October 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Toshihide Uematsu, Haruo Shimamoto
  • Patent number: 8530353
    Abstract: A method of manufacturing a SiC substrate which has a first principal surface and a second principal surface, includes the step of removing, by a vapor phase etching process, at least a portion of a work-affected layer which is formed by mechanical flattening or cutting on the first principal surface of the SiC substrate.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: September 10, 2013
    Assignee: Hitachi Metals, Ltd.
    Inventor: Taisuke Hirooka
  • Patent number: 8524537
    Abstract: A semiconductor device has a build-up interconnect structure formed over an active surface of a semiconductor wafer containing a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the interconnect structure. Bumps are formed over the interconnect structure. A protective coating material is deposited over the insulating layer and saw street. A lamination tape is applied over the coating material. A portion of a back surface of the semiconductor wafer is removed. A mounting tape is applied over the back surface. The lamination tape is removed while leaving the coating material over the insulating layer and saw street. A first channel is formed through the saw street extending partially through the semiconductor wafer. The coating material is removed after forming the first channel. A second channel is formed through the saw street and the mounting tape is removed to singulate the semiconductor wafer.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: September 3, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: JaEun Yun, HunTeak Lee, SeungYong Chai, WonJun Ko
  • Patent number: 8486805
    Abstract: A through-silicon via and a method for forming the same are provided. The method includes: providing a semiconductor substrate, the semiconductor substrate including an upper surface and an opposite lower surface; etching the upper surface of the semiconductor substrate to form an opening; filling the opening with a conductive material to form a first nail; etching the lower surface of the semiconductor substrate to form a recess, such that the first nail is exposed at a bottom of the recess; filling the recess with a conductive material that can be etched, and etching the conductive material that can be etched to form a second nail, such that the second nail is vertically connected with the first nail; and filling a gap between the second nail and the semiconductor substrate and a gap between the second nail and an adjacent second nail with a dielectric layer. Then invention can improve the reliability of through-silicon vias and avoid voids.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: July 16, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Chao Zhao, Dapeng Chen, Wen Ou
  • Patent number: 8481342
    Abstract: A method for manufacturing a semiconductor device, includes: a step of etching a Si (111) substrate along a (111) plane of the Si (111) substrate to separate a Si (111) thin-film device having a separated surface along the (111) plane.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: July 9, 2013
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Tomohiko Sagimori, Takahito Suzuki, Masataka Muto
  • Patent number: 8455983
    Abstract: Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: June 4, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Ed A. Schrock, Ford B. Grigg
  • Patent number: 8304345
    Abstract: The invention relates to improvements in the polishing of a layer of germanium by a method which includes a first step of chemical-mechanical polishing of the surface of the germanium layer that is carried out with a first polishing solution having an acidic pH. The first polishing step is then followed by a second step of chemical-mechanical polishing of the surface of the germanium layer carried out with a second polishing solution having an alkaline pH. The polished heteroepitaxial germanium layer has a surface microroughness of less than 0.1 nm RMS and a surface macroroughness corresponding to a surface haze level of less than 0.5 ppm.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: November 6, 2012
    Assignee: Soitec
    Inventors: Muriel Martinez, Pierre Bey
  • Patent number: 8187907
    Abstract: A method of manufacturing a solar cell by providing a first substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell including a top subcell and a bottom subcell; forming a metal back contact over the bottom subcell; forming a group of discrete, spaced-apart first bonding elements over the surface of the back metal contact; attaching a surrogate substrate on top of the back metal contact using the bonding elements; and removing the first substrate to expose the surface of the top subcell.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: May 29, 2012
    Assignee: Emcore Solar Power, Inc.
    Inventor: Fred Newman
  • Patent number: 8124471
    Abstract: A method of grinding a molded semiconductor package to a desired ultra thin thickness without damage to the package is disclosed. Prior to grinding a molded package to a desired package thickness, the package may be protected from excessive mechanical stress generated during grinding by applying a protective tape to enclose interconnects formed on the package. This way, the protective tape provides support to the semiconductor package during package grinding involving the mold material as well as the die. In the post-grind package, the grinded die surface may be exposed and substantially flush with the mold material. The protective tape may then be removed to prepare the post-grind package for connection with an external device or PCB.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: February 28, 2012
    Assignee: Intel Corporation
    Inventors: James-Yii Lee Kiong, Chong Hin Tan, Shivaram Sahadevan, Max Mah Boon Hooi, Tang Shiau Phing
  • Patent number: 8101523
    Abstract: A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 ?m-10 ?m thick edge process-induced degradation layer.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: January 24, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Hidenori Mikami, Naoki Matsumoto
  • Patent number: 8093137
    Abstract: A device layer is formed on at least the upper surface of a prime wafer by an epitaxial growth method. Then, a protective film is formed to cover at least the device layer. The lower surface of the prime wafer is ground to have a flat lower surface.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: January 10, 2012
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Masatsugu Desaki
  • Patent number: 8062958
    Abstract: Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: November 22, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Ed A. Schrock, Ford B. Grigg
  • Patent number: 8029335
    Abstract: In a wafer processing method, rough grinding using a first grinding stone is divided into first and second steps. In the first step, a wafer is processed into a concave shape at a first transfer rate with a reinforcing rib area slightly left. Thereafter, as primary rough grinding in the second step, the grinding stone is positioned slightly on the inner circumferential side and the wafer is further processed into the concave portion at a second transfer rate faster than the first transfer rate. Since the first transfer rate is suppressed to a rate not to cause a burst chipping, a burst chipping resulting from the second step fast in the processing rate to ensure productivity will occur at the stepped edge portion on the inside of the reinforcing rib area surface. Thus, the flatness of the reinforcing rib area can be ensured.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: October 4, 2011
    Assignee: Disco Corporation
    Inventors: Aki Takahashi, Masaaki Nagashima
  • Patent number: 8008165
    Abstract: Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: August 30, 2011
    Assignees: Sumitomo Electric Industries, Ltd., Sony Corporation
    Inventors: Masahiro Nakayama, Naoki Matsumoto, Koshi Tamamura, Masao Ikeda
  • Patent number: 7851381
    Abstract: A surface treatment method for a nitride crystal is a surface treatment method of chemically and mechanically polishing a surface of the nitride crystal. Oxide abrasive grains are used. The abrasive grains have a standard free energy of formation of at least ?850 kJ/mol as a converted value per 1 mole of oxygen molecules and have a Mohs hardness of at least 4. The surface treatment method efficiently provides, for efficiently obtaining a nitride crystal substrate that can be used for a semiconductor device, the nitride crystal having the smooth and high-quality surface formed thereon.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: December 14, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Takayuki Nishiura, Masato Irikura, Seiji Nakahata
  • Patent number: 7758402
    Abstract: A recessed portion is formed in an area, of a rear surface of a wafer, corresponding to a device formation area is formed by a rough grinding wheel of a rough grinding unit and an annular protruding portion is concurrently formed around the recessed portion. The inner circumferential lateral surface of the recessed portion is next ground by a finishing grinding wheel of a finishing grinding unit and the bottom surface is subsequently ground.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: July 20, 2010
    Assignee: Disco Corporation
    Inventors: Shinji Yoshida, Osamu Nagai
  • Patent number: 7737038
    Abstract: A method of fabricating a semiconductor device includes forming a conductive layer on an insulating layer having a plurality of trenches on a semiconductor substrate, such that the conductive layer fills in the plurality of trenches formed in the insulating layer, and calculating a target eddy current value to measure an end point using parameters of a pattern density and a depth of the trenches. The method further includes planarizing the conductive layer and measuring eddy current values on the conductive layer using an eddy current monitoring system, and stopping the planarization when the measured eddy current value reaches the target eddy current value to form a planarized conductive layer having a target height on the insulating layer.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: June 15, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Mahn Lee, Byung-Lyul Park, MooJin Jung
  • Patent number: 7727859
    Abstract: It is an object of the present invention to provide a semiconductor device in which a barrier property is improved; a compact size, a thin shape, and lightweight are achieved; and flexibility is provided. By providing a stacked body including a plurality of transistors in a space between a pair of substrates, a semiconductor device is provided, in which a harmful substance is prevented from entering and a barrier property is improved. In addition, by using a pair of substrates which are thinned by performing grinding and polishing, a semiconductor device is provided, in which a compact size, a thin shape, and lightweight are achieved. Further, a semiconductor device is provided, in which flexibility is provided and a high-added value is achieved.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: June 1, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventors: Yasuko Watanabe, Junya Maruyama, Yoshitaka Moriya
  • Patent number: 7682224
    Abstract: A method of machining a wafer is disclosed, in which the wafer is held by sucking its back-side surface directly onto a suction surface of a chuck table, and the tips of protruding electrodes and a resist layer are cut to make them flush with each other (appendant part cutting step). Next, the wafer is held by sucking the surface of the cut appendant part directly onto the suction surface of the chuck table, and the back-side surface of the wafer is ground (back-side surface grinding step), followed by removing the resist layer. The wafer is held onto the chuck table without using any protective tape but by directly holding the wafer, whereby the wafer can be ground to have a uniform thickness.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: March 23, 2010
    Assignee: Disco Corporation
    Inventors: Yusuke Kimura, Toshiharu Daii, Takashi Mori
  • Patent number: 7662672
    Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: February 16, 2010
    Assignees: ChipMos Technologies (Bermuda) Ltd., ChipMos Technologies Inc.
    Inventor: Hung-Tsun Lin
  • Patent number: 7659207
    Abstract: Epitaxially coated silicon wafers, are coated individually in an epitaxy reactor by placing a wafer on a susceptor, pretreating under a hydrogen atmosphere, in and then with addition of an etching medium, and coating epitaxially on a polished front side, wherein an etching treatment of the susceptor is effected after a specific number of epitaxial coatings, and the susceptor is then hydrophilized. Silicon wafer produced thereby have a maximum local flatness value SFQRmax of 0.01 ?m to 0.035 ?m relative to at least 99% of the partial regions of an area grid of measurement windows having a size of 26×8 mm2 on the front side of the silicon wafer with an edge exclusion of 2 mm.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: February 9, 2010
    Assignee: Siltronic AG
    Inventors: Reinhard Schauer, Thorsten Schneppensieper
  • Patent number: 7625810
    Abstract: A method of processing a wafer having a device area where a plurality of devices are formed on the front surface and an extra area surrounding the device area and comprising electrodes which are formed in the device area, comprising: a reinforcement forming step for removing an area, which corresponds to the device area, in the back surface of the wafer to reduce the thickness of the device area to a predetermined value and keeping an area, which corresponds to the extra area, in the back surface of the wafer to form an annular reinforcement; and a via-hole forming step for forming a via-hole in the electrodes of the wafer which has been subjected to the reinforcement forming step.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: December 1, 2009
    Assignee: Disco Corporation
    Inventors: Keiichi Kajiyama, Koichi Kondo, Yasuomi Kaneuchi
  • Patent number: 7625821
    Abstract: The present invention provides system and apparatus for use in processing wafers. The new system and apparatus allows for the production of thinner wafers that at same time remain strong. As a result, the wafers produced by the present process are less susceptible to breaking. The unique system also offers an improved structure for handling thinned wafers and reduces the number of processing steps. This results in improved yields and improved process efficiency.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: December 1, 2009
    Assignee: Semitool, Inc.
    Inventors: Kert L. Dolechek, Raymon F. Thompson
  • Patent number: 7554175
    Abstract: Fracture-resistant gallium nitride substrate, and methods of testing for and manufacturing such substrates are made available. A gallium nitride substrate (10) is provided with a front side (12) polished to a mirrorlike finish, a back side (14) on the substrate side that is the opposite of the front side (12). A damaged layer (16) whose thickness d is 30 ?m or less is formed on the back side (14). Given that the strength of the front side (12) is I1 and the strength of the back side (14) is I2, then the ratio I2/I1 is 0.46 or more.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: June 30, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Akihiro Hachigo
  • Patent number: 7541287
    Abstract: A semiconductor wafer is guided in a cutout in a carrier while a thickness of the semiconductor wafer is reduced to a target thickness by material removal from the front and back surfaces simultaneously. The semiconductor wafer is machined until it is thinner than a carrier body and thicker than an inlay used to line the cutout in the carrier to protect the semiconductor wafer. The carrier is distinguished by the fact that the carrier body and the inlay have different thicknesses throughout the entire duration of the machining of the semiconductor wafer, the carrier body being thicker than the inlay, by from 20 to 70 ?m. Themethod provides semiconductor wafers polished on both sides, having a front surface, a back surface and an edge, and a local flatness of the front surface, SFQRmax of less than 50 nm with an edge exclusion of R-2 mm and less than nm with an edge exclusion of R-1 mm, based on a site area of 26 by 8 mm.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: June 2, 2009
    Assignee: Siltronic AG
    Inventors: Ruediger Schmolke, Thomas Buschhardt, Gerhard Heier, Guido Wenski
  • Patent number: 7446423
    Abstract: In a semiconductor device provided with a thinned semiconductor element, the present invention intends to inhibit damage of the semiconductor element in the neighborhood of its outer periphery so as to improve reliability. A plurality of external connection terminals are formed on a front surface of the thinned semiconductor element. A plate higher in rigidity than the semiconductor element is adhered with a resin binder to a rear surface of the semiconductor element. An outer shape of the plate is made larger than that of the semiconductor element, and the resin binder covers a side face of the semiconductor element to form a reinforcement portion for reinforcing a periphery of the semiconductor element.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: November 4, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadahiko Sakai, Mitsuru Ozono, Yoshiyuki Wada
  • Patent number: 7366575
    Abstract: Methods of controlling polishing of wafers are disclosed. In one aspect, a method may include measuring one or more pre-polish thicknesses of one or more layers of a wafer. The one or more layers may then be polished. Then a post-polish thickness of a layer of the wafer may be measured. Polishing may be controlled by using feed-forward control with the one or more pre-polish thicknesses and by using feed-back control with the post-polish thickness. Machine-accessible software to perform such methods are also disclosed as are systems in which such methods may be implemented.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: April 29, 2008
    Assignee: Intel Corporation
    Inventors: Matthew A. Ring, Scot Goerutiz, Kimberly A. Ryglelski, Anju Narendra, Kevin E. Heldrich, Brook D. Ferney
  • Patent number: 7338882
    Abstract: A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: March 4, 2008
    Assignees: Siltron Inc.
    Inventors: Jea-Gun Park, Gon-Sub Lee, Sang-Hee Lee
  • Patent number: 7314823
    Abstract: A composition for chemical mechanical polishing includes a slurry. A sufficient amount of a selectively oxidizing and reducing compound is provided in the composition to produce a differential removal of a metal and a dielectric material. A pH adjusting compound adjusts the pH of the composition to provide a pH that makes the selectively oxidizing and reducing compound provide the differential removal of the metal and the dielectric material. A composition for chemical mechanical polishing is improved by including an effective amount for chemical mechanical polishing of a hydroxylamine compound, ammonium persulfate, a compound which is an indirect source of hydrogen peroxide, a peracetic acid or periodic acid. A method for chemical mechanical polishing comprises applying a slurry to a metal and dielectric material surface to produce mechanical removal of the metal and the dielectric material.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: January 1, 2008
    Assignee: DuPont Airproducts NanoMaterials LLC
    Inventors: Robert J. Small, Laurence McGhee, David J. Maloney, Maria L. Peterson
  • Patent number: 7300876
    Abstract: A method is provided to clean slurry particles from a surface in which tungsten and dielectric are coexposed after a dielectric CMP step. Such a surface is formed when tungsten features are patterned and etched, the tungsten features are covered with dielectric, and the dielectric is planarized to expose tops of the tungsten features. The surface to be cleaned is subjected to mechanical action in an acid environment. Suitable mechanical action includes performing a brief tungsten CMP step on the tungsten features or scrubbing the surface using, for example, a commercial post-CMP scrubber.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: November 27, 2007
    Assignee: Sandisk 3D LLC
    Inventors: Samuel V. Dunton, Steven J. Radigan
  • Patent number: 7259097
    Abstract: A method for controlling an apparatus to perform a multi-layer chemical mechanical polishing (CMP) process with a polishing rate for a plurality of process runs. For each process run, a multilayered structure with a first thickness formed on a wafer is polished and a second thickness of the multilayered structure is predetermined to be polished away. The method comprises steps of receiving a post-CMP thickness information of the multilayered structure of a first process run, wherein for the first process run, the CMP process is performed for a first CMP process time. Then, a second CMP process time is determined according to the first CMP process time, the first thickness and the post-CMP thickness. Further, the second CMP process time is provided to the apparatus for processing a second process run posterior to the first process run.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: August 21, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Hsin Yeh, Cheng-Chuan Lee, Yi-Ching Wu, Chih-Hsiang Hsiao
  • Patent number: 7186654
    Abstract: A chemical mechanical polishing slurry contains an alumina powder including ?-alumina particles and at least one other alumina particles having a crystal structure different from that of ?-alumina, and resin particles.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: March 6, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yukiteru Matsui
  • Patent number: 7078312
    Abstract: Plasma etch processes incorporating etch chemistries which include hydrogen. In particular, high density plasma chemical vapor deposition-etch-deposition processes incorporating etch chemistries which include hydrogen that can effectively fill high aspect ratio (typically at least 3:1, for example 6:1, and up to 10:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps while reducing or eliminating chamber loading and redeposition and improving wafer-to-wafer uniformity relative to conventional deposition-etch-deposition processes which do not incorporate hydrogen in their etch chemistries.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: July 18, 2006
    Assignee: Novellus Systems, Inc.
    Inventors: Siswanto Sutanto, Wenxian Zhu, Waikit Fung, Mayasari Lim, Vishal Gauri, George D. Papasouliotis
  • Patent number: 7052969
    Abstract: A method of manufacturing a planarized semiconductor wafer in which a semiconductor wafer is provided with a chemical-mechanical polishing stop layer deposited thereon. A photoresist layer is processed and used to form a patterned chemical-mechanical polishing stop layer and shallow trenches. A shallow trench isolation material is then grown on the chemical-mechanical polishing stop layer and in the shallow trenches, and is chemical-mechanical polished to the chemical-mechanical polishing stop layer.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: May 30, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kashmir S. Sahota, Krishnashree Achuthan
  • Patent number: 7052996
    Abstract: An electropolish process may remove a conductive film from a semiconductor wafer. An electropolish apparatus having a pad over a platen may make surface-to-surface electrical contact with the conductive film of the wafer across the entire surface of the pad and the conductive film on the wafer. An electric field may be applied through openings in the pad and electrodes which receive potential by feedthroughs that extend through the platen to those electrodes. The electrodes in the feedthroughs may be electrically isolated from the pad and the platen. As a result, more uniform application of electrical potential across the surface to be polished may be achieved in some embodiments.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: May 30, 2006
    Assignee: Intel Corporation
    Inventor: Joseph M. Steigerwald
  • Patent number: 7029937
    Abstract: A depression is formed from a first surface of a semiconductor substrate. An insulating layer is provided on the bottom surface and an inner wall surface of the depression. A conductive portion is provided inside the insulating layer. A second surface of the semiconductor substrate is etched by a first etchant having characteristics such that the etching amount with respect to the semiconductor substrate is greater than the etching amount with respect to the insulating layer, and the conductive portion is caused to project while covered by the insulating layer. At least a portion of the insulating layer formed on the bottom surface of the depression is etched with a second etchant having characteristics such that at least the insulating layer is etched without forming a residue on the conductive portion, to expose the conductive portion.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: April 18, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Ikuya Miyazawa
  • Patent number: 7005383
    Abstract: Disclosed are apparatus and methods of chemical mechanical polishing a semiconductor wafer to minimize formation of scratches on a surface of a wafer. According to one example, a method of planarizing a pattern of a wafer by rotating the wafer that is fixed to a carrier head, on a polishing pad by pressing the wafer against the polishing pad and injecting slurry onto the polishing pad is disclosed. The method may include performing a first planarization process by injecting the slurry onto the polishing pad and rotating the wafer as the wafer contacts the polishing pad and performing a second planarization process during which the wafer is spaced apart from the polishing pad at a given spacing, wherein air is injected into the polishing pad to produce bubbles in the slurry on the polishing pad while the wafer is rotated.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: February 28, 2006
    Assignee: DongbuAnam Semiconductor, Inc.
    Inventor: Ji Myong Lee
  • Patent number: 7001845
    Abstract: In one aspect, the invention includes a method of treating a surface of a substrate. A mixture which comprises at least a frozen first material and liquid second material is provided on the surface and moved relative to the substrate. In another aspect, the invention encompasses a method of treating a plurality of substrates. A treating member is provided proximate a first substrate, and an initial layer of frozen material is formed over a surface of the treating member. A surface of the first substrate is treated by moving at least one of the treating member and the first substrate relative to the other of the treating member and the first substrate. After the surface of the first substrate is treated, the initial layer of frozen material is removed from over the surface of the treating member.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: February 21, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Moore, Trung Tri Doan
  • Patent number: 7003148
    Abstract: A two-dimensional image of a substrate surface targeted for polishing is periodically picked up, and the image is analyzed to obtain an entropy H1, H2 of the two-dimensional image. An end point of polishing is then determined according to the entropy H1, H2. Alternatively, other image characteristic value such as a difference statistic of the image may be employed instead of the entropy H1, H2.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: February 21, 2006
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Junichi Shiomi, Hiroki Fujimoto, Eiji Nishihara, Atsushi Imamura
  • Patent number: 6958272
    Abstract: A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: October 25, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Emmanuil H. Lingunis, Nga-Ching Alan Wong, Sameer Haddad, Mark W. Randolph, Mark T. Ramsbey, Ashot Melik-Martirosian, Edward F. Runnion, Yi He
  • Patent number: 6955971
    Abstract: A semiconductor structure and methods for fabricating are disclosed. In an implementation, a method of fabricating a semiconductor structure includes forming a first semiconductor material substrate with a first dielectric area having a first thickness and a second dielectric area having a second thickness, bonding the first substrate to a second semiconductor substrate, and thinning at least one of the first and second substrates. The invention also pertains to a semiconductor structure. The structure includes a semiconductor substrate having a surface layer of semiconductor material, a first dielectric layer of a first dielectric material buried under the surface layer, and a second dielectric layer buried under the surface layer. In an embodiment, the thickness of the first dielectric layer is different than the thickness of the second dielectric layer.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: October 18, 2005
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Bruno Ghyselen, Oliver Rayssac, Cécile Aulnette, Carlos Mazuré