Porous Semiconductor Patents (Class 438/960)
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Patent number: 6200878Abstract: An object of this invention is to provide a substrate processing method capable of satisfactorily performing in etching in the step of removing a porous silicon layer by etching.Type: GrantFiled: December 15, 1998Date of Patent: March 13, 2001Assignee: Canon Kabushiki KaishaInventors: Kenji Yamagata, Kiyofumi Sakaguchi
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Patent number: 6197654Abstract: A method of anodizing a lightly doped wafer wherein there is provided a lightly p-typed doped silicon wafer having a frontside and a backside. A p-type region is formed on the backside doped sufficiently to avoid inversion to n-type when a later applied current density of predetermined maximum value is applied to the backside. The wafer is placed in the electrolyte of a chamber having an electrolyte and having a pair of electrodes, preferably platinum, on opposite sides of the wafer and in the electrolyte. The current of predetermined value is passed between the electrodes and through the wafer, the current being sufficient to cause pores to form on the frontside of the wafer. The chamber preferably has first and second regions, one of the electrodes being disposed in one of the regions and the other electrode being disposed in the other regions with the wafer hermetically sealing the first region from the second region.Type: GrantFiled: August 21, 1998Date of Patent: March 6, 2001Assignee: Texas Instruments IncorporatedInventor: Leland S. Swanson
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Patent number: 6194239Abstract: The present invention provides new and improved methods for making crystalline semiconductor thin films which may be bonded to different kinds of substrates. The thin films may be flexible. In accordance with preferred methods, a multi-layer porous structure including two or more porous layers having different porosities is formed in a semiconductor substrate. A semiconductor thin film is grown on the porous structure. Electrodes and/or a desired support substrate may be attached to the grown film. The grown film is separated from the semiconductor substrate along a line of weakness defined in the porous structure. The separated thin film attached to the support substrate may be further processed to provide improved film products, solar panels and light emitting diode devices. These thin film semiconductors are excellent in crystallinity and may be inexpensively produced, thereby enabling production of solar cells and light emitting diodes at lower cost.Type: GrantFiled: December 7, 1999Date of Patent: February 27, 2001Assignee: Sony CorporationInventor: Hiroshi Tayanaka
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Patent number: 6177235Abstract: The present invention relates to an improved photolithography process particularly suitable for high-resolution optical lithography techniques using the g, h and i lines of the spectrum of mercury and short-wavelength UV, comprising, prior to deposition of the photosensitive resin on the layer of material to be lithographically patterned, the formation of an antireflective porous layer within the said layer to be lithographically patterned and on the surface of the latter.Type: GrantFiled: December 23, 1997Date of Patent: January 23, 2001Assignee: France TelecomInventors: Jean Marc Francou, Aomar Halimaoui, Andr{acute over (e)} Schiltz
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Patent number: 6165835Abstract: In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.Type: GrantFiled: July 20, 1999Date of Patent: December 26, 2000Assignee: Siemens AktiengesellschaftInventors: Hermann Wendt, Hans Reisinger, Andreas Spitzer, Reinhard Stengl, Ulrike Gruning, Josef Willer, Wolfgang Honlein, Volker Lehmann
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Patent number: 6163066Abstract: A porous silicon dioxide insulator having a low relative dielectric constant of about 2.0 or less is formed from a silicon carbide base layer. Initially, at least one layer of silicon carbide is deposited on a semiconductor substrate. The silicon carbide layer is then etched to form a porous silicon carbide layer, which is oxidized to produce the final porous silicon dioxide layer.Type: GrantFiled: August 24, 1998Date of Patent: December 19, 2000Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Kie Y. Ahn
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Patent number: 6156374Abstract: The invention includes a method of forming an insulating material between components of an integrated circuit. A pair of spaced electrical components are provided over a substrate. Polysilicon is chemical vapor deposited over, between, and against the pair of electrical components. Cavities are formed within the polysilicon to enhance porosity of the polysilicon. After the cavities are formed, at least some of the polysilicon is transformed into porous silicon dioxide.Type: GrantFiled: March 16, 1999Date of Patent: December 5, 2000Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Kie Y. Ahn
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Patent number: 6140209Abstract: A process for producing an SOI substrate is disclosed which is useful for saving resources and lowering production cost. Further, a process for producing a photoelectric conversion device such as a solar cell is disclosed which can successfully separate a substrate by a porous Si layer, does not require a strong adhesion between a substrate and a jig, and can save resources and lower production cost. In a substrate having a porous layer on a nonporous layer and further having on the porous layer a layer small in porosity, the nonporous layer and the layer small in porosity are separated by the porous layer to form a thin film. A metal wire is wound around a side surface of the substrate, and a current is made to flow into the metal wire to generate a heat from the metal wire and transfer the heat preferentially to the porous layer, thus conducting the separation.Type: GrantFiled: March 23, 1998Date of Patent: October 31, 2000Assignee: Canon Kabushiki KaishaInventors: Masaaki Iwane, Takao Yonehara, Kazuaki Ohmi
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Patent number: 6121112Abstract: A method for fabricating a semiconductor substrate comprises the steps of employing a diffusion method to diffuse, in a silicon substrate, an element, which is capable of controlling a conductive type, and to form a diffused region, forming a porous layer in the diffused region, forming a non-porous single crystal layer on the porous layer, bonding the non-porous single crystal layer to a base substrate, while an insulation layer is provided either on a surface to be bonded of the non-porous single crystal layer or on a surface to be bonded of the base substrate, and removing the porous layer.Type: GrantFiled: July 31, 1996Date of Patent: September 19, 2000Assignee: Canon Kabushiki KaishaInventors: Kiyofumi Sakaguchi, Takao Yonehara
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Patent number: 6107213Abstract: The present invention provides new and improved methods for making crystalline semiconductor thin films which may be bonded to different kinds of substrates. The thin films may be flexible. In accordance with preferred methods, a multi-layer porous structure including two or more porous layers having different porosities is formed in a semiconductor substrate. A semiconductor thin film is grown on the porous structure. Electrodes and/or a desired support substrate may be attached to the grown film. The grown film is separated from the semiconductor substrate along a line of weakness defined in the porous structure. The separated thin film attached to the support substrate may be further processed to provide improved film products, solar panels and light emitting diode devices. These thin film semiconductors are excellent in crystallinity and may be inexpensively produced, thereby enabling production of solar cells and light emitting diodes at lower cost.Type: GrantFiled: March 14, 1997Date of Patent: August 22, 2000Assignee: Sony CorporationInventor: Hiroshi Tayanaka
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Patent number: 6100165Abstract: A method of manufacturing a semiconductor article comprises steps of forming a diffusion region at least on the surface of one of the sides of a silicon substrate by diffusing an element capable of controlling the conduction type, forming a porous silicon layer in a region including the diffusion region, preparing a first substrate by forming a nonporous semiconductor layer on the porous silicon layer, bonding the first substrate and a second substrate together to produce a multilayer structure with the nonporous semiconductor layer located inside, splitting the multilayer structure along the porous silicon layer but not along the diffusion region and removing the porous silicon layer remaining on the split second substrate.Type: GrantFiled: November 14, 1997Date of Patent: August 8, 2000Assignee: Canon Kabushiki KaishaInventors: Kiyofumi Sakaguchi, Takao Yonehara
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Patent number: 6017773Abstract: A method of producing light-emitting porous silicon light-emitting diode including forming a porous silicon p+ layer in a p-type silicon wafer, annealing the wafer at 800-950.degree. C. in an atmosphere of inert gas and 1-25% oxygen, depositing a polycrystalline silicon film on the porous silicon layer, and n+ doping a portion of the polycrystalline silicon film.Type: GrantFiled: April 3, 1998Date of Patent: January 25, 2000Assignee: University of RochesterInventors: Philippe M. Fauchet, Leonid Tsybeskov, Karl D. Hirschmann
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Patent number: 6017811Abstract: A method for manufacturing a semiconductor structure having improved light mitting characteristics includes the step of exposing a semiconductor substrate, such as a silicon wafer, to an unbiased etching solution comprised of an acid, water, and an oxidizing agent to form a porous region having interstitial spaces in the semiconductor structure. Next, an electrically conductive contact structure is formed in the interstitial spaces and on the semiconductor structure. The large surface area at the interface junction between the electrical contact layer and the porous region is believed to enhance the intensity of light emitted by the porous region by allowing increased electrical current flow across the interface junction.Type: GrantFiled: October 6, 1997Date of Patent: January 25, 2000Assignee: The United States of America as represented by the Secretary of the NavyInventors: Michael J. Winton, Stephen D. Russell
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Patent number: 5970360Abstract: A porous silicon layer is created by using wet etching to etch a polysilicon layer. In preferred embodiment, the polysilicon layer is treated by H.sub.3 PO.sub.4 solution at 60-165.degree. C. for about 3-200 minutes. The porous silicon layer is subsequently treated by using a SC-1 solution at a temperature about 50-100.degree. C. for about 5-30 minutes to form a roughened polysilicon layer. The SC-1 solution is composed of NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O. The volume ratio for the three compounds of said SC-1 is NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O=0.1-5:0.1-5:1-20. The next step of the formation is the deposition of a dielectric film along the roughened surface of the micro-islands polysilicon layers. A conductive layer is deposited over the dielectric film. Next, photolithgraphy and etching process are used to etch the conductive layer, the dielectric film and the micro-islands polysilicon layer into a portion of the layer.Type: GrantFiled: December 3, 1996Date of Patent: October 19, 1999Assignee: Mosel Vitelic Inc.Inventors: Huang-Chung Cheng, Han-Wen Liu, Stewart Huang, Roger Yen
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Patent number: 5970361Abstract: Disclosed are a semiconductor device having a porous member as an active region, the porous member comprising a plurality of porous regions having different structures or compositions; and a process for producing a semiconductor device, comprising a step of modifying partially a non-porous substrate, and a subsequent step of making the substrate porous.Type: GrantFiled: April 28, 1997Date of Patent: October 19, 1999Assignee: Canon Kabushiki KaishaInventors: Hideya Kumomi, Takao Yonehara, Nobuhiko Sato
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Patent number: 5950094Abstract: The present invention provides a method of fabricating fully dielectric isolated silicon (FDIS) by anodizing a buried doped silicon layer through trenches formed between active areas to form a porous silicon layer; oxidizing the porous silicon layer through the trenches to form a buried oxide layer; and by depositing a dielectric in the trenches. The process begins by forming a buried doped layer in a silicon substrate defining a silicon top layer over the conductive buried doped layer. The silicon top layer and the buried doped layer are patterned to form trenches that extend into but not through the buried doped layer. The trenches define isolated silicon regions. The buried doped layer is anodized to form a porous silicon layer. The porous silicon layer is converted into a buried oxide layer by oxidation. The oxidation step also forms a liner oxide layer on the tops and sidewalls of the isolated silicon regions.Type: GrantFiled: February 18, 1999Date of Patent: September 7, 1999Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chi Lin, Hui-ju Yu, Yen-Ming Chen, Hui-Hua Chang
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Patent number: 5930626Abstract: The method of fabricating a capacitor of a memory cell is disclosed including the steps of forming a transistor on a semiconductor substrate; sequentially forming an etch stop layer, an insulating layer and a first conductive layer on the semiconductor substrate and the transistor; converting a portion of the first conductive layer into a first porous layer through anodization; patterning a predetermined portion of the first porous layer to form a storage node contact; forming a second conductive layer on the semiconductor substrate and the first porous layer; converting a portion of the second conductive layer into a second porous layer through anodization; patterning a portion of the second porous layer and forming a storage node electrode pattern through an etching process; forming a dielectric layer on an overall surface of the storage node electrode pattern; and forming a third conductive layer on an overall surface of the dielectric layer.Type: GrantFiled: November 1, 1996Date of Patent: July 27, 1999Assignee: LG Semicon Co., Ltd.Inventor: Ki-Yeol Park
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Patent number: 5914183Abstract: Porous semiconductor material in the form of at least partly crystalline silicon is produced with a porosity in excess of 90% determined gravimetrically, and voids, crazing and peeling are substantially not observable by scanning electron microscopy at a magnification of 7,000. The porous silicon is dried by supercritical drying. The silicon material has good luminescence properties together with good morphology and crystallinity.Type: GrantFiled: June 5, 1996Date of Patent: June 22, 1999Assignee: The Secretary of State for Defence in Her Brittanic Majesty's Government of the United Kingdom of Great Britain and Northern IrelandInventor: Leigh Trevor Canham
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Patent number: 5915165Abstract: The present invention relates to a vertical cavity surface emitting laser with an accurately defined and controlled aperture which directs the current path within the laser. Specifically, the oxide regions surrounding the aperture are formed by a pre-oxidation layer disordering process which controls the regions within which oxidation can occur. The present invention allows for the manufacture of highly compact lasers with reproducible optical and electrical characteristics.Type: GrantFiled: December 15, 1997Date of Patent: June 22, 1999Assignee: Xerox CorporationInventors: Decai Sun, Philip D. Floyd
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Patent number: 5907767Abstract: Disclosed is a backside-illuminated charge-coupled device imager, which has: a silicon substrate which includes a light-receiving region which is formed on the frontside of the silicon substrate and includes charge-coupled devices which are arranged one-dimensionally or two-dimensionally and has a thickness equal to or less than a pixel pitch, wherein light is supplied from the backside of the silicon substrate; wherein the light-receiving region of the silicon substrate is provided with a silicon layer with a thickness equal to or less than the pixel pitch and a silicon dioxide (SiO.sub.2) layer thicker than the silicon layer.Type: GrantFiled: June 11, 1997Date of Patent: May 25, 1999Assignee: NEC CorporationInventor: Shigeru Tohyama
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Patent number: 5863826Abstract: A method for forming field isolation regions in multilayer semiconductor devices comprises the steps of masking active regions of the substrate, forming porous silicon in the exposed field isolation regions, removing the mask and oxidizing the substrate. A light ion impurity implant is used to create pores in the substrate. Substrate oxidation proceeds by rapid thermal annealing because the increased surface area of the pores and the high reactivity of unsaturated bonds on these surfaces provides for enhanced oxidation.Type: GrantFiled: August 2, 1996Date of Patent: January 26, 1999Assignee: Micron Technology, Inc.Inventors: Zhiqiang Jeff Wu, Li Li
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Patent number: 5856229Abstract: A process for producing a semiconductor substrate is provided which comprises steps of forming a porous layer on a first substrate, forming a nonporous monocrystalline semiconductor layer on the porous layer of the first substrate, bonding the nonporous monocrystalline layer onto a second substrate, separating the bonded substrates at the porous layer, removing the porous layer on the second substrate, and removing the porous layer constituting the first substrate.Type: GrantFiled: May 27, 1997Date of Patent: January 5, 1999Assignee: Canon Kabushiki KaishaInventors: Kiyofumi Sakaguchi, Takao Yonehara
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Patent number: 5840616Abstract: A method for preparing a semiconductor member comprises process of making a porous Si substrate and then forming a non-porous Si monocrystalline layer on the porous Si substrate; primary bonding process of bonding the porous Si substrate and an insulating substrate via the non-porous Si monocrystalline layer; etching process of etching the porous Si to remove the porous Si by chemical etching after the primary bonding process; and secondary bonding process of strengthening the primary bonding after the etching process.Type: GrantFiled: September 8, 1995Date of Patent: November 24, 1998Assignee: Canon Kabushiki KaishaInventors: Kiyofumi Sakaguchi, Takao Yonehara
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Patent number: 5830777Abstract: A compact capacitance type acceleration sensor in which a mass portion having a plurality of movable electrodes are arranged in a recess portion formed on the surface of a p-type single crystal silicon base plate under the condition that the mass portion can be displaced. A plurality of stationary electrodes are arranged at a position opposed to the movable electrodes being separate from the movable electrodes. The mass portion is elastically supported by a support from the lower side and also elastically supported by four beams from the lateral side. Due to the above structure, the damping characteristic of the mass portion can be improved.Type: GrantFiled: June 27, 1996Date of Patent: November 3, 1998Assignee: Kabushiki Kaisha Tokai Rika Denki SeisakushoInventors: Tatsuya Ishida, Yasuo Imaeda
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Patent number: 5827755Abstract: A liquid crystal image display unit created on a substrate non-transparent to the light in the visible radiation area, characterized in that a portion beneath a liquid crystal pixel part on said substrate is removed, so that the light is made transmissive through said liquid crystal pixel part.Type: GrantFiled: August 22, 1995Date of Patent: October 27, 1998Assignee: Canon Kabushiki KaishaInventors: Takao Yonehara, Mamoru Miyawaki, Akira Ishizaki, Junichi Hoshi, Masaru Sakamoto, Shigetoshi Sugawa, Shunsuke Inoue, Toru Koizumi, Tetsunobu Kohchi, Kiyofumi Sakaguchi, Takanori Watanabe
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Patent number: 5773353Abstract: A semiconductor substrate and a method of fabricating the same, and provides which the active area to be formed the active element is defined by the trench filled with any conductive polycrystal silicon in which any portion of a large number of the epitaxial layer is crystally grown on any conductive silicon substrate, and the multi-aperture silicon oxide layer is formed from the metal line to be used to the passive element or the transmitting line outside the trench, so that the interference between the passive element and the semiconductor substrate is prevented, and to attenuate the transmitting signal prevents to be attenuated in the high frequency band operation. Therefore, the semiconductor substrate for a unit active element and the MMIC to be able to operate the high frequency band is manufactured into the silicon, and thus it is advantageous to reduce the cost and enhance the yield.Type: GrantFiled: November 29, 1995Date of Patent: June 30, 1998Assignee: Electronics and Telecommunications Research InstituteInventors: Oh-Joon Kwon, Jung-Hee Lee, Yong-Hyun Lee
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Patent number: 5736446Abstract: A method of fabricating a MOS device having a gate-side air-gap structure is provided. A nitride spacer for reserving space of the air gap is formed on the substrate adjacent to the gate structure. An amorphous silicon spacer for forming the sidewall spacer and sealing the air gap is formed adjacent to the nitride spacer. The upper portion of the amorphous silicon spacer is heavily doped during the source/drain implantation. After removing the nitride spacer the doped amorphous silicon spacer is oxidized by a wet oxidation process to form a doped oxide spacer. The growing doped oxide spacer will seal the hole for the nitride spacer resulting from the heavily doped upper portion having a higher oxidation rate than that of other portions. Dopants implanted in the amorphous silicon spacer migrate into the substrate and extended ultra-shallow doped regions are formed that reduce the series resistance of the LDD structure.Type: GrantFiled: May 21, 1997Date of Patent: April 7, 1998Assignee: Powerchip Semiconductor Corp.Inventor: Shye-Lin Wu
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Patent number: 5736430Abstract: A method of forming apparatus including a force transducer on a silicon substrate having an upper surface, the silicon substrate including a dopant of one of the n-type or the p-type, the force transducer including a cavity having spaced side walls and a diaphragm supported in the cavity, the diaphragm extending between the side walls of the cavity, comprising the steps of: a. implant in the substrate a layer of a dopant of the one of the n-type or the p-type; b. deposit an epitaxial layer on the upper surface of the substrate, the epitaxial layer including a dopant of the other of the n-type or the p-type; c. implant spaced sinkers through the epitaxial layer and into electrical connection with the layer of a dopant of the one of the n-type or the p-type, each of the sinkers including a dopant of the one of the n-type or the p-type; d. anodize the substrate to form porous silicon of the sinkers and the layer; e. oxidize the porous silicon to form silicon dioxide; and f.Type: GrantFiled: June 7, 1995Date of Patent: April 7, 1998Assignee: SSI Technologies, Inc.Inventors: James D. Seefeldt, Michael F. Mattes
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Patent number: 5665423Abstract: The present invention is related to a method for manufacturing a photodetector which comprises the steps of: (a) preparing a substrate having a back surface; (b) applying a first conducting layer on the back surface; (c) annealing the substrate coated with the first conducting layer in an inert gas atmosphere; (d) applying a anti-corrosion layer on the first conducting layer; (e) immersing the anti-corrosion layer-applied substrate in a hydrofluoric acid aqueous solution with a concentration of 5%.about.10%; (f) eroding the anti-corrosion layer-applied substrate under a current density of about 12.5.about.25 mA/cm.sup.2 for about 5.about.40 minutes to obtain a porous layer therereon; and (g) applying a thin film layer of a second conducting layer to an upper surface of the porous layer to obtain the photodetector. The present photodetector has a wider frequency band and a higher sensitivity than conventional ones and the present manufacturing method is simple and economical.Type: GrantFiled: February 10, 1995Date of Patent: September 9, 1997Assignee: National Science CouncilInventor: Ming-Kwei Lee
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Patent number: 5665250Abstract: A surface type acceleration sensor includes a p-type single crystal silicon base plate, a cantilever functioning as a cantilever structure portion, and a plurality of strain gauges. The cantilever is disposed in a recess portion formed on the front face of the p-type single crystal silicon base plate so that the cantilever can be displaced in the upward and downward direction. The cantilever includes an epitaxial growth layer principally made of n-type single crystal silicon. The strain gauge is made of p-type silicon and formed on an upper face of the base end portion of the cantilever.Type: GrantFiled: March 29, 1996Date of Patent: September 9, 1997Assignee: Kabushiki Kaisha Tokai Rika Denki SeisakushoInventors: Hitoshi Iwata, Makoto Murate
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Patent number: 5635419Abstract: The invention provides a capacitor structure utilizing porous silicon as a first plate of the capacitor structure, thereby greatly increasing the surface area available for the capacitor and thereby the capacitance attainable. The invention also provides a trench structure having a porous silicon region surrounding the sidewalls thereof. Such a trench can then be utilized to form a capacitor according to the subject invention. Methods of producing the capacitor and trench structures according to the subject invention are also provided. Porous silicon is produced utilizing electrolytic anodic etching.Type: GrantFiled: May 4, 1995Date of Patent: June 3, 1997Assignee: International Business Machines CorporationInventors: Peter J. Geiss, Donald M. Kenney
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Patent number: 5633182Abstract: Variations in the individual liquid crystal cells and cross-talk between adjacent pixels are reduced, stable operation is maintained and the aperture and the S/N ratio are increased by providing a transistor and an interconnection layer therefor on one surface of an insulating layer while providing an electrode for applying a voltage to a liquid crystal on the other surface thereof. One major electrode portion of the transistor and the liquid crystal voltage applying electrode are connected to each other using an electrode via an opening. Also, the electrode for connecting the major electrode portion 3 to the liquid crystal voltage applying electrode is provided on the other surface of the insulating layer such that it shield the transistor from light.Type: GrantFiled: December 12, 1995Date of Patent: May 27, 1997Assignee: Canon Kabushiki KaishaInventors: Mamoru Miyawaki, Shigeki Kondo, Yoshio Nakamura, Tetsunobu Kouchi
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Patent number: 5627081Abstract: The instant invention teaches a novel method for fabricating silicon solar cells utilizing concentrated solar radiation. The solar radiation is concentrated by use of a solar furnace which is used to form a front surface junction and back-surface field in one processing step. The present invention also provides a method of making multicrystallline silicon from amorphous silicon. The invention also teaches a method of texturing the surface of a wafer by forming a porous silicon layer on the surface of a silicon substrate and a method of gettering impurities. Also contemplated by the invention are methods of surface passivation, forming novel solar cell structures, and hydrogen passivation.Type: GrantFiled: November 29, 1994Date of Patent: May 6, 1997Assignee: Midwest Research InstituteInventors: Y. Simon Tsuo, Marc D. Landry, John R. Pitts