Abstract: The invention provides a suitable method and an appropriate, PV film structure. This aim is achieved by a room temperature method in which aqueous dispersions are printed onto a substrate and cured by an accompanying reaction. The accompanying reaction forms gradients and also nanoscale structures at the film boundaries, which produce a PV active film having standard performance and a higher stability. At around 10% efficiency, stability and no initial loss in performance in the climatic chamber test can be obtained and over a 20 year test period, consistently less fluctuation can be achieved. The method is free from tempering or sintering steps, enables the use of technically pure, advantageous starting materials and makes the PV film structure available as a finished, highly flexible cell for a fraction of the typical investment in production or distribution.

Abstract: The present disclosure relates to methods of fabricating a porous structure, such as a porous silicon carbide structure. The methods can include a step of providing a structure to be rendered porous, and a step of providing an etching solution. The methods can also include a step of electrochemically etching the structure to produce pores through at least a region of the structure, resulting in the formation of a porous structure. The morphology of the porous structure can be controlled by one or more parameters of the electrochemical etching process, such as the strength of the etching solution and/or the applied voltage.

Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate that extends from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; forming a mask layer over the substrate that exposes a portion of the ILD layer and a portion of the outer gate spacer; selectively etching the exposed portion of the outer gate spacer, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process on the exposed portion of the ILD layer to seal the air gap.

Abstract: Forming a porous multilayer material includes forming a multilayer material on a substrate. Forming the multilayer material includes alternately forming a sacrificial layer and a semi-sacrificial layer, where the sacrificial layer includes a first metal and the semi-sacrificial layer includes the first metal and a second metal or metallic alloy. Forming the porous multilayer material further includes removing at least a portion of the first metal from each of the sacrificial and semi-sacrificial layers to yield the porous multilayer material. The porous multilayer material includes a multiplicity of metal-containing layers, each layer having a thickness in a range between about 5 nm and about 100 nm and bonded to an adjacent layer. Each layer includes chromium, niobium, tantalum, vanadium, molybdenum, tungsten, or a combination thereof. A void is defined between each pair of layers, and a density of porous the multilayer material is <1% bulk density.

Abstract: A resistive memory device includes a first metallic layer comprising a source of positive metallic ions, a switching media having an upper surface and a lower surface, wherein the upper surface is adjacent to the first metallic layer, wherein the switching media comprises conductive filaments comprising positive metallic ions from the source of positive metallic ions formed from the upper surface towards the lower surface, a semiconductor substrate, a second metallic layer disposed above the semiconductor substrate, a non-metallic conductive layer disposed above the second metallic layer, and an interface region between the non-metallic conductive layer and the switching media having a negative ionic charge.

Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.

Abstract: (a) Forming on a growth substrate a void-containing layer that is made of a group III nitride compound semiconductor and contains voids. (b) Forming on the void-containing layer an n-type layer that is made of an n-type group III nitride compound semiconductor and serves to close the voids. (c) Forming on the n-type layer an active layer made of a group III nitride compound semiconductor. (d) Forming on the active layer a p-type layer made of a p-type group III nitride compound semiconductor. (e) Bonding a support substrate above the p-type layer. (f) Peeling off the growth substrate at the boundary where the void are produced. (g) Planarizing the n-type layer. Step (b) comprises (b1) forming part of the n-type layer under conditions where horizontal growth is relatively weak and (b2) forming the remaining part of the n-type layer under conditions where horizontal growth is relatively strong.

Abstract: Defects in a semiconductor substrate are reduced. A semiconductor substrate with fewer defects is manufactured with high yield. Further, a semiconductor device is manufactured with high yield. A semiconductor layer is formed over a supporting substrate with an oxide insulating layer interposed therebetween, adhesiveness between the supporting substrate and the oxide insulating layer in an edge portion of the semiconductor layer is increased, an insulating layer over a surface of the semiconductor layer is removed, and the semiconductor layer is irradiated with laser light, so that a planarized semiconductor layer is obtained. For increasing the adhesiveness between the supporting substrate and the oxide insulating layer in the edge portion of the semiconductor layer, laser light irradiation is performed from the surface of the semiconductor layer.

Abstract: Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate.

Abstract: A transmission electron microscope (TEM) micro-grid includes a grid and a heater including at least one carbon nanotube film structure located on the grid. The micro-grid with the at least one carbon nanotube film structure prevents a floating of the sample located on the micro-grid to increase the quality of TEM images.

Abstract: A transmission electron microscope (TEM) micro-grid includes a grid, a carbon nanotube film structure and two electrodes electrically connected to the carbon nanotube film structure.

Abstract: A transmission electron microscope (TEM) micro-grid includes a metallic grid and a carbon nanotube film structure covered thereon. A method for making a TEM micro-grid includes the steps of: (a) providing an array of carbon nanotubes, quite suitably, providing a super-aligned array of carbon nanotubes; (b) drawing a carbon nanotube film from the array of carbon nanotubes; (c) covering the carbon nanotube film on a metallic grid, and treating the carbon nanotube film and the metallic grid with an organic solvent.

Abstract: A method for forming an interconnect structure with airgaps, includes: providing a structure having a trench formed on a substrate; depositing a spacer oxide layer on sidewalls of the trench as sidewall spacers by plasma enhanced atomic layer deposition; filling the trench having the sidewall spacers with copper; removing the sidewall spacers to form an airgap structure; and encapsulating the airgap structure, wherein airgaps are formed between the filled copper and the sidewalls of the trench.

Abstract: A transmission electron microscope (TEM) micro-grid includes a pure carbon grid having a plurality of holes defined therein and at least one carbon nanotube film covering the holes. A method for manufacturing a TEM micro-grid includes following steps. A pure carbon grid precursor and at least one carbon nanotube film are first provided. The at least one carbon nanotube film is disposed on a surface of the pure carbon grid precursor. The pure carbon grid precursor and the at least one carbon nanotube film are then cut to form the TEM micro-grid in desired shape.

Abstract: A method for manufacturing an active layer of a solar cell is disclosed, the active layer manufactured including multiple micro cavities in sub-micrometer scale, which can increase the photoelectric conversion rate of a solar cell. The method comprises following steps: providing a substrate having multiple layers of nanospheres which are formed by the aggregated nanospheres; forming at least one silicon active layer to fill the inter-gap between the nanospheres and part of the surface of the substrate; and removing the nanospheres to form an active layer having plural micro cavities on the surface of the substrate. The present invention also provides a solar cell comprising: a substrate, an active layer, a transparent top-passivation, at least one front contact pad, and at least one back contact pad. The active layer locates on a surface of the substrate and has plural micro cavities whose diameter is less than one micrometer.

Abstract: In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the properties of the cap film. Of particular concern is the change in the stress state of the cap from compressive to tensile stress. This leads to a weaker dielectric-cap interface and mechanical failure of the ULK film. A layer of nanoparticles is inserted between the cap and the ULK film. The nanoparticles absorb the UV light before it can damage the cap film, thus maintaining the mechanical integrity of the ULK dielectric.

Abstract: A method of manufacturing a solar cell having a texture on a surface of a silicon substrate includes first forming a porous layer on the surface of the silicon substrate by dipping the silicon substrate into a mixed aqueous solution of oxidizing reagent containing metal ions and hydrofluoric acid. Second, a texture is formed by etching the surface of the silicon substrate after the porous layer is formed, by dipping the silicon substrate into a mixed acid mainly containing hydrofluoric acid and nitric acid.

Abstract: The present invention provides a porous semiconductive structure, characterized in that the structure has an electrical conductivity of 5·10?8 S·cm?1 to 10 S·cm?1, and an activation energy of the electrical conductivity of 0.1 to 700 meV, and a solid fraction of 30 to 60% by volume, and a pore size of 1 nm to 500 nm, the solid fraction having at least partly crystalline doped constituents which are bonded to one another via sinter necks and have sizes of 5 nm to 500 nm and a spherical and/or ellipsoidal shape, which comprise the elements silicon, germanium or an alloy of these elements, and also a process for producing a porous semiconductive structure, characterized in that A. doped semimetal particles are obtained, and then B. a dispersion is obtained from the semimetal particles obtained after step A, and then C. a substrate is coated with the dispersion obtained after step B, and then D. the layer obtained after step C is treated by means of a solution of hydrogen fluoride in water, and then E.

Abstract: The present invention provides means and methods for producing surface-activated semiconductor nanoparticles suitable for in vitro and in vivo applications that can fluoresce in response to light excitation. Semiconductor nanostructures can be produced by generating a porous layer in semiconductor substrate comprising a network of nanostructures. Prior or subsequent to cleavage from the substrate, the nanostructures can be activated by an activation means such as exposing their surfaces to a plasma, oxidation or ion implantation. In some embodiments, the surface activation renders the nanostructures more hydrophilic, thereby facilitating functionalization of the nanoparticles for either in vitro or in vivo use.

Abstract: The present invention relates to alternative methods for the production of crystalline silicon compounds and/or alloys such as silicon carbide layers and substrates. In one embodiment, a method of the present invention comprises heating a porous silicon deposition surface of a porous silicon substrate to a temperature operable for epitaxial deposition of at least one atom or molecule, contacting the porous silicon deposition surface with a reactive gas mixture comprising at least one chemical species comprising a group IV element and at least one silicon chemical species, and depositing a silicon-group IV element layer on the porous silicon deposition surface. In another embodiment, the chemical species comprising a group IV element can be replaced with a transition metal species to form a silicon silicide layer.

Abstract: A sensor which has high measuring sensitivity and is excellent in response is provided by forming a porous film in a sensitive section of a field-effect transistor. It comprises a porous body, which is formed on a sensitive section (here, a gate insulating film) of the field-effect transistor and has cylindrical pores which are formed almost perpendicularly to a substrate, and the field-effect transistor. It uses as a porous film a porous film which is made of a semiconductor material whose main component (except oxygen) is silicon, germanium, or a composite of silicon and germanium, or a porous film made of an insulation material whose main component is silicon oxide, which has pores perpendicular to the substrate.

Abstract: Single-walled carbon nanotube transistor devices, and associated methods of making such devices include a porous structure for the single-walled carbon nanotubes. The porous structure may be anodized aluminum oxide or another material. Electrodes for source and drain of a transistor are provided at opposite ends of the single-walled carbon nanotube devices. A concentric gate surrounds at least a portion of a nanotube in a pore. A transistor of the invention may be especially suited for power transistor or power amplifier applications.

Abstract: A method for making transmission electron microscope gird is provided. An array of carbon nanotubes is provided and drawing a carbon nanotube film from the array of carbon nanotubes. A substrate has a plurality of spaced metal girds attached on the substrate. The metal girds are covered with the carbon nanotube film and treating the carbon nanotube film and the metal girds with organic solvent. A transmission electron microscope (TEM) grid is obtained by removing remaining CNT film.

Abstract: The present invention relates to alternative methods for the production of crystalline silicon compounds and/or alloys such as silicon carbide layers and substrates.

Abstract: A method of forming a nanostructure having the form of a tree, comprises a first stage and a second stage. The first stage includes providing one or more catalytic particles on a substrate surface, and growing a first nanowhisker via each catalytic particle. The second stage includes providing, on the periphery of each first nanowhisker, one or more second catalytic particles, and growing, from each second catalytic particle, a second nanowhisker extending transversely from the periphery of the respective first nanowhisker. Further stages may be included to grow one or more further nanowhiskers extending from the nanowhisker(s) of the preceding stage. Heterostructures may be created within the nanowhiskers. Such nanostructures may form the components of a solar cell array or a light emitting flat panel, where the nanowhiskers are formed of a photosensitive material.

Abstract: In a manufacturing process of electronic components which include conductive patterns laminated with insulating layers provided therebetween, conductive pattern layers having conductive patterns formed at intervals therebetween along layer surfaces and insulating layers are alternately laminated to each other. The laminate is pressed by applying a force thereto in the lamination direction, followed by cutting of the laminate along cutting lines provided along boundaries between the electronic components, so that the electronic components are separated from each other. In a cutting-removal region of a mother substrate from which the electronic components are separated from each other by cutting, removal dummy patterns having a size allowing it to be disposed within the above region are formed. In the electronic component, floating dummy patterns which are not electrically connected to the conductive patterns are formed at intervals from the cutting-removal region.

Abstract: Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering, methods for fabricating such device structures, and methods for forming a semiconductor-on-insulator substrate. The semiconductor structure comprises a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant. In one embodiment, the dielectric constant of the first dielectric region may be less than about 3.9 and the dielectric constant of the second dielectric region may be greater than about ten (10). The semiconductor-on-insulator substrate comprises a semiconductor layer separated from a bulk layer by an insulator layer of a high-dielectric constant material.

Abstract: Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.

Abstract: A method of making a device for measuring deformation includes a step of depositing a silicon adhesion underlayer on a silicon carbide surface by chemical vapor spraying, and a step of depositing a coating on the silicon adhesion underlayer by atmospheric thermal spraying.

Abstract: Low dielectric constant dielectric films having a high degree of porosity suffer from poor mechanical strength and can be damaged during processing steps. Damage can be substantially eliminated or minimized by stuffing the pores of the dielectric film with a material that substantially fills the pores. The stuffing material should have low surface tension and viscosity to provide good wetting. Alternatively, the stuffing material can be dissolved in a wetting carrier fluid, such as supercritical carbon dioxide and the like.

Abstract: Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon layer. The porous silicon layer and temporary support are then removed and packaging is completed. Embodiments of the invention provide reliable, low cost methods and apparatuses for producing reduced-thickness IC device wafers to substantially increase thermal conductivity between the device layer of an IC device and a heat sink. In alternative embodiments, the layered silicon substrate includes an insulator layer on a layer of porous silicon and a silicon layer on the insulator layer.

Abstract: In a first aspect, a first method of manufacturing a finFET is provided. The first method includes the steps of (1) providing a substrate; and (2) forming at least one source/drain diffusion region of the finFET on the substrate. Each source/drain diffusion region includes (a) an interior region of unsilicided silicon; and (b) silicide formed on a top surface and sidewalls of the region of unsilicided silicon. Numerous other aspects are provided.

Abstract: A process of a porous body comprises the steps of disposing a first material in which pores are formed by anodization on a substrate to form a first layer, disposing on the first layer a second material which has a hardness lower than that of the first material and an oxide of which is dissolved by an anodization step to form a second layer, forming a concave structure on a surface of the second layer, oxidizing the second layer, and subjecting the first layer to anodization to dissolve the second layer. A magnetic recording medium or a light-emitting element comprises a first layer which is comprised of an oxide of aluminum and comprises a porous portion on a substrate, and a second layer on the first layer which has a hardness lower than that of the first layer and is comprised of a metal element, wherein the pores are packed with a magnetic substance or a light-emitting material.

Abstract: A method of fabricating a semiconductor device includes etching a substrate to form a recess, the substrate being formed on a backside of a semiconductor wafer, forming pores in the substrate in an area of the recess, and forming in the recess a material having a thermal conductivity which is greater than a thermal conductivity of the substrate. In another aspect, a method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.

Abstract: The invention relates to methods for preparing a removable system on a mother substrate. The method deposits a high surface to volume sacrificial layer on a mother substrate and stabilizes the sacrificial layer by a) removing volatile chemical species in and on the sacrificial layer and/or b) modifying the surface of the layer. The method coats over the sacrificial layer with a capping medium. A system is the fabricated on the capping medium. The method provides through holes to access the sacrificial layer. The method may also apply a top layer onto the system to form a covered system. The invention also includes the step of removing the sacrificial layer to release the system from the mother substrate. Methods of the invention also include selectively removing a portion of the system and capping layers to form void regions defining an array of islands composed of device, structure, or system and capping layer regions, and optionally filling the island-defining void region with a sacrificial material.

Abstract: A method of producing a semiconductor component, e.g., a multilayer semiconductor component, and a semiconductor component produced by this method, where the semiconductor component has, e.g., a mobile mass, i.e., an oscillator structure. A method easily and inexpensively produce a micromechanical component having monocrystalline oscillator structures, such as an acceleration sensor or a rotational rate sensor for example, by surface micromechanics, a first porous layer is formed in the semiconductor component in a first step and a cavity, i.e., a cavern, is formed beneath or out of the first porous layer in the semiconductor component in a second step.

Abstract: A process for fabricating a strained layer of silicon or of a silicon/germanium alloy, includes: a) the formation of a layer (2) of silicon or of a silicon/germanium alloy on a layer (1) of a material having a modifiable lattice parameter; and b) the modification of the lattice parameter.

Abstract: In a method of manufacturing a semiconductor device, semiconductor circuit elements or wiring patterns are formed on a semiconductor substrate then, a porous semiconductor oxide film is formed as an interlayer insulating film on the semiconductor substrate including the semiconductor circuit elements or wiring patterns by oxidizing semiconductor substance in a mixture gas containing an oxygen gas in a chamber.

Abstract: Methods and systems are disclosed for fabricating ultra-low dielectric constant porous materials. In one aspect of the invention, a method for making porous low-k films is disclosed. The method uses polymer based porogens as sacrificial templates around which a chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) deposited matrix is formed. Upon pyrolysis, the porogens decompose resulting in a porous ultra-low dielectric material. This method can be used, for example, to produce porous organosilicate glass (OSG) materials, ultra-low dielectric nanoporous materials, porous ceramics, porous scaffolds, and/or porous metals. Various uses and embodiments of the methods and systems of this invention are disclosed.

Abstract: Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon layer. The porous silicon layer and temporary support are then removed and packaging is completed. Embodiments of the invention provide reliable, low cost methods and apparatuses for producing reduced-thickness IC device wafers to substantially increase thermal conductivity between the device layer of an IC device and a heat sink. In alternative embodiments, the layered silicon substrate includes an insulator layer on a layer of porous silicon and a silicon layer on the insulator layer.

Abstract: A method for forming macropores in a substrate is disclosed. On a substrate a pattern of submicron features is formed. This pattern is covered with a layer, which is preferably selectively removable with respect to the substrate and the submicron features. This cover layer is removed until the submicron features are exposed. The submicron features are then etched selectively to the cover layer, thereby creating a pattern of submicron openings in this cover layer. The patterned cover layer is used as a hardmask to etch macropores in the substrate.

Abstract: A method and system for cutting a wafer comprising a conductive substrate attached to an array of integrated devices includes placing the wafer on a stage such as a movable X-Y stage including a vacuum chuck having a porous mounting surface, and securing the wafer during and after cutting by vacuum pressure through the pores. The wafer is cut by directing UV pulses of laser energy at the conductive substrate using a solid-state laser. An adhesive membrane can be attached to the separated die to remove them from the mounting surface, or the die can otherwise be removed after cutting from the wafer.

Abstract: A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top semiconductor layer. Then, an etch stop layer is formed upon the wafer that carries the device structure, and a window is formed in the etch stop layer. Further, a dielectric layer is formed upon the etch stop layer that has the window. Then, a first contact hole through the dielectric layer and the window down to the backside semiconductor substrate is simultaneously etched with at least one second contact hole through the dielectric layer down to the device structure. The wafer may be a silicon-on-insulator (SOI) wafer, and the etch stop layer and the dielectric layer may be formed by depositing silicon oxynitride and tetraethyl orthosilicate (TEOS), respectively. The device structure may be a CMOS transistor structure.

Abstract: The present invention provides a method that can prevent an anti-diffusion film from being formed defectively on a porous dielectric film due to pores in method for forming metal wires in a semiconductor device in which the porous dielectric film is used as an insulating film between metal wires.

Abstract: A material layer containing impurities that react with water molecules is formed on a substrate. The material layer is then heated under a pressure exceeding one atmosphere and in the presence of water vapor to generate pores in the material layer. The material layer may form the interlayer insulating layer of a semiconductor device.

Abstract: The invention relates to a method for producing a thin layer (8) containing at least one component (6, 6A, 6B) comprising:—a preparation step, wherein an added layer (2, 3, 4) is created on a support (1), at least one part (2) of said layer being adapted for local embrittling and said substrate and the part which can be embrittled being made from different materials and/or having different microstructures; an embrittlement step, wherein a fragile underlayer (5) is produced in the part which can be embrittled; a work step, wherein at least one component (6, 6A, 6B) is created on said added layer; and a separation step, wherein a dissociation is induced in the part which can be embrittled, along said fragile underlayer, in order to produce a thin layer (8) comprising a part of said added layer and said component.

Abstract: A high emission electron emitter and a method of fabricating a high emission electron emitter are disclosed. A high emission electron emitter includes an electron injection layer, an active layer of high porosity porous silicon material in contact with the electron injection layer, a contact layer of low porosity porous silicon material in contact with the active layer and including an interface surface with a heavily doped region, and an optional top electrode in contact with the contact layer. The contact layer reduces contact resistance between the active layer and the top electrode and the heavily doped region reduces resistivity of the contact layer thereby increasing electron emission efficiency and stable electron emission from the top electrode. The electron injection layer is made from an electrically conductive material such as n+ semiconductor, n+ single crystal silicon, a metal, a silicide, or a nitride.

Abstract: A process for depositing porous silicon oxide-based films using a sol-gel approach utilizing a precursor solution formulation which includes a purified nonionic surfactant and an additive among other components, where the additive is either an ionic additive or an amine additive which forms an ionic ammonium type salt in the acidic precursor solution. Using this precursor solution formulation enables formation of a film having a dielectric constant less than 2.5, appropriate mechanical properties, and minimal levels of alkali metal impurities. In one embodiment, this is achieved by purifying the surfactant and adding ionic or amine additives such as tetraalkylammonium salts and amines to the stock precursor solution.

Abstract: A method for treating a film of material, which can be defined on a substrate, e.g., silicon. The method includes providing a substrate comprising a cleaved surface, which had a porous silicon layer thereon. The substrate may have a distribution of hydrogen bearing particles defined from the cleaved surface to a region underlying said cleaved surface. The method also includes increasing a temperature of the cleaved surface to greater than about 1,000 Degrees Celsius while maintaining the cleaved surface in a etchant bearing environment to reduce a surface roughness value by about fifty percent and greater. Preferably, the value can be reduced by about eighty or ninety percent and greater, depending upon the embodiment.

Abstract: In the preferred embodiment of this invention a method is described to convert patterned SOI regions into patterned SGOI (silicon-germanium on oxide) by the SiGe/SOI thermal mixing process to further enhance performance of the logic circuit in an embedded DRAM. The SGOI region acts as a template for subsequent Si growth such that the Si is strained, and electron and holes in the Si have higher mobility.