Polycrystalline Semiconductor Patents (Class 438/97)
  • Patent number: 10720327
    Abstract: This disclosure provides a method and a device for manufacturing a semiconductor substrate. The method for manufacturing a semiconductor substrate comprises the following steps: heating a semiconductor material to a molten state to obtain a molten semiconductor material; thermally spraying the molten semiconductor material onto a baseplate by using a thermal spraying gun, then cooling to solidify the molten semiconductor material on the baseplate to obtain the semiconductor substrate. The disclosed method offers, when manufacturing the semiconductor substrate, high material utilization, low manufacturing cost, and the ability to manufacture larger semiconductor substrate, with controllable thickness and high purity, providing broad application prospects.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: July 21, 2020
    Assignee: HONG WU YES ENGINEERING TECHNOGOLOGY RESEARCH INSTITUTE CO., LTD.
    Inventor: Guangwu Li
  • Patent number: 10535785
    Abstract: Approaches for foil-based metallization of solar cells and the resulting solar cells are described. For example, a method of fabricating a solar cell involves locating a metal foil above a plurality of alternating N-type and P-type semiconductor regions disposed in or above a substrate. The method also involves laser welding the metal foil to the alternating N-type and P-type semiconductor regions. The method also involves patterning the metal foil by laser ablating through at least a portion of the metal foil at regions in alignment with locations between the alternating N-type and P-type semiconductor regions. The laser welding and the patterning are performed at the same time.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: January 14, 2020
    Assignees: SunPower Corporation, Total Marketing Services
    Inventors: Taeseok Kim, Gabriel Harley, John Wade Viatella, Perine Jaffrennou
  • Patent number: 10170657
    Abstract: Solar cells having emitter regions composed of wide bandgap semiconductor material are described. In an example, a method includes forming, in a process tool having a controlled atmosphere, a thin dielectric layer on a surface of a semiconductor substrate of the solar cell. The semiconductor substrate has a bandgap. Without removing the semiconductor substrate from the controlled atmosphere of the process tool, a semiconductor layer is formed on the thin dielectric layer. The semiconductor layer has a bandgap at least approximately 0.2 electron Volts (eV) above the bandgap of the semiconductor substrate.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: January 1, 2019
    Assignee: SunPower Corporation
    Inventors: Richard M. Swanson, Marius M. Bunea, Michael C. Johnson, David D. Smith, Yu-Chen Shen, Peter J. Cousins, Tim Dennis
  • Patent number: 10109511
    Abstract: A post-processing apparatus of a solar cell carries out a post-processing operation including a main period for heat-treating a solar cell including a semiconductor substrate while providing light to the solar cell. The post-processing apparatus includes a main section to carry out the main period. The main section includes a first heat source unit to provide heat to the semiconductor substrate and a light source unit to provide light to the semiconductor substrate. The first heat source unit and the light source unit are positioned in the main section. The light source unit includes a light source constituted by a plasma lighting system (PLS).
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: October 23, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Kyoungsoo Lee, Minho Choi, Jinhyung Lee, Gyeayoung Kwag, Sangwook Park
  • Patent number: 9620555
    Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Ching-Yao Sun, Jyun-Ru Wu, Ching-Che Huang, Szu-An Wu, Ying-Lang Wang
  • Patent number: 9472745
    Abstract: A process for forming a doped nc-Si thin film thermoelectric material. A nc-Si thin film is slowly deposited on a substrate, either by hot-wire CVD (HWCVD) with a controlled H2:SiH4 ratio R=6-10 or by plasma-enhanced (PECVD) with a controlled R=80-100, followed by ion implantation of an n- or p-type dopant and a final annealing step to activate the implanted dopants and to remove amorphous regions. A doped nc-Si thin film thermoelectric material so formed has both a controllable grain size of from a few tens of nm to 3 nm and a controllable dopant distribution and thus can be configured to provide a thermoelectric material having predetermined desired thermal and/or electrical properties. A final annealing step is used to activate the dopants and remove any residual amorphous regions.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 18, 2016
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Xiao Liu, Thomas H. Metcalf, Daniel R. Queen, Battogtokh Jugdersuren, Qi Wang, William Nemeth
  • Patent number: 9362364
    Abstract: A method of manufacturing one or more graphene devices is disclosed. A thin film growth substrate is formed directly on a device substrate. Graphene is formed on the thin film growth substrate. A transistor is also disclosed, having a device substrate and a source supported by the device substrate. The transistor also has a drain separated from the source and supported by the device substrate. The transistor further has a single layer graphene (SLG) channel grown partially on and coupling the source and the drain. The transistor also has a gate aligned with the SLG channel, and a gate insulator between the gate and the SLG channel. Integrated circuits and other apparati having a device substrate, a thin film growth substrate formed directly on at least a portion of the device substrate, and graphene formed directly on at least a portion of the thin film growth substrate are also disclosed.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: June 7, 2016
    Assignee: CORNELL UNIVERSITY
    Inventors: Jiwoong Park, Carlos Ruiz-Vargas, Mark Philip Levendorf, Lola Brown
  • Patent number: 9287432
    Abstract: Various embodiments of a germanium-on-silicon (Ge—Si) photodiode are provided along with the fabrication method thereof. In one aspect, a Ge—Si photodiode includes a doped bottom region at the bottom of a germanium layer, formed by thermal diffusion of donors implanted into a silicon layer. The Ge—Si photodiode further includes a doped sidewall region of Ge mesa formed by ion implantation. Thus, the electric field is distributed in the intrinsic region of the Ge—Si photodiode where there is low dislocation density. The doped bottom region and sidewall region of the Ge layer prevent electric field from penetrating into the Ge—Si interface and Ge mesa sidewall region, where a large amount of dislocations are distributed. This design significantly suppresses dark current.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: March 15, 2016
    Assignee: SiFotonics Technologies Co, Ltd.
    Inventors: Tuo Shi, Liangbo Wang, Pengfei Cai, Ching-yin Hong, Mengyuan Huang, Wang Chen, Su Li, Dong Pan
  • Patent number: 9213181
    Abstract: A display apparatus includes a first substrate, a plurality of microelectromechanical systems (MEMS) light modulators formed from a structural material coupled to the first substrate and a second substrate separated from the first substrate. A plurality of spacers extend from the first substrate to keep the second substrate a minimum distance away from the plurality of light modulators. The spacers include a first polymer layer having a surface in contact with the first substrate, a second polymer layer encapsulating the first polymer layer and a layer of the structural material encapsulating the second polymer layer. The spacers can be used as fluid barriers and configured to surround more than one but less than all of the MEMS light modulators in the display apparatus.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: December 15, 2015
    Assignee: Pixtronix, Inc.
    Inventors: Timothy J. Brosnihan, Mark B. Andersson, Eugene E. Fike, III, Joyce Wu, J. Lodewyk Steyn
  • Patent number: 9202954
    Abstract: Nanostructures and photovoltaic structures are disclosed. Methods for creating nanostructures are also presented.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: December 1, 2015
    Assignee: Q1 NANOSYSTEMS CORPORATION
    Inventors: Vincent Evelsizer, Larry Bawden, John Fisher
  • Patent number: 9184180
    Abstract: A method of manufacturing a flexible display apparatus includes: preparing a support substrate; forming a first graphene oxide layer having a first electrical charge on the support substrate; forming a second graphene oxide layer having a second electrical charge on the first graphene oxide layer; forming a flexible substrate on the second graphene oxide layer; forming a display unit on the flexible substrate; and separating the support substrate and the flexible substrate from each other.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: November 10, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myung-Soo Huh, Sung-Chul Kim, Suk-Won Jung
  • Patent number: 9166071
    Abstract: A polarization resistant solar cell using an oxygen-rich interface layer is provided. The oxygen-rich interface layer may be comprised of SiOxNy, which may have a graded profile that varies between oxygen-rich proximate to the solar cell to nitrogen-rich distal to the solar cell. A silicon oxide passivation layer may be interposed between the solar cell and the SiOxNy graded dielectric layer. The graded SiOxNy dielectric layer may be replaced with a non-graded SiOxNy dielectric layer and a SiN AR coating.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: October 20, 2015
    Assignee: Silicor Materials Inc.
    Inventors: Bill Phan, Renhua Zhang, John Gorman, Omar Sidelkheir, Jean Patrice Rakotoniaina, Alain Paul Blosse, Martin Kaes
  • Patent number: 9024177
    Abstract: A solar cell includes a doped layer disposed on a first surface of a semiconductor substrate, a doped polysilicon layer disposed in a first region of a second surface of the semiconductor substrate, a doped area disposed in a second region of the second surface, and an insulating layer covering the doped polysilicon layer and the doped area. The insulating layer has openings exposing portions of the doped polysilicon layer and the doped layer, and the doped polysilicon layer and doped layer are respectively connected to a first electrode and a second electrode through the openings. The semiconductor substrate and the doped layer have a first doping type. One of the doped polysilicon layer and the doping area has a second doping type, and the other one of the doped polysilicon layer and the doping area has the first doping type which is opposite to the second doping type.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: May 5, 2015
    Assignee: AU Optronics Corp.
    Inventors: Peng Chen, Shuo-Wei Liang
  • Patent number: 9018033
    Abstract: A method of manufacturing solar cells is disclosed. The method comprises depositing an etch-resistant dopant material on a silicon substrate, the etch-resistant dopant material comprising a dopant source, forming a cross-linked matrix in the etch-resistant dopant material using a non-thermal cure of the etch-resistant dopant material, and heating the silicon substrate and the etch-resistant dopant material to a temperature sufficient to cause the dopant source to diffuse into the silicon substrate.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: April 28, 2015
    Assignee: SunPower Corporation
    Inventors: Kahn C. Wu, Steven M. Kraft, Paul Loscutoff, Steven Edward Molesa
  • Publication number: 20150101658
    Abstract: A photovoltaic device (10) includes a photovoltaic layer (3) in which a p-type semiconductor layer (31), an i-type semiconductor layer (32), and an n-type semiconductor layer (33) are successively stacked. The p-type semiconductor layer (31) is formed from a p-type thin silicon films (311 to 313). The p-type thin silicon films (311 and 312) are formed by depositing silicon thin films having a p-type conductivity type and then by nitriding the silicon thin films using pulse power in which a 100 Hz to 1 kHz low-frequency pulse power is superimposed on a 1 MHz and 50 MHz high-frequency power as plasma excitation power, and using conditions in which the density of the high-frequency power is 100 to 300 mW/cm2, the pressure during plasma processing is 300 to 600 Pa, and the substrate temperature during plasma processing is 140° C. to 190° C. The p-type thin silicon film (313) is deposited under the above conditions.
    Type: Application
    Filed: April 15, 2013
    Publication date: April 16, 2015
    Inventors: Kazuhito Nishimura, Yoshiyuki Nasuno, Shinya Honda, Takashi Yamada
  • Publication number: 20150096611
    Abstract: In order to provide a solar cell device having increased reliability, the present invention is provided with: a substrate having a semiconductor region containing silicon at one primary surface side; a first electrode provided on the one primary surface and containing silver as the primary component; and a second electrode connected to the first electrode on the one primary surface and containing aluminum as the primary component. The first electrode is a solar cell device containing elemental tin.
    Type: Application
    Filed: April 26, 2013
    Publication date: April 9, 2015
    Inventor: Takanobu Yoshida
  • Publication number: 20150090325
    Abstract: Metal seed layers for solar cell conductive contacts and methods of forming metal seed layers for solar cell conductive contacts are described. For example, a solar cell includes a substrate. A semiconductor region is disposed in or above the substrate. A conductive contact is disposed on the semiconductor region and includes a seed layer in contact with the semiconductor region. The seed layer is composed of aluminum (Al) and a second, different, metal.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Richard Hamilton Sewell, Jacob Huffman Woodruff
  • Patent number: 8993373
    Abstract: Methods of doping a solar cell, particularly a point contact solar cell, are disclosed. One surface of a solar cell may require portions to be n-doped, while other portions are p-doped. At least one lithography step can be eliminated by the use of a blanket doping of species having one conductivity and a patterned counterdoping process of species having the opposite conductivity. The areas doped during the patterned implant receive a sufficient dose so as to completely reverse the effect of the blanket doping and achieve a conductivity that is opposite the blanket doping. In some embodiments, counterdoped lines are also used to reduce lateral series resistance of the majority carriers.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: March 31, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas Bateman, John Graff
  • Patent number: 8993372
    Abstract: Exemplary embodiments of a method for producing a semiconductor component having a polycrystalline semiconductor body region are disclosed, wherein the polycrystalline semiconductor body region is produced between the first and second surfaces of the semiconductor body in a semiconductor component section, wherein an electromagnetic radiation having a wavelength of at least 1064 nm is introduced into the semiconductor body in a manner focused onto a position in the semiconductor component section of the semiconductor body and wherein the power density of the radiation at the position is less than 1×108 W/cm2.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: March 31, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Manfred Schneegans, Carsten Ahrens, Adolf Koller, Gerald Lackner, Anton Mauder, Hans-Joachim Schulze
  • Publication number: 20150087104
    Abstract: Embodiments of mechanisms of a backside illuminated image sensor device structure are provided. The method for manufacturing a backside illuminated image sensor device structure includes providing a substrate and forming a polysilicon layer over the substrate. The method further includes forming a buffer layer over the polysilicon layer and forming an etch stop layer over the buffer layer. The method further includes forming a hard mask layer over the etch stop layer and patterning the hard mask layer to form an opening in the hard mask layer. The method further includes performing an implant process through the opening of the hard mask layer to form a doped region in the substrate and removing the hard mask layer by a first removing process. The method further includes removing the etch stop layer by a second removing process and removing the buffer layer by a third removing process.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chung-Chuan TSENG, Chia-Wei LIU, Li-Hsin CHU, Yu-Hsiang TSAI
  • Publication number: 20150083215
    Abstract: A bipolar solar cell includes a backside junction formed by an N-type silicon substrate and a P-type polysilicon emitter formed on the backside of the solar cell. An antireflection layer may be formed on a textured front surface of the silicon substrate. A negative polarity metal contact on the front side of the solar cell makes an electrical connection to the substrate, while a positive polarity metal contact on the backside of the solar cell makes an electrical connection to the polysilicon emitter. An external electrical circuit may be connected to the negative and positive metal contacts to be powered by the solar cell. The positive polarity metal contact may form an infrared reflecting layer with an underlying dielectric layer for increased solar radiation collection.
    Type: Application
    Filed: October 2, 2014
    Publication date: March 26, 2015
    Inventor: Peter John COUSINS
  • Patent number: 8987032
    Abstract: A method for making a solar cell is disclosed. In accordance with the method of the present invention a composite wafer is formed. The composite layer includes a single crystal silicon wafer, a silicon-based device layer and sacrificial porous silicon sandwiched therebetween. The composite wafer is treated to an aqueous etchant maintained below ambient temperatures to selectively etch the sacrificial porous silicon and release or undercut the silicon-based layer from the single crystal silicon wafer. The released silicon device layer is attached to a substrate to make a solar cell and the released single crystal silicon wafer is reused to make additional silicon device layer.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: March 24, 2015
    Inventor: Ismail I. Kashkoush
  • Patent number: 8987588
    Abstract: A solar cell and method of fabricating the same are provided. The substrate of the solar cell has heavily-doped regions and lightly-doped regions. The anode and the cathode are disposed on the back surface of the substrate, and thus the amount of incident light on the front surface of the substrate is increased. The anode and the cathode are in contact with the heavily doped regions to form selective emitter structure, and thus the contact resistance is reduced. The lightly-doped regions, which are not in contact with the anode and the cathode, have lower saturation current, and thus recombination of hole-electron pairs is reduced, and absorption of infrared light is increased.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: March 24, 2015
    Assignee: AU Optronics Corp.
    Inventors: Peng Chen, Shou-Wei Liang
  • Patent number: 8975172
    Abstract: [Object] To provide a method for manufacturing a solar cell element including a semiconductor substrate that includes a high-concentration dopant layer located near the surface of the semiconductor substrate and a low-concentration dopant layer located more inside the semiconductor substrate than the high-concentration dopant layer. [Solving Means] A method includes heating a semiconductor substrate having a first conductivity type in a first atmosphere which contains a dopant having a second conductivity type and which has a first dopant concentration; heating in a second atmosphere the semiconductor substrate heated in the first atmosphere, the second atmosphere having a second dopant concentration less than the first dopant concentration; and heating in a third atmosphere the semiconductor substrate heated in the second atmosphere, the third atmosphere having a third dopant concentration greater than the second dopant concentration.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: March 10, 2015
    Assignee: KYOCERA Corporation
    Inventors: Rui Yatabe, Kenichi Kurobe, Yosuke Inomata
  • Patent number: 8975717
    Abstract: A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 10, 2015
    Assignee: SunPower Corporation
    Inventor: David D. Smith
  • Publication number: 20150062088
    Abstract: A method of forming a photo sensor includes the following steps. A substrate is provided, and a first electrode is formed on the substrate. A first silicon-rich dielectric layer is formed on the first electrode for sensing an infrared ray, wherein the first silicon-rich dielectric layer comprises a silicon-rich oxide layer, a silicon-rich nitride layer, or a silicon-rich oxynitride layer. A second silicon-rich dielectric layer is formed on the first silicon-rich dielectric layer for sensing visible light beams, wherein the second silicon-rich dielectric layer comprises a silicon-rich oxide layer, a silicon-rich nitride layer, or a silicon-rich oxynitride layer. A second electrode is formed on the second silicon-rich dielectric layer.
    Type: Application
    Filed: November 7, 2014
    Publication date: March 5, 2015
    Inventors: An-Thung Cho, Chia-Tien Peng, Hung-Wei Tseng, Cheng-Chiu Pai, Yu-Hsuan Li, Chun-Hsiun Chen, Wei-Ming Huang
  • Patent number: 8952349
    Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 10, 2015
    Assignee: Crossbar, Inc.
    Inventors: Wei Lu, Sung Hyun Jo
  • Patent number: 8945977
    Abstract: A method for producing an opto-microelectronic micro-imaging device includes a step of forming a first functional part on the base of a first substrate, a base layer, and first electric connection pad. The first functional part is transferred onto a second substrate. The first substrate is thinned until the base layer is reached. A second functional part is formed on the base layer. One via is connected to the first electric connection pad and through the first functional part. The step of forming the second functional part includes connecting the via with the second electric connection pad.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: February 3, 2015
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Umberto Rossini, Thierry Flahaut
  • Patent number: 8937024
    Abstract: A process for producing at least one photonic component (32, 33, 35, 39, 41), includes inserting the photonic component (32, 33, 35, 39, 41) into a surface layer (12) of a semiconductor wafer and/or within a semiconductor wafer, especially of a semiconductor chip (11, 31, 34, 38, 40) for the simpler and more cost-effective production with the most desired possible three-dimensional structures. At least one laser beam (22) is coupled into the material of the surface layer (12) and/or of the semiconductor wafer, in which the laser beam (22) is focused at a predetermined depth in the material. At least one property of the material and/or the material structure is changed in the area of focus (23, 36).
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: January 20, 2015
    Assignee: BIAS Bremer Institut für angewandte Strahltechnik GmbH
    Inventors: Ralf Bergmann, Mike Bülters, Vijay Vittal Parsi Sreenivas
  • Publication number: 20150013759
    Abstract: A microcrystalline silicon solar cell structure and a manufacturing method thereof are revealed to comprise a substrate, a n-type semiconductor layer deposited on the substrate, an intrinsic layer deposited on n-type semiconductor layer and a p-type semiconductor layer deposited on the intrinsic layer and a transparent conductive oxide layer on the p-type semiconductor layer, wherein the intrinsic layer also acts as a major light-absorbing layer of the microcrystalline silicon solar cell by doping 8˜12 vppm p-type ions of the group III element therein, which enables to modify the intrinsic layer with slight n type to improve the conversion efficiency of a battery.
    Type: Application
    Filed: June 20, 2014
    Publication date: January 15, 2015
    Inventors: Chie Gau, Yeu-Long Jiang, Pei-Ling Li
  • Publication number: 20150007867
    Abstract: A photoelectric conversion device includes an n-type semiconductor layer and a p-type semiconductor layer, a collecting electrode formed on the n-type semiconductor layer, and a collecting electrode formed on the p-type semiconductor layer, on a back surface opposite to a light receiving surface of an n-type crystalline silicon substrate, and an n-type semiconductor region on a surface on a light receiving surface side of the n-type crystalline silicon substrate, wherein in the n-type semiconductor region, an n-type semiconductor region that is opposed to the n-type semiconductor layer with the n-type crystalline silicon substrate therebetween and an n-type semiconductor region that is opposed to the p-type semiconductor layer with the n-type crystalline silicon substrate therebetween have different average impurity concentrations.
    Type: Application
    Filed: January 31, 2013
    Publication date: January 8, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hidetada Tokioka, Takehiko Sato
  • Publication number: 20150007879
    Abstract: Discussed is a solar cell including a semiconductor substrate, a tunneling layer formed on one surface of the semiconductor substrate, a first conductive semiconductor layer formed on a surface of the tunneling layer and a second conductive semiconductor layer formed on the surface the tunneling layer. A separation portion separates the first and second conductive semiconductor layers from each other, and is formed on the surface of the tunneling layer at a location corresponding to at least a portion of a boundary between the first and second conductive semiconductor layers.
    Type: Application
    Filed: July 3, 2014
    Publication date: January 8, 2015
    Inventors: Hyungjin Kwon, Hyunjung Park, Junghoon Choi, Changseo Park
  • Patent number: 8927428
    Abstract: A process for the formation of at least one aluminum p-doped surface region of an n-type semiconductor substrate comprising the steps: (1) providing an n-type semiconductor substrate, (2) applying and drying an aluminum paste on at least one surface area of the n-type semiconductor substrate, (3) firing the dried aluminum paste, and (4) removing the fired aluminum paste with water, wherein the aluminum paste employed in step (2) includes particulate aluminum, an organic vehicle and 3 to 20 wt. % of glass frit, based on total aluminum paste composition.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: January 6, 2015
    Assignee: E I du Pont de Nemours and Company
    Inventors: Kenneth Warren Hang, Alistair Graeme Prince, Michael Rose, Richard John Sheffield Young
  • Patent number: 8916772
    Abstract: A three-dimensional thin-film semiconductor substrate with selective through-holes is provided. The substrate having an inverted pyramidal structure comprising selectively formed through-holes positioned between the front and back lateral surface planes of the semiconductor substrate to form a partially transparent three-dimensional thin-film semiconductor substrate.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: December 23, 2014
    Assignee: Solexel, Inc.
    Inventors: Mehrdad M. Moslehi, David Xuan-Qi Wang
  • Patent number: 8906734
    Abstract: A photovoltaic device and method include a crystalline substrate and an emitter contact portion formed in contact with the substrate. A back-surface-field junction includes a homogeneous junction layer formed in contact with the crystalline substrate and having a same conductivity type and a higher active doping density than that of the substrate. The homogeneous junction layer includes a thickness less than a diffusion length of minority carriers in the homogeneous junction layer. A passivation layer is formed in contact with the homogeneous junction layer opposite the substrate, which is either undoped or has the same conductivity type as that of the substrate.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Bahman Hekmatshoartabari, Devendra K. Sadana, Davood Shahrjerdi
  • Patent number: 8901413
    Abstract: Disclosed is a photovoltaic device. The photovoltaic device includes: a flexible substrate; a first electrode and a second electrode located over the flexible substrate; and at least one unit cell located between the first electrode and the second electrode, wherein the first electrode includes a transparent conductive oxide layer, wherein a texturing structure is formed on the transparent conductive oxide layer, and wherein a ratio of a root mean square (rms) roughness to an average pitch of the texturing structure is equal to or more than 0.05 and equal to or less than 0.13.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: December 2, 2014
    Assignee: Intellectual Discovery Co., Ltd.
    Inventor: Seung-Yeop Myong
  • Patent number: 8895435
    Abstract: The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: November 25, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Yun-Ren Wang, Ying-Wei Yen, Wen-Yi Teng, Chan-Lon Yang
  • Patent number: 8878053
    Abstract: A bipolar solar cell includes a backside junction formed by an N-type silicon substrate and a P-type polysilicon emitter formed on the backside of the solar cell. An antireflection layer may be formed on a textured front surface of the silicon substrate. A negative polarity metal contact on the front side of the solar cell makes an electrical connection to the substrate, while a positive polarity metal contact on the backside of the solar cell makes an electrical connection to the polysilicon emitter. An external electrical circuit may be connected to the negative and positive metal contacts to be powered by the solar cell. The positive polarity metal contact may form an infrared reflecting layer with an underlying dielectric layer for increased solar radiation collection.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: November 4, 2014
    Assignee: SunPower Corporation
    Inventor: Peter John Cousins
  • Patent number: 8871548
    Abstract: A diode has a first contact of a material having a first conductivity type, a second contact of a material having a second conductivity type arranged co-planarly with the first contact, a channel arranged co-planarly between the first and second contacts, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate. A diode has a layer of material arranged on a substrate, a first region of material doped to have a first conductivity type, a second region of material doped to have a second conductivity type, a channel between the first and second regions formed of an undoped region, a gate arranged adjacent the channel, and a voltage source electrically connected to the gate.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: October 28, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Jengping Lu, Raj B. Apte
  • Patent number: 8871552
    Abstract: Although Cl (chlorine) is no longer supplied in the course of a first process in which a detecting layer formed by a polycrystalline film or a polycrystalline lamination film by vapor deposition or sublimation is formed, an additional source (e.g., HCl of Cl-containing gas) other than a source is supplied at the start or in the course of the first process. Thus, the detecting layer as the polycrystalline film or the polycrystalline lamination film of CdTe, ZnTe, or CdZnTe can be doped with Cl uniformly in a thickness direction from the start until the end of the first process in film formation. As a result, uniform crystal particles and uniform detection characteristics can be achieved.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: October 28, 2014
    Assignees: Shimadzu Corporation, Institute of National Colleges of Technology, Japan
    Inventors: Satoshi Tokuda, Koichi Tanabe, Toshinori Yoshimuta, Hiroyuki Kishihara, Masatomo Kaino, Akina Yoshimatsu, Toshiyuki Sato, Shoji Kuwabara
  • Publication number: 20140305501
    Abstract: Methods of fabricating back-contact solar cells and devices thereof are described. A method of fabricating a back-contact solar cell includes forming an N-type dopant source layer and a P-type dopant source layer above a material layer disposed above a substrate. The N-type dopant source layer is spaced apart from the P-type dopant source layer. The N-type dopant source layer and the P-type dopant source layer are heated. Subsequently, a trench is formed in the material layer, between the N-type and P-type dopant source layers.
    Type: Application
    Filed: June 25, 2014
    Publication date: October 16, 2014
    Inventors: Bo Li, David Smith, Peter Cousins
  • Patent number: 8859320
    Abstract: Disclosed in a method that is for producing a solar cell and that is characterized by performing an annealing step on a semiconductor substrate before an electrode-forming step. By means of performing annealing in the above manner, it is possible to improve the electrical characteristics of the solar cell without negatively impacting reliability or outward appearance. As a result, the method can be widely used in methods for producing solar cells having high reliability and electrical characteristics.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: October 14, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Ryo Mitta, Mitsuhito Takahashi, Hiroshi Hashigami, Takashi Murakami, Shintarou Tsukigata, Takenori Watabe, Hiroyuki Otsuka
  • Patent number: 8853521
    Abstract: The present disclosure presents a partially-transparent (see-through) three-dimensional thin film solar cell (3-D TFSC) substrate. The substrate includes a plurality of unit cells. Each unit cell structure has the shape of a truncated pyramid, and its parameters may be varied to allow a desired portion of sunlight to pass through.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: October 7, 2014
    Assignee: Solexel, Inc.
    Inventors: Mehrdad Moslehi, David Xuan-Qi Wang
  • Patent number: 8853524
    Abstract: A solar cell and method of fabrication are disclosed. In one embodiment of the present invention, the method comprises depositing a first doped amorphous silicon layer on a first surface of a silicon substrate, depositing a second doped amorphous silicon layer on the first surface of the silicon substrate. The second doped amorphous silicon layer is doped oppositely from the first doped amorphous silicon layer. An anneal is performed to transform the first doped amorphous silicon layer and second doped amorphous silicon layer to crystalline silicon layers.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventor: Harold John Hovel
  • Patent number: 8847223
    Abstract: A method of forming a photosensitive pattern on a substrate with a photosensitive layer disposed thereon may include moving at least one of the substrate and a set of micro-mirrors in a first direction, the set of micro-mirrors being disposed above the substrate and being arranged as an array, the array having a first edge extending in a second direction, the second direction being at an acute angle with respect to the first direction. The method may also include selectively turning on one or more micro-mirrors of the set of micro-mirrors according to a position of the set of micro-mirrors relative to the photosensitive layer, thereby irradiating one or more spot beams on the photosensitive layer. The photosensitive layer exposed by the spot beams is developed to form a photosensitive pattern having an edge portion extending in a third direction crossing the first and second directions.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: September 30, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung-In Park, Su-Yeon Sim, Sang-Hyun Yun, Cha-Dong Kim, Hi-Kuk Lee
  • Publication number: 20140261670
    Abstract: A solar cell, having a front side which faces the sun during normal operation, and a back side opposite the front side can include a silicon substrate having doped regions and a polysilicon layer disposed over the doped regions. The solar cell can include a conductive filling formed between a first metal layer and doped regions and through or at least partially through the polysilicon layer, where the conductive filling electrically couples the first metal layer and the doped region. In an embodiment, a second metal layer is formed on the first metal layer, where the first metal layer and the conductive filling electrically couple the doped regions and the second metal layer. In some embodiments, the solar cell can be a front contact solar cell or a back contact solar cell.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Inventor: Xi Zhu
  • Patent number: 8828784
    Abstract: Methods and structures for extracting at least one electric parametric value from a back contact solar cell having dual level metallization are provided.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: September 9, 2014
    Assignee: Solexel, Inc.
    Inventors: Swaroop Kommera, Pawan Kapur, Mehrdad M. Moslehi
  • Patent number: 8828781
    Abstract: Photovoltaic devices are produced using a minimally modified standard process flow by forming lateral P-I-N light-sensitive diodes on silicon islands that are isolated laterally by trenches performed by RIE, and from an underlying support substrate by porous silicon regions. P+ and N+ doped regions are formed in a P? epitaxial layer, trenches are etched through the epitaxial layer into a P+ substrate, a protective layer (e.g., SiN) is formed on the trench walls, and then porous silicon is formed (e.g., using HF solution) in the trenches that grows laterally through the P+ substrate and merges under the island. The method is either utilized to form low-cost embedded photovoltaic arrays on CMOS IC devices, or the devices are separated from the P+ substrate by etching through the porous silicon to produce low-cost, high voltage solar arrays for solar energy sources, e.g., solar concentrators.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 9, 2014
    Assignees: Tower Semiconductor Ltd., Yissum Research Development Company of the Hebrew University of Jerusalem Ltd.
    Inventors: Yakov Roizin, Evgeny Pikhay, Irit Chen-Zamero, Ora Eli, Micha Asscher, Amir Saar
  • Patent number: 8828783
    Abstract: A reverse p-n junction solar cell device and methods for forming the reverse p-n junction solar cell device are described. A variety of n-p junction and reverse p-n junction solar cell devices and related methods of manufacturing are provided. N-intrinsic-p junction and reverse p-intrinsic-n junction solar cell devices are also described.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: September 9, 2014
    Assignee: Uriel Solar, Inc.
    Inventor: James David Garnett
  • Publication number: 20140248739
    Abstract: A multi-ingot furnace for the growth of crystalline semiconductor material has one or more heating devices for heating a hot zone in which crucibles containing semiconductor material are received. At least one of the heating devices is arranged to apply a predetermined differential heat flux profile across a horizontal cross-section of the semiconductor material in one or more of the crucibles, the predetermined differential heat flux profile being selected in dependence the position of the one or more crucibles in an array. In this manner, the heating device can at least partially compensate for differences in the temperature across the semiconductor material that arises from its geometric position in the furnace. This reduces the possibility of defects such as dislocations during the growth of a crystalline semiconductor material. Associated methods are also disclosed.
    Type: Application
    Filed: July 19, 2012
    Publication date: September 4, 2014
    Inventors: Per Bakke, Egor Vladimirov, Pouria Homayonifar, Alexandre Teixeira