Responsive To Electromagnetic Radiation Patents (Class 438/57)
  • Patent number: 10270000
    Abstract: A multijunction solar cell and its method of manufacture including interconnected first and second discrete semiconductor regions disposed adjacent and parallel to each other in a single semiconductor body, including first top subcell, second (and possibly third) lattice matched middle subcells; a graded interlayer adjacent to the last middle solar subcell; and a bottom solar subcell adjacent to said graded interlayer being lattice mismatched with respect to the last middle solar subcell; wherein the interconnected regions form at least a four junction solar cell by a series connection being formed between the bottom solar subcell in the first semiconductor region and the bottom solar subcell in the second semiconductor region.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: April 23, 2019
    Assignee: SolAero Technologies Corp.
    Inventor: Daniel Derkacs
  • Patent number: 10256359
    Abstract: A multijunction solar cell and its method of manufacture including interconnected first and second discrete semiconductor regions disposed adjacent and parallel to each other in a single semiconductor body, including first top subcell, second (and possibly third) lattice matched middle subcells; and a bottom solar subcell adjacent to said last middle subcell and lattice matched thereto; wherein the interconnected regions form at least a four junction solar cell by a series connection being formed between the bottom solar subcell in the first semiconductor region and the bottom solar subcell in the second semiconductor region.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: April 9, 2019
    Assignee: SolAero Technologies Corp.
    Inventor: Daniel Derkacs
  • Patent number: 10249580
    Abstract: In conventional device packages, separate standalone inductors are provided and mounted on an interposer substrate along with a die. Separate inductors reduce integration density, decrease flexibility, increase footprint, and generally increase costs. To address such disadvantages, it is proposed to provide a part of an inductor in a substrate below a die. The proposed stacked substrate inductor may include a first inductor in a first substrate, a second inductor in a second a second substrate stacked on the first substrate, and an inductor interconnect coupling the first and second inductors. The core regions of the first and second inductors may overlap with each other at least partially. The proposed stacked substrate inductor may enhance integration density, increase flexibility, decrease footprint, and/or reduce costs.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: April 2, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, Changhan Hobie Yun, David Francis Berdy, Chengjie Zuo, Mario Francisco Velez, Jonghae Kim
  • Patent number: 10211243
    Abstract: A method of image sensor package fabrication includes providing an image sensor, including a pixel array disposed in a semiconductor material, and a first transparent shield adhered to the semiconductor material. The pixel array is disposed between the semiconductor material and the first transparent shield. A light blocking layer is deposited and disposed between lateral edges of the pixel array and lateral edges of the first transparent shield, and a second transparent shield is placed on the image sensor package, where the light blocking layer is disposed between the first transparent shield and the second transparent shield.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: February 19, 2019
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chia-Chun Miao, Yin Qian, Chao-Hung Lin, Chen-Wei Lu, Dyson H. Tai, Ming Zhang, Jin Li
  • Patent number: 10153310
    Abstract: A photon detection device includes a single photon avalanche diode (SPAD) disposed in a semiconductor layer. A guard ring structure is disposed in the semiconductor layer surrounding the SPAD to isolate the SPAD. A well region is disposed in the semiconductor layer surrounding the guard ring structure and disposed along an outside perimeter of the photon detection device. A contact region is disposed in the well region only in a corner region of the outside perimeter such that there is no contact region disposed along side regions of the outside perimeter. A distance between an inside edge of the guard ring structure and the contact region in the corner region of the outside perimeter is greater than a distance between the inside edge of the guard ring structure and the side regions of the outside perimeter such that an electric field distribution is uniform around the photon detection device.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: December 11, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Bowei Zhang, Vincent Venezia, Gang Chen, Dyson H. Tai, Duli Mao
  • Patent number: 10141466
    Abstract: Provided is a substrate for a solar cell, wherein a flat chamfered portion is formed on one corner of a silicon substrate having a square shape in a planar view, or a notch is formed on the corner or close to the corner. This invention makes it possible to easily check the position of the substrate and determine the direction of the substrate in a solar cell manufacturing step, and suppresses failures generated due to the direction of the substrate.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: November 27, 2018
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hideo Ooiwa, Takenori Watabe, Hiroyuki Otsuka, Kazuo Hara
  • Patent number: 10109672
    Abstract: An electrically-powered device, structure and/or component is provided that includes an attached electrical power source in a form of a unique, environmentally-friendly energy harvesting element or component. The energy harvesting component provides a mechanism for generating autonomous renewable energy, or a renewable energy supplement, in the integrated circuit system, structure and/or component. The energy harvesting element includes a first conductor layer, a low work function layer, a dielectric layer, and a second conductor layer that are particularly configured in a manner to promote electron migration from the low work function layer, through the dielectric layer, to the facing surface of the second conductor layer in a manner that develops an electric potential between the first conductor layer and the second conductor layer. The energy harvesting component includes a plurality of energy harvesting elements electrically connected to one another to increase an electrical power output.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 23, 2018
    Assignee: Face International Corporation
    Inventors: Clark D Boyd, Bradbury R Face, Jeffrey D Shepard
  • Patent number: 10109752
    Abstract: A transparent electrode can include a graphene sheet on a substrate, a layer including a conductive polymer disposed over the graphene sheet, and a plurality of semiconducting nanowires, such as ZnO nanowires, disposed over the layer including the conductive polymer.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 23, 2018
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Hyesung Park, Sehoon Chang, Jing Kong, Silvija Gradecak
  • Patent number: 10096640
    Abstract: Certain embodiments provide a solid-state imaging apparatus including a first impurity layer, a second impurity layer, a third impurity layer, and an electrode. The first impurity layer is a photoelectric conversion layer, and is formed to have a constant depth on a semiconductor substrate. The second impurity layer is formed on a surface of the first impurity layer, to have a depth which becomes shallower toward a direction from the first impurity layer to the third impurity layer. The third impurity layer is formed in a position spaced apart from the first impurity layer and the second impurity layer on the surface of the semiconductor substrate. The electrode can transport electric charges from the first impurity layer to the third impurity layer, and is formed between the second impurity layer and the third impurity layer, on the surface of the semiconductor substrate.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: October 9, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoyuki Arai, Fumiaki Sano
  • Patent number: 9994684
    Abstract: Described is a doping technique that forms a stable amorphous silicon film and a stable polycrystalline silicon film at a low temperature and simultaneously that imparts conductivity in an atmospheric pressure environment. A method for producing a compound containing a bond between different elements belonging to Group 4 to Group 15 of the periodic table, the method including: applying, at a low frequency and atmospheric pressure, high voltage to an inside of an electric discharge tube obtained by attaching high-voltage electrodes to a metal tube or an insulator tube or between flat plate electrodes while passing an introduction gas, so as to convert molecules present in the electric discharge tube or between the flat plate electrodes into a plasma; and applying the plasma to substances to be irradiated, the substances to be irradiated being two or more elementary substances or compounds.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: June 12, 2018
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Hitoshi Furusho, Yuki Nohara, Hisayuki Watanabe, Yuichi Goto
  • Patent number: 9985077
    Abstract: The present invention relates to a serial module of organic solar cells and the method for manufacturing the same. The structure comprises a transparent conductive layer composed by a plurality of conductive blocks, an active layer having notches on the periphery, and a metal layer composed by a plurality of metal blocks. The active layer according to the present invention is a complete layer except the notches on the periphery for exposing a portion of the transparent conductive layer. The metal blocks can contact the conductive blocks of adjacent organic solar cell via the exposure areas and thus connecting the organic solar cells in series. The present invention can improves the power generating efficiency of organic solar cells in a limited space, which is beneficial to the development of promotion of future organic solar cells.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: May 29, 2018
    Assignee: ATOMIC ENERGY COUNCIL—INSTITUTE OF NUCLEAR ENERGY RESEARCH
    Inventors: Yu-Ching Huang, De-Han Lu, Hou-Chin Cha, Cheng-Wei Chou, Chih-Min Chuang, Yeong-Der Lin, Charn-Ying Chen, Cheng-Si Tsao
  • Patent number: 9972492
    Abstract: Provided is a method of doping a substrate. The method includes providing the substrate, providing a target material on the substrate, and implanting a dopant of the target material into the substrate by providing a laser beam to the target material.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: May 15, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Moon Youn Jung, Jisu Lee
  • Patent number: 9954121
    Abstract: Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: April 24, 2018
    Assignee: Artilux Inc.
    Inventors: Szu-Lin Cheng, Shu-Lu Chen
  • Patent number: 9955087
    Abstract: Photodetectors based on hydrogen-doped, single-crystalline germanium, including waveguide integrated photodetectors for photonic chip applications are provided. Hydrogen doping provides the single-crystalline germanium with increased radiation absorption in the near infrared region of the electromagnetic spectrum, including at wavelengths of 1550 nm and above.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 24, 2018
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Munho Kim
  • Patent number: 9905602
    Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 27, 2018
    Assignee: Sony Corporation
    Inventors: Hiroshi Takahashi, Shunichi Sukegawa, Keishi Inoue
  • Patent number: 9893224
    Abstract: A system and method of patterning dopants of opposite polarity to form a solar cell is described. Two dopant films are deposited on a substrate. A laser is used to pattern the N-type dopant, by mixing the two dopant films into a single film with an exposure to the laser and/or drive the N-type dopant into the substrate to form an N-type emitter. A thermal process drives the P-type dopant from the P-type dopant film to form P-type emitters and further drives the N-type dopant from the single film to either form or further drive the N-type emitter.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: February 13, 2018
    Assignee: SunPower Corporation
    Inventors: Paul Loscutoff, Gabriel Harley
  • Patent number: 9893117
    Abstract: A pixel structure comprises an epitaxial layer (1) of a first conductivity type. A photo-sensitive element comprises a first region (4) of a second conductivity type and a second region (3) of the first conductivity type positioned between the epitaxial layer (1) and the first region (4). A charge storage node (ø2) is arranged to store charges acquired by the photo-sensitive element, or to form part of a charge storage element. A third region (2) of the second conductivity type is positioned between the charge storage node and the epitaxial layer. The pixel structure further comprises a charge-to-voltage conversion element (13) for converting charges from the charge storage node to a voltage signal and an output circuit (21, 22) for selectively outputting the voltage signal from the pixel structure.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: February 13, 2018
    Assignee: CMOSIS BVBA
    Inventors: Guy Meynants, Koen Van Wichelen
  • Patent number: 9887234
    Abstract: A complementary metal oxide semiconductor (CMOS) image sensor and a method for fabricating the same are provided. An example CMOS image sensor includes first active regions of a semiconductor substrate, where the first active regions are arranged in rows or columns. Photosensitive regions are formed in the first active regions. The CMOS image sensor also includes second active regions of the semiconductor substrate that are interposed between the first active regions. Each of the second active regions includes a device isolation region formed by doping the semiconductor substrate with impurities. Each of the second active regions also includes a channel region of a field effect transistor (FET) that is formed within the device isolation region and is configured to connect source and drain regions of the FET. At least one control gate is formed over each of the second active regions.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Min-Feng Kao, Wei-Cheng Hsu, Tzu-Jui Wang, Hsiao-Hui Tseng, Tzu-Hsuan Hsu, Jen-Cheng Liu, Jhy-Jyi Sze, Dun-Nian Yaung
  • Patent number: 9884966
    Abstract: Photovoltaic devices such as solar cells, hybrid solar cell-batteries, and other such devices may include an active layer disposed between two electrodes. The active layer may have perovskite material and other material such as mesoporous material, interfacial layers, thin-coat interfacial layers, and combinations thereof. The perovskite material may be photoactive. The perovskite material may be disposed between two or more other materials in the photovoltaic device. Inclusion of these materials in various arrangements within an active layer of a photovoltaic device may improve device performance. Other materials may be included to further improve device performance, such as, for example: additional perovskites, and additional interfacial layers.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: February 6, 2018
    Assignee: Hee Solar, L.L.C.
    Inventors: Michael D. Irwin, Jerred A. Chute, Vivek V. Dhas
  • Patent number: 9888156
    Abstract: A photoelectric conversion apparatus includes a photoelectric conversion unit having a light incident surface and including: a first electrode; a second electrode disposed further toward the light incident surface; and a photoelectric conversion layer disposed between the first and second electrodes. The photoelectric conversion apparatus includes a member in contact with the photoelectric conversion layer and constituting a light guide together with the layer. An area of a first surface parallel to the light incident surface at a portion of the photoelectric conversion layer surrounded by the member is smaller than an area of a second surface disposed between the first surface and the second electrode at a portion of the photoelectric conversion layer surrounded by the member, and an area of orthogonal projection to the light incident surface of the first electrode is smaller than an area of orthogonal projection to the light incident surface of the second surface.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: February 6, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takashi Matsuda, Sho Suzuki, Hidekazu Takahashi, Nobuhiko Sato
  • Patent number: 9881906
    Abstract: According to one embodiment, a semiconductor module includes: a substrate; a first interconnect layer provided on the substrate; a plurality of first semiconductor elements provided on the first interconnect layer, each of the first semiconductor elements having a first electrode, a second electrode, and a third electrode, and the second electrode being electrically connected to the first interconnect layer; a plurality of first rectifying elements provided on the first interconnect layer, each of the first rectifying elements having a fourth electrode and a fifth electrode, and the fifth electrode being electrically connected to the first interconnect layer; and a second interconnect layer provided on the substrate, and the second interconnect layer being electrically connected to the first electrode and the fourth electrode. The second interconnect layer includes a corrugated surface or the first interconnect layer includes a corrugated surface.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: January 30, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Matsuyama
  • Patent number: 9859314
    Abstract: A curved image sensor chip has a first side and a second side opposite the first side. The second side includes light sensors configured to generate electrical signals in response to receiving light. A substrate is in contact with the first side of the curved image sensor chip and is configured to increase in volume so as to apply a bending force to form the curved image sensor chip.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: January 2, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Geoffrey P. McKnight, John J. Vajo, Jason A. Graetz
  • Patent number: 9741893
    Abstract: An amorphous-silicon photoelectric device and a fabricating method thereof are disclosed. The amorphous-silicon photoelectric device includes: a substrate; a thin-film transistor and a photosensor with the photodiode structure, which are provided at different positions on the substrate; and a contact layer; in which the contact layer is located below the photosensor, and the contact layer is partially covered by the photosensor, moreover, the contact layer and the gate-electrode layer in the thin-film transistor are provided in a same layer and of a same material. According to the technical solutions of the present disclosure, the fabricating procedure of an a-Si photoelectric device can be simplified, thereby improving the fabrication efficiency and reducing costs.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: August 22, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhenyu Xie, Xu Chen, Shaoying Xu
  • Patent number: 9698196
    Abstract: A demodulation pixel improves the charge transport speed and sensitivity by exploiting two effects of charge transport in silicon in order to achieve the before-mentioned optimization. The first one is a transport method based on the CCD gate principle. However, this is not limited to CCD technology, but can be realized also in CMOS technology. The charge transport in a surface or even a buried channel close to the surface is highly efficient in terms of speed, sensitivity and low trapping noise. In addition, by activating a majority carrier current flowing through the substrate, another drift field is generated below the depleted CCD channel. This drift field is located deeply in the substrate, acting as an efficient separator for deeply photo-generated electron-hole pairs. Thus, another large amount of minority carriers is transported to the diffusion nodes at high speed and detected.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: July 4, 2017
    Assignee: Heptagon Micro Optics Pte. Ltd.
    Inventors: Bernhard Buettgen, Jonas Felber, Michael Lehmann, Thierry Oggier
  • Patent number: 9685581
    Abstract: A manufacturing method of a solar cell having diffusion layers of different conductivity types on a front surface of a semiconductor substrate and a back surface thereof, respectively, includes a step of forming a diffusion protection mask containing impurities to cover at least a partial region of the semiconductor substrate, and a diffusion step of performing a diffusion step including a thermal step in a state where at least the partial region of the semiconductor substrate is covered with the diffusion protection mask containing impurities, forming a first-impurity diffusion layer in a first region covered with the diffusion protection mask, and forming a second-impurity diffusion layer having a different impurity concentration or a different conductivity type from that of the diffusion protection mask in a second region exposed from the diffusion protection mask.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: June 20, 2017
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Hayato Kohata
  • Patent number: 9653502
    Abstract: There is provided a solid-state imaging device including a semiconductor substrate having an effective region in which a photodiode performing a photoelectric conversion is formed and, an optical black region shielded by a light shielding film; a first film which is formed on the effective region and in which at least one layer or more of layers having a negative fixed charge are laminated; and a second film which is formed on the light shielding region and in which at least one layer or more of layers having a negative fixed charge are laminated, in which the number of layers formed in the first film is different from the number of layers formed in the second film.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: May 16, 2017
    Assignee: Sony Corporation
    Inventor: Kai Yoshitsugu
  • Patent number: 9620666
    Abstract: A diffusing agent composition including a condensation product and an impurity diffusion component. The condensation product is a reaction product resulting from hydrolysis of an alkoxysilane. The impurity diffusion component is a monoester or diester of phosphoric acid, or a mixture thereof.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: April 11, 2017
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Toshiro Morita, Takashi Kamizono
  • Patent number: 9553119
    Abstract: Methods of forming an image sensor are provided. A method of forming an image sensor includes forming a trench in a substrate to define a unit pixel region of the substrate. The method includes forming an in-situ-doped passivation layer on an exposed surface of the trench. The method includes forming a capping pattern on the in-situ-doped passivation layer, in the trench. The method includes forming a photoelectric conversion region in the unit pixel region. Moreover, the method includes forming a floating diffusion region in the unit pixel region.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: January 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Young Choi, Taegon Kim, JunHyun Cho
  • Patent number: 9520517
    Abstract: A solar cell including a non-amorphous semiconductor substrate of a first conductive type; at least a first semiconductor layer on the non-amorphous semiconductor substrate, the first semiconductor layer including a portion that is amorphous and a plurality of portions having crystal lumps, so that the plurality of portions having the crystal lumps are distributed in the first semiconductor layer; a first electrode on the semiconductor substrate; and a second electrode on the semiconductor substrate.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: December 13, 2016
    Assignee: LG ELECTRONICS INC.
    Inventors: Hyunjin Yang, Heonmin Lee, Junghoon Choi, Kwangsun Ji
  • Patent number: 9515139
    Abstract: A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: December 6, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Anton Arriagada, Michael A. Stuber, Stuart B. Molin
  • Patent number: 9502597
    Abstract: The invention relates to a method for manufacturing a photovoltaic module comprising a plurality of solar cells in a thin-layer structure, in which the following are consecutively formed: an electrode on the rear surface (41), a photovoltaic layer (46) obtained by depositing a layer (42) of precursors and by annealing such as to convert the precursors into a semiconductor material, and another semiconductor layer (43) in order to create a pn junction with the photovoltaic layer (46); characterized in that the layer (42) is deposited in a localized manner, such as to leave free at least one area (410) of the electrode on the rear surface (41) placed between two adjacent cells, wherein the annealing step modifies said area (410) which has higher resistivity than the rest of the electrode on the rear surface (41), such as to provide electric insulation between two adjacent cells.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: November 22, 2016
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Joel Dufourcq, Sevak Amtablian, Nicolas Karst, Frederic Roux
  • Patent number: 9498799
    Abstract: A method for removing non-bonding compounds from absorber layers of a plurality of absorber substrates during a cleaning process comprises setting one or more conditions of a solution in a solvent tank used to clean the non-bonding compounds from the absorber layers of the absorber substrates. The method further comprises calculating thickness of boundary layers formed on the absorber layers based on hydrodynamics of the solution in the solvent tank during the cleaning process, and setting one or more of spacing between the absorber substrates and circulation speed of the solution in the solvent tank during the cleaning process. The method further comprises immersing and cleaning the absorber substrates in the solvent tank under one or more of the set conditions, spacing and circulation speed of the solution.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Wei Chen
  • Patent number: 9496302
    Abstract: The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate having a first type of dopant; a semiconductor layer having a second type of dopant different from the first type of dopant and disposed on the semiconductor substrate; and an image sensor formed in the semiconductor layer.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: November 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chung-Wei Chang, Han-Chi Liu, Chun-Yao Ko, Shou-Gwo Wuu
  • Patent number: 9482834
    Abstract: A semiconductor optical device includes a substrate including first and second regions arranged in a first direction, a photodiode disposed on the first region, an optical waveguide disposed on the second region, and a buried layer disposed on a side surface of the photodiode. The side surface of the photodiode extends in the first direction. The photodiode has a first end surface intersecting with the first direction, and the optical waveguide is in direct contact with the first end surface. The buried layer is composed of a III-V compound semiconductor doped with a transition metal. The photodiode includes a stacked semiconductor layer including a first cladding layer, a light-absorbing layer and a second cladding layer stacked in that order on the substrate. The light-absorbing layer has a side surface having at least a portion recessed with respect to a side surface of the first cladding layer.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: November 1, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takehiko Kikuchi, Hideki Yagi, Yoshihiro Yoneda
  • Patent number: 9478737
    Abstract: The present invention provides a memory structure including a resistance-changing storage element, which enables a reset operation with a reset gate and in which cross-sectional areas of a resistance-changing film and a lower electrode in a current-flowing direction can be decreased.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: October 25, 2016
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9472706
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device are disclosed. The method includes forming a trench, in a vertical direction of a semiconductor substrate having a plurality of photoelectric converting elements arranged on the semiconductor device, at positions between the photoelectric converting elements that are next to each other, forming a first conductive-material layer in and above the trench by implanting a first conductive material into the trench after an oxide film is formed on an inner wall of the trench, forming a first conductor by removing the first conductive-material layer excluding a first conductive portion of the first conductive-material layer implanted into the trench, and forming an upper gate electrode above the first conductor, the upper gate electrode configured to be conductive with the first conductor. The semiconductor device includes a semiconductor substrate, an image sensor, a trench, a first conductor, and an upper gate electrode.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: October 18, 2016
    Assignee: RICOH COMPANY, LTD.
    Inventors: Katsuyuki Sakurano, Takaaki Negoro, Katsuhiko Aisu, Kazuhiro Yoneda, Yasukazu Nakatani, Hirofumi Watanabe
  • Patent number: 9455296
    Abstract: A solid-state imaging device in which a pixel circuit formed on the first surface side of a semiconductor substrate is shared by a plurality of light reception regions and second surface side of the semiconductor substrate is the light incident side of the light reception regions. The second surface side regions of the light reception regions are arranged at approximately even intervals and the first surface side regions of the light reception regions e are arranged at uneven intervals. Respective second surface side regions and first surface side regions are joined in the semiconductor substrate so that the light reception regions extend from the second surface side to the first surface side of the semiconductor substrate.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: September 27, 2016
    Assignee: Sony Corporation
    Inventor: Keiji Mabuchi
  • Patent number: 9455093
    Abstract: A dye-sensitized solar cell that includes an electrode having a semiconductor nanoparticle layer dispersed on a transparent conductive substrate, a plurality of semiconductor nanofibers dispersed on the nanoparticle layer, a first light absorption material is attached to the plurality of semiconductor nanofibers in which the first light absorption material having a first light absorption bandwidth, and a second light absorption material deposited on the light absorption material of the plurality of semiconductor nanofibers, the second light absorption material having a second light absorption bandwidth complementary to the first light absorption bandwidth, a counter electrode includes a metal-coated transparent conductive substrate, and an electrolyte in contact with the near-infrared light absorption material and the counter electrode.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: September 27, 2016
    Assignee: THE HONG KONG POLYTECHNIC UNIVERSITY
    Inventors: Wallace Woon-fong Leung, Lijun Yang
  • Patent number: 9437427
    Abstract: After oxidizing a sacrificial semiconductor layer composed of silicon germanium that is located over an insulator layer to form a germanium-enriched region located within a first end of the sacrificial semiconductor layer and having a greater germanium concentration than a remaining portion of the sacrificial semiconductor layer, the remaining portion of the sacrificial semiconductor layer is removed to provide a trench. Next, a semiconductor barrier layer is formed on a sidewall of the germanium-enriched region that is exposed by the trench. A III-V compound semiconductor layer is formed within the trench by a lateral epitaxial semiconductor regrowth process.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: September 6, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Lukas Czornomaz, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9373510
    Abstract: Disclosed is a method for manufacturing a semiconductor device, including: forming a first material layer including holes exposing a part of an ion injection target layer on the ion injection target layer; forming gap filling layers having a smaller height than that of the holes inside the holes; forming a second material layer on the gap filling layers and the first material layer; forming ion injection mask patterns exposing the gap filling layer by removing the second material layer formed on the gap filling layer in the second material layer; exposing a part of the ion injection target layer through inner portions of the holes by removing the exposed gap filling layer; and performing an ion injection process on the exposed ion injection target layer.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: June 21, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jong Hoon Kim
  • Patent number: 9340873
    Abstract: Provided is a semiconductor device manufacturing method including: (a) supplying a source gas containing a first element and chlorine to a substrate accommodated in a processing chamber to form an adsorption layer of the source gas on the substrate; (b) supplying a chlorine-containing gas having a composition different from that of the source gas to the substrate while supplying the sources gas before an adsorption of the source gas to the substrate is saturated to suppress the adsorption of the source gas to the substrate; (c) removing the source gas and the chlorine-containing gas remaining on the substrate; (d) supplying a modifying gas including a second element to the substrate to form a layer including the first element and the second element on the substrate by modifying the adsorption layer of the source gas; and (e) removing the modifying gas remaining on the substrate.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: May 17, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tatsuyuki Saito, Masanori Sakai, Yukinao Kaga, Takashi Yokogawa
  • Patent number: 9331221
    Abstract: Separation layers, usable in devices for converting radiation energy to electrical energy, allow at least some of the components of the devices to be separated from one another for disposal thereof. A separation layer may be interposed between and bonded to adjoining layers, and when acted upon by application of an external source, may be degraded to release the layers from one another. Once released, the layers may be disposed of more efficiently and economically, including proper disposal of hazardous waste, and recycling of materials which may be re-usable.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: May 3, 2016
    Assignee: Empire Technology Development LLC
    Inventors: Sung-Wei Chen, Christopher J. Rothfuss
  • Patent number: 9306087
    Abstract: A method for manufacturing a photovoltaic cell with a locally diffused rear side, comprising steps of: (a) providing a doped silicon substrate, the substrate comprising a front, sunward facing, surface and a rear surface; (b) forming a silicon dioxide layer on the front surface and the rear surface; (c) depositing a boron-containing doping paste on the rear surface in a pattern, the boron-containing paste comprising a boron compound and a solvent; (d) depositing a phosphorus-containing doping paste on the rear surface in a pattern, the phosphorus-containing doping paste comprising a phosphorus compound and a solvent; (e) heating the silicon substrate in an ambient to a first temperature and for a first time period in order to locally diffuse boron and phosphorus into the rear surface of the silicon substrate.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: April 5, 2016
    Assignee: E I DU PONT DE NEMOURS AND COMPANY
    Inventors: Giuseppe Scardera, Maxim Kelman, Elena V Rogojina, Dmitry Poplavskyy, Elizabeth Tai, Gonghou Wang
  • Patent number: 9257583
    Abstract: A solar cell including a substrate 1, a nanopillar 11 having diameter D1 connected to the substrate 1, and a nanopillar 12 having diameter D2 connected to the substrate 1 is characterized in that D2 is greater than D1 in order to realize a solar cell having, as the surface structure, a nanopillar array structure with which it is possible to prevent reflection within the broad wavelength region of solar light. A nanopillar array structure 21 formed from two types of nanopillars having different diameters has a point of minimum reflectivity of a nanopillar array structure formed from the nanopillar 11 having diameter D1 and a point of minimum reflectivity of a nanopillar array structure formed from the nanopillar 12 having diameter D2 and therefore, is capable of preventing reflection within the broad wavelength region of solar light.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: February 9, 2016
    Assignee: HITACHI, LTD.
    Inventors: Keiji Watanabe, Ryuta Tsuchiya, Takashi Hattori, Mieko Matsumura
  • Patent number: 9231014
    Abstract: A back side illumination photodiode includes a light-receiving back side surface of a semiconductor material substrate. An area of the light-receiving back side surface includes a recess. The recess is filled with a material having an optical index that is lower than an optical index of the semiconductor material substrate. Both the substrate and the filling material are transparent to an operating wavelength of the photodiode. The recess may be formed to have a ring shape.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: January 5, 2016
    Assignees: STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Laurent Frey, Michel Marty
  • Patent number: 9231147
    Abstract: Inverted metamorphic multijunction solar cells having a heterojunction middle subcell and a graded interlayer, and methods of making same, are disclosed herein. The present disclosure provides a method of manufacturing a solar cell using an MOCVD process, wherein the graded interlayer is composed of (InxGa1-x)y Al1-yAs, and is formed in the MOCVD reactor so that it is compositionally graded to lattice match the middle second subcell on one side and the lower third subcell on the other side, with the values for x and y computed and the composition of the graded interlayer determined so that as the layer is grown in the MOCVD reactor, the band gap of the graded interlayer remains constant at 1.5 eV throughout the thickness of the graded interlayer.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: January 5, 2016
    Assignee: SolAero Technologies Corp.
    Inventors: Mark A. Stan, Arthur Cornfeld
  • Patent number: 9224881
    Abstract: An imaging device includes a semiconductor substrate having a photosensitive element for accumulating charge in response to incident image light. The semiconductor substrate includes a light-receiving surface positioned to receive the image light. The imaging device also includes a negative charge layer and a charge sinking layer. The negative charge layer is disposed proximate to the light-receiving surface of the semiconductor substrate to induce holes in an accumulation zone in the semiconductor substrate along the light-receiving surface. The charge sinking layer is disposed proximate to the negative charge layer and is configured to conserve or increase an amount of negative charge in the negative charge layer. The negative charge layer is disposed between the semiconductor substrate and the charge sinking layer.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: December 29, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chih-Wei Hsiung, Oray Orkun Cellek, Gang Chen, Duli Mao, Vincent Venezia, Hsin-Chih Tai
  • Patent number: 9218991
    Abstract: There are disclosed herein various implementations of a method and system for ion implantation at high temperature surface equilibrium conditions. The method may include situating a III-Nitride semiconductor body in a surface equilibrium chamber, establishing a gas pressure greater than or approximately equal to a surface equilibrium pressure of the III-Nitride semiconductor body, and heating the III-Nitride semiconductor body to an elevated implantation temperature in the surface equilibrium chamber while substantially maintaining the gas pressure. The method also includes implanting the III-Nitride semiconductor body in the surface equilibrium at the elevated implantation temperature chamber while substantially maintaining the gas pressure, the implanting being performed using an ion implanter interfacing with the surface equilibrium chamber.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: December 22, 2015
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Michael A. Briere
  • Patent number: 9214584
    Abstract: In a method of manufacturing a solar cell includes forming a dopant layer by doping a dopant of a first conductive type and a counter dopant of a second conductive type opposite to the first conductive type to a surface of a semiconductor substrate. Here, a doping amount of the counter dopant is less than a doping amount of the dopant.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: December 15, 2015
    Assignee: LG ELECTRONICS INC.
    Inventors: Youngsung Yang, Yongduk Jin, Manhyo Ha, Juhwa Cheong
  • Patent number: 9209221
    Abstract: An image sensor system has an input from a photosensor, receiving photogenerated electricity, and coupling said photogenerated electricity to a first photodiode to integrate the photogenerated electricity. The photodiode can be a pinned diode, configured to act integrate charge.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: December 8, 2015
    Assignee: Forza Silicon Corporation
    Inventor: Guang Yang