Making Device Or Circuit Responsive To Nonelectrical Signal Patents (Class 438/48)
  • Patent number: 10697994
    Abstract: Techniques for compensating package stress of a proof mass are provided. In an example, a proof mass can be suspended from a substrate by a proof mass anchor. The first proof mass can have a major surface that defines a first plane. Portions of electrodes forming part of the proof mass can be symmetric with each other across a first line, wherein the first line bisects the first proof mass anchor, extends parallel to the first plane and extends between the first electrode and the second electrode.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: June 30, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Cenk Acar, Brenton Ross Simon, Sandipan Maity
  • Patent number: 10700660
    Abstract: A bulk acoustic wave (BAW) resonator includes: a substrate; an acoustic reflector disposed in the substrate; a first electrode disposed over the acoustic reflector; a second electrode; and a piezoelectric layer between the first and second electrodes. The second electrode is not disposed between the first electrode and the acoustic reflector. The BAW resonator further includes a block disposed over the substrate and beneath the piezoelectric layer. A contacting overlap of the acoustic reflector, the first electrode, the second electrode and the piezoelectric layer defines an active area of the BAW resonator.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: June 30, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: John Choy, Chris Feng, Phil Nikkel
  • Patent number: 10692753
    Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark D. Jaffe, Alvin J. Joseph, Qizhi Liu, Anthony K. Stamper
  • Patent number: 10634696
    Abstract: A multi-axis accelerometer may include a proof mass, a first electrode set, and a second electrode set. The first electrode set may detect acceleration along a second axis of the accelerometer, and may include a first electrode (C1) and a second electrode (C2). The second electrode set may detect acceleration along a first axis of the accelerometer that is orthogonal to the second axis, and may include a third electrode (C3) and a fourth electrode (C4). Application of a force along only the second axis may result in the exhibition of a non-zero change in differential capacitance between at least C1 and C2, but a zero net change in the differential capacitance between at least C3 and C4. As such, the accelerometer may exhibit little or no cross axis sensitivity in response to the applied force.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: April 28, 2020
    Assignee: Khalifa University of Science and Technology
    Inventors: Zakriya Mohammed, Waqas Amin Gill, Mahmoud Rasras
  • Patent number: 10566528
    Abstract: A radio frequency (RF) switch includes a heating element, a phase-change material (PCM) situated over the heating element, and PCM contacts situated over passive segments of the PCM. The heating element extends transverse to the PCM. The heating element can have a heater line underlying an active segment of the PCM. Alternatively, the heating element can have a split heater lines underlying an active segment of the PCM. The split heater lines increase an area of the active segment of the PCM and reduce a heater-to-PCM parasitic capacitance. A fan-out structure having fan-out metal can connect the heater line to a heater contact. The fan-out structure reduces heat generation outside the active segment of the PCM and reduces a heater contact-to-PCM parasitic capacitance. The fan-out structure can have dielectric segments interspersed between the fan-out metal to reduce dishing.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: February 18, 2020
    Assignee: Newport Fab, LLC
    Inventors: Nabil El-Hinnawy, Gregory P. Slovin, Michael J. DeBar, Jefferson E. Rose, David J. Howard
  • Patent number: 10566224
    Abstract: Methods, systems and devices for protecting partially processed electronic parts, are disclosed. In some embodiments, a method for protecting electronic parts includes applying a first protective sheet on one or more partially-processed semiconductor devices, removing the first protective sheet, and performing a semiconductor-processing operation on the one or more partially-processed semiconductor devices. In some embodiments, a semiconductor processing system for protecting electronic parts includes one or more partially-processed semiconductor devices, and a first protective sheet applied on the one or more partially-processed semiconductor devices, the first protective sheet being subsequently removed, and a semiconductor-processing operation being performed on the one or more partially-processed semiconductor devices.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: February 18, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventor: John D Steeves
  • Patent number: 10556792
    Abstract: The present disclosure relates to a micro-electro mechanical system (MEMS) package and a method of achieving differential pressure adjustment in multiple MEMS cavities at a wafer-to-wafer bonding level. A device substrate comprising first and second MEMS devices is bonded to a capping substrate comprising first and second recessed regions. A ventilation trench is laterally spaced apart from the recessed regions and within the second cavity. A sealing structure is arranged within the ventilation trench and defines a vent in fluid communication with the second cavity. A cap is arranged within the vent to seal the second cavity at a second gas pressure that is different than a first gas pressure of the first cavity.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: February 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Chia Lee, Chin-Min Lin, Cheng San Chou, Hsiang-Fu Chen, Wen-Chuan Tai, Ching-Kai Shen, Hua-Shu Ivan Wu, Fan Hu
  • Patent number: 10508051
    Abstract: There are provided a lens forming mold, and a manufacturing method for a cylindrical lens, with which cylindrical lenses having good mass productivity can be manufactured. A lens forming mold for forming a molding on which a plurality of cylindrical surfaces are arranged in parallel includes: a first mold including a plurality of cylindrical surface forming portions that are arranged in parallel at equal intervals; and a first flat surface forming portion that is provided between adjacent cylindrical surface forming portions; and a second mold that sandwiches the glass material and faces the first mold when the molding is molded, in which the second mold includes a second flat surface forming portion that faces the plurality of cylindrical surface forming portions and the first flat surface forming portion.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: December 17, 2019
    Assignee: FANUC CORPORATION
    Inventor: Risa Ito
  • Patent number: 10510662
    Abstract: One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh, Hui Zang
  • Patent number: 10446697
    Abstract: A bifacial solar cell includes a substrate of an n-type; an emitter layer positioned on a first surface of the substrate; a plurality of first electrodes locally positioned on the emitter layer and electrically connected to the emitter layer; a first passivation layer positioned on the emitter layer; a silicon oxide layer formed at an interface between the first passivation layer and the emitter layer, the silicon oxide layer having a thickness of about 1 nm to 3 nm; a first anti-reflection layer positioned on the first passivation layer; a plurality of back surface field layers locally positioned on a second surface of the substrate; a plurality of second electrodes respectively positioned on the plurality of back surface field layers and electrically connected to the plurality of back surface field layers; and a second passivation layer positioned on the second surface of the substrate.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: October 15, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Changseo Park, Yoonsil Jin, Youngho Choe
  • Patent number: 10431624
    Abstract: A method of manufacturing an image sensor includes: preparing a sensor substrate including: a sensor layer including a photosensitive cell; and a signal line layer including lines to receive electric signals from the photosensitive cell; forming a first material layer having a first refractive index on the sensor substrate; and forming a nanopattern layer on the first material layer, the nanopattern layer including a material having a second refractive index different from the first refractive index.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: October 1, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Seunghoon Han, Yongsung Kim, Seyedeh Mahsa Kamali, Amir Arbabi, Yu Horie, Andrei Faraon, Sungwoo Hwang
  • Patent number: 10418111
    Abstract: There are provided a memory system and an operating method thereof. A memory system includes: a memory device including a plurality of memory blocks, the memory device configured to perform a read operation on a selected memory block among the plurality of memory blocks; and a memory controller for controlling the memory device to perform the read operation, wherein an Initial turn-on period of the read operation is controlled based on information on an erase number of source line sharing blocks of the selected memory block.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventor: Chi Wook An
  • Patent number: 10374114
    Abstract: The lateral single-photon avalanche diode comprises a semiconductor body comprising a semiconductor material of a first type of electric conductivity, a trench in the semiconductor body, and anode and cathode terminals. A junction region of the first type of electric conductivity is located near the sidewall of the trench, and the electric conductivity is higher in the junction region than at a farther distance from the sidewall. A semiconductor layer of an opposite second type of electric conductivity is arranged at the sidewall of the trench adjacent to the junction region. The anode and cathode terminals are electrically connected with the semiconductor layer and with the junction region, respectively. The junction region may be formed by a sidewall implantation.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: August 6, 2019
    Assignee: ams AG
    Inventors: Jordi Teva, Frederic Roger, Ewald Stueckler, Stefan Jessenig, Rainer Minixhofer, Ewald Wachmann, Martin Schrems, Guenther Koppitsch
  • Patent number: 10338429
    Abstract: The present invention provides a method for manufacturing a quantum dot color filter, which uses a printing mold to pick up quantum dots and printing the quantum dots into a partially cured photoresist layer and then separates the quantum dots and the printing mold, followed by irradiation of UV light to completely cure the photoresist layer so that the quantum dots may uniformly distributed in the photoresist layer. This simplifies the process of transferring a quantum dot layer and reduces cost; requires no process of forming a sacrifice layer and no step of dissolving the sacrifice layer to prevent damage to the quantum dot layer; allows the quantum dots to be uniformly distributed in the photoresist layer to thereby improve the utilization of the quantum dots; and allows a quantum dot color filter so manufactured to be used with white backlighting or blue backlighting for achieving displaying of three primary colors of red, green, and blue.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: July 2, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Hongquan Wei
  • Patent number: 10310695
    Abstract: A sensor having a set of plates that are in contact from their bottom at the corners with a set of protrusions that are in contact from above with a plurality of intersections, each having a sensing element, of a grid of wires disposed on a base, and a top surface layer that is disposed atop the set of plates, so that force imparted from above onto the top surface layer is transmitted to the plates and then to the protrusions, and then to the intersections of the grid of wires which are thereby compressed between the base and protrusions; and that the protrusions above thereby focus the imparted force directly onto the intersections. A sensor includes a computer in communication with the grid which causes prompting signals to be sent to the grid and reconstructs a continuous position of force on the surface from interpolation based on data signals received from the grid. A method for sensing.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 4, 2019
    Assignees: Tactonic Technologies, LLC, New York University
    Inventors: Kenneth Perlin, Charles Hendee, Alex Grau, Gerald Seidman
  • Patent number: 10306372
    Abstract: The present invention provides a method for manufacturing a fully wafer-level-packaged MEMS microphone and a microphone manufactured with the same, the method comprises: separately manufacturing a first packaging wafer, an MEMS microphone wafer and a second packaging wafer; performing wafer-to-wafer bonding for the three wafers to form a plurality of fully wafer-level-packaged MEMS microphone units; singulating the fully wafer-level-packaged MEMS microphone units to form a plurality of fully wafer-level-packaged MEMS microphones, which are fully packaged at wafer level and do not need any further process after die singulation. The method can improve cost-effectiveness, performance consistency, manufacturability, quality, scaling capability of the packaged MEMS microphone.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: May 28, 2019
    Assignee: GOERTEK INC.
    Inventors: Quanbo Zou, Zhe Wang
  • Patent number: 10290670
    Abstract: A resonant-filter image sensor includes a pixel array including a plurality of pixels and a microresonator layer above the pixel array. The microresonator layer includes a plurality of microresonators formed of a first material with an extinction coefficient less than 0.02 at a free-space wavelength of five hundred nanometers. Each of the plurality of pixels may have at least one of the plurality of microresonators at least partially thereabove. The resonant-filter image sensor may further include a layer covering the microresonator layer that has a second refractive index less than a first refractive index, the first refractive index being the refractive index of the first material. Each microresonator may be one of a parallelepiped, a cylinder, a spheroid, and a sphere.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 14, 2019
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yuanwei Zheng, Gang Chen, Duli Mao, Dyson H. Tai, Lequn Liu
  • Patent number: 10274450
    Abstract: A capacitive environmental sensor and a method for determining the presence of a target substance (e.g. water) using differential capacitive measurements. The sensor includes a semiconductor substrate having a surface. The sensor also includes a plurality of sensor electrodes located on the surface. The electrodes are laterally separated on the surface by intervening spaces. The sensor further includes a sensor layer covering the electrodes. The sensor layer has a permittivity that is sensitive to the presence of the target substance. The surface of the substrate, in a space separating at least one pair of electrodes, includes a recess. The surface of the substrate, in a space separating at least one pair of electrodes, does not include a recess. The sensor may be provided in a Radio Frequency Identification (RFID) tag. The sensor may be provided in a smart building.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: April 30, 2019
    Assignee: ams International AG
    Inventors: Hilco Suy, Zoran Zivkovic, Franciscus Petrus Widdershoven, Nebojsa Nenadovic
  • Patent number: 10257933
    Abstract: An electronic device including a transverse circuit board to route electrical traces is provided. In some embodiments, the electronic device includes: a housing; a first printed circuit board (PCB) that is fixed relative to the device housing; an integrated circuit that is connected to the first PCB; a second PCB that is situated in a transverse position relative to the first PCB, a plurality of electrical traces; and a securing component that secures the second PCB in the transverse position relative to the first PCB. Each respective electrical trace from the plurality of electrical traces includes: (i) a first portion that extends across the first PCB, between the integrated circuit and the second PCB, (ii) a second portion that extends across the second PCB, between the first PCB and either the first PCB or a third PCB, and (iii) a third portion that extends across either the first PCB or the third PCB, between the second PCB and a location other than the integrated circuit.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: April 9, 2019
    Assignee: Google LLC
    Inventors: Brian Jon Hassemer, Mark Daniel Janninck, David Kyungtag Lim
  • Patent number: 10211087
    Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark D. Jaffe, Alvin J. Joseph, Qizhi Liu, Anthony K. Stamper
  • Patent number: 10160633
    Abstract: A device includes a carrier having a plurality of cavities, a micro-electro-mechanical system (MEMS) substrate bonded on the carrier, wherein the MEMS substrate comprises a first side bonded on the carrier, a moving element over a bottom electrode, wherein the bottom electrode is formed of polysilicon and a second side having a plurality of bonding pads and a semiconductor substrate bonded on the MEMS substrate, wherein the semiconductor substrate comprises a top electrode and the first moving element is between the top electrode and the bottom electrode.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng, Te-Hao Lee, Chung-Hsien Lin
  • Patent number: 10157941
    Abstract: An image sensor and a fabrication method thereof are provided. In the fabrication method of the image sensor, at first, two isolation features are formed in a substrate to define a pixel region. Then, a floating node and a pinning layer are formed in one of the isolation features, in which a space region is located between the floating node and the pinning layer, and the floating node has a first conductivity type different from a second conductivity type of the pinning layer. Thereafter, a light-sensitive element is formed in the pixel region, and a transfer gate is formed on the pixel region, thereby forming a pixel. Since there is a space region located between the floating node and the pinning layer, a leakage path between the floating node and the pinning layer can be prevented.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Pin Cheng, Fu-Cheng Chang, Ching-Hung Kao, Che-Chun Lu
  • Patent number: 10093533
    Abstract: A sensor chip includes a first substrate with a first surface and a second surface including at least one CMOS circuit, a first MEMS substrate with a first surface and a second surface on opposing sides of the first MEMS substrate, a second substrate, a second MEMS substrate, and a third substrate including at least one CMOS circuit. The first surface of the first substrate is attached to a packaging substrate and the second surface of the first substrate is attached to the first surface of the first MEMS substrate. The second surface of the first MEMS substrate is attached to the second substrate. The first substrate, the first MEMS substrate, the second substrate and the packaging substrate are provided with electrical inter-connects.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: October 9, 2018
    Assignee: InvenSense, Inc.
    Inventors: Peter Smeys, Martin Lim
  • Patent number: 10019124
    Abstract: A touch window includes a substrate, a sensing electrode on the substrate, and a dummy electrode in the sensing electrode. The dummy electrode includes first to third dummy electrodes spaced apart from each other.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 10, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Gwan Youl Jung
  • Patent number: 10017375
    Abstract: A method is provided for manufacturing a micromechanical component including a substrate and a cap connected to the substrate and together with the substrate enclosing a first cavity, a first pressure prevailing and a first gas mixture with a first chemical composition being enclosed in the first cavity. An access opening, connecting the first cavity to surroundings of the micromechanical component, is formed in the substrate or in the cap. The first pressure and/or the first chemical composition are adjusted in the first cavity. The access opening is sealed by introducing energy and heat into an absorbing part of the substrate or the cap with the aid of a laser. A recess is formed in a surface of the substrate or of the cap facing away from the first cavity in the area of the access opening for reducing local stresses occurring at a sealed access opening.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 10, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventors: Frank Reichenbach, Till Schade, Jochen Reinmuth, Philip Kappe, Alexander Ilin, Mawuli Ametowobla, Julia Amthor
  • Patent number: 10005662
    Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: June 26, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee Alan Stringer, Mona Eissa, Byron J. R. Shulver, Sopa Chevacharoenkul, Mark R. Kimmich, Sudtida Lavangkul, Mark L. Jenson
  • Patent number: 9991301
    Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: June 5, 2018
    Assignee: Sony Corporation
    Inventors: Atsushi Yamamoto, Shinji Miyazawa, Yutaka Ooka, Kensaku Maeda, Yusuke Moriya, Naoki Ogawa, Nobutoshi Fujii, Shunsuke Furuse, Masaya Nagata, Yuichi Yamamoto
  • Patent number: 9972808
    Abstract: There is provided a display device including an element substrate that has a display area; and a counter substrate. When it is assumed that the length of the shortest edge of the display area is X1, the length of a longest diagonal line of the display area is X3, the thickness of the counter substrate is L1, the refraction index of the counter substrate is n1, the refractive index of the air is n2, and the minimum value of an angle, which is generated between a progress direction of light emitted from the organic EL elements and a normal vector direction is totally reflected in the surface, is ?, the relationship of X1/(2 tan ?)?L1?X3/(tan ?) is realized.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: May 15, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Koya Shiratori, Takeshi Koshihara
  • Patent number: 9954137
    Abstract: Photodetector structures and methods of manufacture are provided. The method includes forming undercuts about detector material formed on a substrate. The method further includes encapsulating the detector to form airgaps from the undercuts. The method further includes annealing the detector material causing expansion of the detector material into the airgaps.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: April 24, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Ellis-Monaghan, John C. S. Hall, Marwan H. Khater, Edward W. Kiewra, Steven M. Shank
  • Patent number: 9914637
    Abstract: According to one embodiment, an electronic device includes a base region, an element portion located on the base region, the element portion including a movable portion, and a protective film overlying the element portion and forming a cavity on an inner side of the protective film. The protective film includes a first protective layer and a second protective layer located on the first protective layer. A hole extends in a direction parallel to a main surface of the base region, and the second protective layer covers the hole.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 13, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Fujimoto, Naofumi Nakamura, Tamio Ikehashi
  • Patent number: 9854189
    Abstract: An imaging element includes a photoelectric conversion section and a wiring layer. The photoelectric conversion section is configured to photoelectrically convert light incident from a subject. The wiring layer is provided on an opposite side of the subject with respect to the photoelectric conversion section and includes a wire connected to an element that constitutes a pixel including the photoelectric conversion section. The wire includes a plurality of wires extending long in a predetermined direction. The plurality of wires are arranged in a direction almost perpendicular to the predetermined direction in the wiring layer. The wire is provided with a protrusion protruding in a direction different from the predetermined direction.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: December 26, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hideo Kido
  • Patent number: 9824882
    Abstract: A method for manufacturing a protective layer for protecting an intermediate structural layer against etching with hydrofluoric acid, the intermediate structural layer being made of a material that can be etched or damaged by hydrofluoric acid, the method comprising the steps of: forming a first layer of aluminum oxide, by atomic layer deposition, on the intermediate structural layer; performing a thermal crystallization process on the first layer of aluminum oxide to form a first intermediate protective layer; forming a second layer of aluminum oxide, by atomic layer deposition, above the first intermediate protective layer; and performing a thermal crystallization process on the second layer of aluminum oxide to form a second intermediate protective layer and thereby completing the formation of the protective layer. The method for forming the protective layer can be used, for example, during the manufacturing steps of an inertial sensor such as a gyroscope or an accelerometer.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: November 21, 2017
    Assignee: STMicroelectronics S.r.l.
    Inventors: Stefano Losa, Raffaella Pezzuto, Roberto Campedelli, Matteo Perletti, Luigi Esposito, Mikel Azpeitia Urquia
  • Patent number: 9815687
    Abstract: A micromechanical structure of a MEMS device, integrated in a die of semiconductor material provided with a substrate and having at least a first axis of symmetry lying in a horizontal plane, has a stator structure, which is fixed with respect to the substrate, and a rotor structure, having a suspended mass, mobile with respect to the substrate and to the stator structure as a result of an external action, the stator structure having fixed sensing electrodes capacitively coupled to the rotor structure; a compensation structure is integrated in the die for compensation of thermo-mechanical strains. The compensation structure has stator compensation electrodes, which are fixed with respect to the substrate, are capacitively coupled to the rotor structure, and are arranged symmetrically to the fixed sensing electrodes with respect to the first axis of symmetry.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 14, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Angelo Antonio Merassi
  • Patent number: 9796580
    Abstract: A sensor chip combining a substrate comprising at least one CMOS circuit, a MEMS substrate and another substrate comprising at least one CMOS circuit in one package that is vertically stacked is disclosed. The package comprises a sensor chip further comprising a first substrate with a first surface and a second surface comprising at least one CMOS circuit; a MEMS substrate with a first surface and a second surface; and a second substrate comprising at least one CMOS circuit. Where the first surface of the first substrate is attached to a packaging substrate and the second surface of the first substrate is attached to the first surface of the MEMS substrate. The second surface of the MEMS substrate is attached to the second substrate. The first substrate, the MEMS substrate, the second substrate and the packaging substrate are mechanically attached and provided with electrical inter-connects.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: October 24, 2017
    Assignee: InvenSense, Inc.
    Inventors: Peter Smeys, Martin Lim
  • Patent number: 9786707
    Abstract: Image sensors comprising an isolation region according to embodiments are disclosed, as well as methods of forming the image sensors with isolation region. An embodiment is a structure comprising a semiconductor substrate, a photo element in the semiconductor substrate, and an isolation region in the semiconductor substrate. The isolation region is proximate the photo element and comprises a dielectric material and an epitaxial region. The epitaxial region is disposed between the semiconductor substrate and the dielectric material.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Min Hao Hong, Kei-Wei Chen, Szu-An Wu
  • Patent number: 9783409
    Abstract: This invention provides a MEMS device, including: a mass structure having at least one anchor; at least one flexible structure connected with the mass structure at the at least one anchor; a plurality of top electrodes located above the mass structure and forming a top capacitor circuit with the mass structure; and a plurality of bottom electrodes located under the mass structure and forming a bottom capacitor circuit with the mass structure. The projections of the plural top electrodes on the mass structure along a normal direction of the mass structure are located at opposite sides of the anchor, and the projections of the plural bottom electrodes on the mass structure along a normal direction of the mass structure are located at opposite sides of the anchor. This invention also provides a MEMS compensation structure.
    Type: Grant
    Filed: September 28, 2014
    Date of Patent: October 10, 2017
    Assignee: PIXART IMAGING INCORPORATION
    Inventors: Ming-Han Tsai, Chih-Ming Sun, Hsin-Hui Hsu
  • Patent number: 9676607
    Abstract: Micromechanical devices include actively deflectable elements. The activation is performed by a layer stack which causes the deflection responsive to attractive forces acting upon the layers of the layer stack.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: June 13, 2017
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Matthieu Gaudet, Klaus Schimmanz, Michael Stolz, Sergiu Langa, Holger Conrad, Bert Kaiser
  • Patent number: 9666475
    Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark D. Jaffe, Alvin J. Joseph, Qizhi Liu, Anthony K. Stamper
  • Patent number: 9653506
    Abstract: An image sensor includes a substrate including a photoelectric conversion region, an interlayer insulation layer including an interconnection line and formed on the substrate, a condensing pattern having a first refractive index and including a first region upwardly protruding from the interlayer insulation layer and a second region buried in the interlayer insulation layer, and a color filter formed on the condensing pattern to bury the condensing pattern.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: May 16, 2017
    Assignee: SK Hynix Inc.
    Inventor: Sang-Sik Kim
  • Patent number: 9638717
    Abstract: The present invention generally relates to nanoscale wires for use in sensors and other applications. In various embodiments, a probe comprising a nanotube (or other nanoscale wire) is provided that can be directly inserted into a cell to determine a property of the cell, e.g., an electrical property. In some cases, only the tip of the nanoscale wire is inserted into the cell; this tip may be very small relative to the cell, allowing for very precise study. In some aspects, the tip of the probe is held by a holding member positioned on a substrate, e.g., at an angle, which makes it easier for the probe to be inserted into the cell. The nanoscale wire may also be connected to electrodes and/or form part of a transistor, such that a property of the nanoscale wire, and thus of the cell, may be determined. Such probes may also be useful for studying other samples besides cells.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: May 2, 2017
    Assignee: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Ruixuan Gao, Steffen Strehle, Xiaojie Duan, Bozhi Tian, Itzhaq Cohen-Karni, Ping Xie, Quan Qing
  • Patent number: 9642231
    Abstract: A fingerprint sensor is provided. The fingerprint sensor includes a sensing array sensing fingerprint information of a user, an insulating surface disposed on the sensing array, and a printed circuit board (PCB) disposed under the sensing array. The PCB includes a substrate, a ground plane disposed on the second surface of the substrate, and an electrostatic discharge (ESD) ring disposed on the first surface of the substrate and surrounding the sensing array. The substrate includes a first surface and a second surface opposite the first surface. The ESD ring surrounds the sensing array. When an ESD event occurs, ESD energy is discharged from the ESD ring to the ground plane through a plurality of vias in the substrate without passing the sensing array.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: May 2, 2017
    Assignee: Egis Technology Inc.
    Inventor: Cheng-Chung Wang
  • Patent number: 9641939
    Abstract: An acoustic transducer includes a slit having higher passage resistance than in conventional structures and having a lower rate of decrease in the passage resistance than in conventional structures when, for example, the vibration electrode plate warps. The acoustic transducer includes a stationary electrode plate, and a vibration electrode plate facing the stationary electrode plate with a space between the electrode plates. The vibration electrode plate includes a slit that allows sound to pass through. The vibration electrode plate includes a resistance increasing section including at least one pair of high-resistance surfaces that constitute side surfaces of the slit in a width direction thereof, and are thicker than a middle portion of the vibration electrode plate.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: May 2, 2017
    Assignee: OMRON Corporation
    Inventors: Yuki Uchida, Koji Momotani, Takashi Kasai
  • Patent number: 9634153
    Abstract: The present invention relates to a sensor that uses a sensing mechanism having a combined static charge and a field effect transistor, the sensor including: a substrate; source and drain units formed on the substrate and separated from each other; a channel unit interposed between the source and drain units; a membrane separated from the channel unit, disposed on a top portion and displaced in response to an external signal; and a static charge member formed on a bottom surface of the membrane separately from the channel unit and generating an electric field.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: April 25, 2017
    Assignee: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Won Kyu Moon, James Edward West, Min Sung, Yub Je, Kum Jae Shin
  • Patent number: 9621125
    Abstract: A first variable capacitance section included in a variable capacitance circuit includes a plurality of first variable capacitance elements connected to a signal line and each having a first capacitance value or a second capacitance value greater than the first capacitance value according to driving voltage, and includes a first fixed capacitance element connected in series with the plurality of first variable capacitance elements. A second variable capacitance section included in the variable capacitance circuit includes a second variable capacitance element connected to the signal line and having the first capacitance value or the second capacitance value according to the driving voltage, and includes a second fixed capacitance element connected in series with the second variable capacitance element.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: April 11, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Takeaki Shimanouchi
  • Patent number: 9608133
    Abstract: A solar cell includes a substrate of a first conductive type, an emitter layer, of a second conductive type opposite the first conductive type, positioned at one surface of the substrate, a first electrode electrically connected to the emitter layer, a first protective layer positioned on a front surface of the emitter layer where the first electrode is not positioned, a back surface field layer positioned at another surface of the substrate, a second electrode electrically connected to the back surface field layer, and a second protective layer positioned on a back surface of the substrate where the second electrode is not positioned. Each of the first and second protective layers is formed of a material having fixed charges of the first conductive type.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: March 28, 2017
    Assignee: LG ELECTRONICS INC.
    Inventors: Changseo Park, Yoonsíl Jin, Youngho Choe
  • Patent number: 9559211
    Abstract: A method for manufacturing a semiconductor device, which enables miniaturization and reduction of defect, is provided. It includes forming an oxide semiconductor layer, and source and drain electrodes in contact with the oxide semiconductor layer, over an insulating surface; forming insulating layers over the source electrode and the drain electrode; forming a gate insulating layer over the oxide semiconductor layer, the source and drain electrodes, and the insulating layer; forming a conductive layer over the gate insulating layer; forming an insulating film covering the conductive layer; processing the insulating film so that at least part of a region of the conductive layer, which overlaps with the source electrode or the drain electrode, is exposed; and etching the exposed region of the conductive layer to form a gate electrode overlapping with at least part of the region sandwiched between the source electrode and the drain electrode, in a self-aligned manner.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: January 31, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9550666
    Abstract: The present disclosure provides a micro-electro-mechanical systems (MEMS) device. In an embodiment, a device includes a substrate; a MEMS structure disposed above a sacrificial layer opening above the substrate; a release aperture disposed at substantially a same level above the sacrificial layer opening as the MEMS structure; a first cap over the MEMS structure and the sacrificial layer opening, a leg of the first cap disposed between the MEMS structure and the release aperture; and a second cap plugging the release aperture.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hsien Lin, Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 9524020
    Abstract: A sensor having a set of grid of bars that are in contact from their bottom at the corners with a set of protrusions that are in contact from above with a plurality of intersections, each having a sensing element, of a grid of wires disposed on a base, and a top surface layer that is disposed atop the grid of bars, so that force imparted from above onto the top surface layer is transmitted to the grid of bars and thence to the protrusions, and thence to the intersections of the grid of wires which are thereby compressed between the base and protrusions; and that the protrusions above thereby focus the imparted force directly onto the intersections. A sensor includes a computer in communication with the grid of wires which causes prompting signals to be sent to the grid of wires and reconstructs a continuous position of force on the surface from interpolation based on data signals received from the grid of wires. A method for sensing.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: December 20, 2016
    Assignees: New York University, Tactonic Technologies, LLC
    Inventors: Kenneth Perlin, Charles Hendee, Alex Grau, Gerald Seidman
  • Patent number: 9518877
    Abstract: A micromechanical component for a capacitive sensor device includes first and second electrodes. The first electrode is at least partially formed from a first semiconductor layer and/or metal layer, and at least one inner side of the second electrode facing the first electrode is formed from a second semiconductor layer and/or metal layer. A cavity is between the first and second electrodes. Continuous recesses are structured into the inner side of the second electrode and sealed off with a closure layer. At least one reinforcing layer of the second electrode and at least one contact element which is electrically connected to the first electrode, to the layer of the second electrode which forms the inner side, to at least one printed conductor, and/or to a conductive substrate area, are formed from at least one epi-polysilicon layer. Also described is a micromechanical component manufacturing method for a capacitive sensor device.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: December 13, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventor: Heribert Weber
  • Patent number: 9502995
    Abstract: A micro-hydraulic device includes an enclosure. The enclosure includes a substrate having a first surface and a second surface distal to the first surface. The enclosure further includes a chamber defined between the first surface and the second surface. The chamber is defined by a wall substantially from the first surface to the second surface. The enclosure includes a first flexible membrane sealingly connected to the first surface and disposed over the chamber; and a second flexible membrane sealingly connected to the second surface disposed over the chamber distal to the first flexible membrane. The device further includes an internal fluid retained within the enclosure and a rigid electrode fixed within the chamber having an aperture therein. A flexible electrode is disposed on the second flexible membrane opposite the rigid electrode.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: November 22, 2016
    Assignee: The Regents of the University of Michigan
    Inventors: Khalil Najafi, Mahdi Sadeghi, Rebecca L. Peterson