Making Device Or Circuit Responsive To Nonelectrical Signal Patents (Class 438/48)
  • Patent number: 11496226
    Abstract: In an acoustic wave device, an antenna end resonator that is electrically closest to a first terminal is a first acoustic wave resonator. In each of the first acoustic wave resonator and a second acoustic wave resonator, a thickness of a piezoelectric layer is about 3.5? or less when a wavelength of an acoustic wave is denoted as ?. The first acoustic wave resonator and the second acoustic wave resonator satisfy at least one of a first condition, a second condition, and a third condition. The first condition is a condition that the first acoustic wave resonator further includes a dielectric film provided between the piezoelectric layer and an interdigital transducer electrode, and the second acoustic wave resonator does not include the dielectric film.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: November 8, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Ryo Nakagawa, Hideki Iwamoto, Tsutomu Takai
  • Patent number: 11462500
    Abstract: In one embodiment, an optoelectronic semiconductor device includes at least two lead frame parts and an optoelectronic semiconductor chip which is mounted in a mounting region on one of the lead frame parts. The lead frame parts are mechanically connected to one another via a casting body. The semiconductor chip is embedded in the cast body. In the mounting region the respective lead frame part has a reduced thickness. An electrical line is led over the cast body from the semiconductor chip to a connection region of the other of the lead frame parts. In the connection region, the respective lead frame part has the full thickness. From the connection region to the semiconductor chip the electrical line does not overcome any significant difference in height.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: October 4, 2022
    Assignee: OSRAM OLED GMBH
    Inventors: Matthias Hien, Matthias Goldbach, Michael Zitzlsperger, Ludwig Peyker
  • Patent number: 11425821
    Abstract: A printed circuit board (PCB) includes a plurality of layers disposed at different depths of the PCB, circuit components disposed at different layers of the PCB, and a plurality of temperature measurement sensors located at one or more layers of the PCB, where each temperature measurement sensor is associated with a corresponding circuit component. A measured temperature is obtained at an embedded temperature measurement sensor located at an embedded layer within the PCB, and the measured temperature is correlated with an electrical property of an embedded circuit component located at the same embedded layer within the PCB as the embedded temperature measurement sensor. A plurality of moisture measurement sensors can also be located at one or more layers of the PCB to facilitate a measured moisture with an electrical property of an embedded circuit component.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 23, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Amendra Koul, Mike Sapozhnikov, David Nozadze, Joel Goergen
  • Patent number: 11406298
    Abstract: Disclosed are systems and methods for detecting analyte levels. These systems and methods may include a sensor configured for at least partial placement in an analyte-containing medium. The sensor may include one or more transducers and one or more diffusion barriers. The diffusion barriers may be arranged to delay diffusion of analyte to one transducer relative to another transducer. This delay may be used for purposes such as calculating and/or compensating for lag between a measured analyte level and a physiological analyte level of interest.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: August 9, 2022
    Assignee: Senseonics, Incorporated
    Inventors: James Masciotti, Abhi Chavan, Andrew Dehennis
  • Patent number: 11397863
    Abstract: The present disclosure concerns a magnetic reader (MR) sensor device for reading magnetic stripes, the MR sensor device comprising a substrate provided on a wafer, a back-end-of-line (BEOL) interconnect layer and a plurality of magneto-resistive sensor elements embedded within the BEOL interconnect layer; the MR sensor device comprising a protective layer having a Vickers hardness of at least 3 GPa. The present disclosure further concerns a method for manufacturing the MR sensor device. The MR sensor device can be brought close to the surface to the magnetic stripe so that the magnetic stripe can be read with an increased resolution.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: July 26, 2022
    Assignee: CROCUS TECHNOLOGY SA
    Inventors: Ali Alaoui, Jeffrey Childress, Hakan Ates Gurcan
  • Patent number: 11369281
    Abstract: A surgical locator circuit identifies a surgical target such as a kidney stone by disposing an emitter such as a magnetic source behind or adjacent the surgical target, and employing the circuit to identify an axis to the emitter, thus defining an axis or path to the surgical target. An array of sensors arranged in an equidistant, coplanar arrangement each senses a signal indicative of a distance to the emitter. A magneto resistor sensor generates a variable resistance is responsive to the distance to a magnetic coil emitting a magnetic field. An equal signal from each of the coplanar sensors indicates positioning on an axis passing through a point central to the sensors and orthogonal to the plane. A fixed element and signal conditioner augments and normalizes the signal received from each of the sensors to accommodate subtle differences in magneto resistive response among the plurality of sensors.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: June 28, 2022
    Assignee: Gyrus Acmi, Inc.
    Inventor: Tailin Fan
  • Patent number: 11329093
    Abstract: A photoelectric conversion apparatus includes a semiconductor substrate including a photoelectric conversion portion, a metal containing portion provided on the semiconductor substrate, an interlayer insulation film arranged on the semiconductor substrate to cover the metal containing portion, a first silicon nitride layer arranged on the photoelectric conversion portion to include a portion lying between the interlayer insulation film and the semiconductor substrate, a silicon oxide film including a portion arranged between the first silicon nitride layer and the photoelectric conversion portion, and a portion arranged between the interlayer insulation film and the metal containing portion, a second silicon nitride layer arranged between the silicon oxide film and the metal containing portion.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: May 10, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shinji Kodaira, Takehito Okabe, Mitsuhiro Yomori, Nobuyuki Endo, Tomoyuki Tezuka, Toshihiro Shoyama, Jun Iwata
  • Patent number: 11319449
    Abstract: Processes of selectively depositing a metal-containing film comprise: providing a surface having a plurality of materials exposed thereon simultaneously, and exposing the surface to a vapor of a metal-containing film-forming composition that contains a precursor having the formula: LxM(—N(R)—(CR?2)n—NR?2) wherein M is a Group 12, Group 13, Group 14, Group 15, Group IV or Group V element; x+1 is the oxidation state of the M; L is an anionic ligand, independently selected from dialkylamine, alkoxy, alkylimine, bis(trialkylsilylamine), amidinate, betadiketonate, keto-imine, halide, or the like; R, R? each are independently a C1-C10 linear, branched or cyclic alkyl, alkenyl, or trialkylsilyl group; R? is H or a C1-C10 linear, branched or cyclic alkyl, alkenyl or trialkylsilyl group; n=1-4, wherein at least one of the materials is at least partially blocked by a blocking agent from the deposition of the metal-containing film through a vapor deposition process.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 3, 2022
    Assignee: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude
    Inventors: Wontae Noh, Jooho Lee, Jean-Marc Girard
  • Patent number: 11307466
    Abstract: The array substrate of embodiments of the present invention uses the adjustment dielectric layer to reduce parasitic capacitance between the gate metal layer and the electrode layer, thus avoiding the dark streak phenomenon due to the fringing electric field and the surrounding environment and improving display quality.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: April 19, 2022
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Qian Li
  • Patent number: 11301083
    Abstract: A sensor having a set of plates that are in contact from their bottom at the corners with a set of protrusions that are in contact from above with a plurality of intersections, each having a sensing element, of a grid of wires disposed on a base, and a top surface layer that is disposed atop the set of plates, so that force imparted from above onto the top surface layer is transmitted to the plates and thence to the protrusions, and thence to the intersections of the grid of wires which are thereby compressed between the base and protrusions; and that the protrusions above thereby focus the imparted force directly onto the intersections. A sensor includes a computer in communication with the grid which causes prompting signals to be sent to the grid and reconstructs a continuous position of force on the surface from interpolation based on data signals received from the grid. A method for sensing.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: April 12, 2022
    Assignees: New York University, Tactonic Technologies, LLC
    Inventors: Kenneth Perlin, Charles Hendee, Alex Grau, Gerald Seidman
  • Patent number: 11289530
    Abstract: A shallow trench isolation (STI) structure and method of fabrication includes a two-step epitaxial growth process. A trench larger than the target STI structure is etched into a semiconductor substrate, a first layer of un-doped semiconductor material epitaxially grown in the trench to provide an STI structure having a target depth and a critical dimension, and a second layer of doped semiconductor material epitaxially grown on the first layer, said second layer filling the trench and forming a protrusion above the front-side of the semiconductor substrate.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: March 29, 2022
    Assignee: OmniVision Technologies, Inc.
    Inventor: Seong Yeol Mun
  • Patent number: 11245376
    Abstract: A method of wafer scale packaging acoustic resonator devices and an apparatus therefor. The method including providing a partially completed semiconductor substrate comprising a plurality of single crystal acoustic resonator devices provided on a silicon and carbide bearing material, each having a first electrode member, a second electrode member, and an overlying passivation material. At least one of the devices to be configured with an external connection, a repassivation material overlying the passivation material, an under metal material overlying the repassivation material. Copper pillar interconnect structures are then configured overlying the electrode members, and solder bump structures are form overlying the copper pillar interconnect structures.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: February 8, 2022
    Assignee: Akoustis, Inc.
    Inventor: Jeffrey B. Shealy
  • Patent number: 11181868
    Abstract: The present invention relates to a method for manufacturing metal timepiece components, characterised in that it comprises the steps of forming a multi-level photoresist mould, by means of a UV-LIGA type method, and of galvanically depositing a layer of at least one metal starting from at least two conductive layers so as to form a block that substantially reaches the top surface of the photoresist.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: November 23, 2021
    Assignee: Nivarox-FAR S.A.
    Inventors: Clare Golfier, Fatmir Salihu, Pierre Cusin
  • Patent number: 11125949
    Abstract: An optical connecting component configures to be mounted onto an optical component includes a plurality of optical fibers and terminal components disposed at the ends of the plurality of optical fibers. The optical fibers are arranged side by side and integrated together in a state in which the optical fibers can be separated from one another. A method of manufacturing an optical connecting component that includes a plurality of optical fibers and a terminal component disposed at ends of the plurality of optical fibers and that is mounted onto an optical component includes a step of arranging the plurality of optical fibers side by side and integrating the plurality of optical fibers together, a step of connecting end portions of the plurality of optical fibers to the terminal component, and a step of separating the plurality of optical fibers from one another.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: September 21, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Takuya Nanjo
  • Patent number: 11114997
    Abstract: A bulk acoustic wave resonator includes a substrate, a seed layer disposed on the substrate, a first electrode disposed on the seed layer and including an aluminum alloy layer containing scandium (Sc), a piezoelectric layer disposed on the first electrode and including a layer having a cation (Al) polarity, and a second electrode disposed on the piezoelectric layer.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 7, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ran Hee Shin, Tae Kyung Lee, Sung Jun Lee, Hwa Sun Lee, Je Hong Kyoung, Sung Sun Kim, Jin Suk Son
  • Patent number: 11092440
    Abstract: According to one embodiment, a method for controlling a vibration device includes a movable body capable of vibrating in a first direction, and a catch and release mechanism capable of catching the movable body that freely vibrates in the first direction, by an electrostatic attractive force, and releasing the caught movable body to freely vibrate the movable body in the first direction, wherein in a condition that tc is a time from a rise start time point to a rise end time point of an applied voltage for catching the movable body that freely vibrates in the first direction, by the electrostatic attractive force, and td is a period of the free vibration in the first direction of the movable body, the time tc is longer than the time td.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: August 17, 2021
    Assignee: KABUSHIKIKAISHA TOSHIBA
    Inventors: Ryunosuke Gando, Tamio Ikehashi, Etsuji Ogawa, Tetsuro Itakura, Yohei Hatakeyama, Yasushi Tomizawa
  • Patent number: 11092471
    Abstract: The present disclosure resides in a sensor element for determining a physical, measured variable of a measured medium, comprising: a planar substrate; a functional layer applied on a surface of the substrate; a passivating layer applied on the functional layer; a metal connecting layer applied on the surface of the passivating layer such that the passivating layer is completely covered; and a metal platelet applied on the surface of the metal connecting layer such that no contact can occur between the passivating layer and the measured medium, as well as residing in a thermal flow sensor, which has at least two such sensor elements.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 17, 2021
    Assignee: Innovative Sensor Technology IST AG
    Inventors: Florian Krogmann, Patrik Grob, Barb Yannick
  • Patent number: 11086222
    Abstract: A method of manufacturing a semiconductor structure includes providing a substrate and a photoresist over the substrate; placing a mask over the photoresist; exposing the photoresist to a predetermined electromagnetic radiation through the mask; and removing at least a portion of the photoresist exposed to the predetermined electromagnetic radiation. The mask includes a first portion configured to totally allow the predetermined electromagnetic radiation passing through, a second portion configured to partially allow the predetermined electromagnetic radiation passing through, and a third portion configured to block the predetermined electromagnetic radiation, the second portion is disposed between the first portion and the third portion.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: August 10, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Yu-Mei Ni, Shih-Yi Liu
  • Patent number: 11078075
    Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chih-Ming Chen, Yuan-Chih Hsieh, Chung-Yi Yu
  • Patent number: 11022577
    Abstract: Methods for forming an electrode structure, which can be used as a biosensor, are provided in which the electrode structure has non-random topography located on one surface of an electrode base. In some embodiments, an electrode structure is obtained that contains no interface between the non-random topography of the electrode structure and the electrode base of the electrode structure. In other embodiments, electrode structures are obtained that have an interface between the non-random topography of the electrode structure and the electrode base of the electrode structure.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventor: Emily R. Kinser
  • Patent number: 10991612
    Abstract: A wafer has a first side with a device area comprising a plurality of devices, and a second side opposite to the first side, wherein the second side has a plurality of protrusions protruding along a thickness direction of the wafer. The wafer is processed by providing a protective film and a base sheet having a cushioning layer applied to a front surface thereof, and attaching a front surface of the protective film to the second side of the wafer. The protective film is adhered to at least a peripheral portion of the second side with an adhesive, and a back surface of the protective film opposite to the front surface thereof is attached to the cushioning layer. The protrusions are embedded in the cushioning layer and a back surface of the base sheet is substantially parallel to the first side of the wafer.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: April 27, 2021
    Assignee: DISCO CORPORATION
    Inventor: Karl Heinz Priewasser
  • Patent number: 10991581
    Abstract: A method for manufacturing a semiconductor film capable of forming a semiconductor film with high crystalline quality using a solid-state laser is provided. A method for manufacturing a semiconductor film according to the present disclosure includes the steps of (a) irradiating an amorphous semiconductor film with a first pulsed laser beam emitted from a solid-state laser, and then after the step (a), (b) irradiating the semiconductor film with a second pulsed laser beam including intensity lower than that of the first pulsed laser beam.
    Type: Grant
    Filed: February 29, 2020
    Date of Patent: April 27, 2021
    Assignee: THE JAPAN STEEL WORKS, LTD.
    Inventors: Naoyuki Kobayashi, Hiroaki Imamura
  • Patent number: 10985200
    Abstract: A method for producing an image sensor comprises: depositing a first back-end-of-line, BEOL, layer above a substrate comprising an array of light-detecting elements, said BEOL layer comprising metal wirings being arranged to form connections to components on the substrate and together with depositing the first BEOL layer, improving planarization of the first BEOL layer by depositing a planarizing metal dummy pattern in the first BEOL layer, wherein a part of the planarizing metal dummy pattern is arranged above a light-detecting element, wherein the planarizing metal dummy patterns is formed from the same material as the metal wirings and is deposited to planarize density of the metal deposited in the first BEOL layer across a surface of the layer and wherein a shape and/or position of the metal dummy pattern above the array of light-detecting elements is designed to provide a desired effect on incident light.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 20, 2021
    Assignee: IMEC VZW
    Inventors: Veronique Rochus, Xavier Rottenberg
  • Patent number: 10964851
    Abstract: A single light emitting diode (LED) structure includes an array of spaced discrete light emitting zones separated by isolation areas. Each emitting zone includes an epitaxial structure configured to emit an emitting light having a particular wavelength over an effective emission area. In addition, the effective emission area for each emitting zone can be geometrically defined and electrically configured to provide a desired light intensity. For example, each effective emission area can have a selected size and spacing depending on the application and light intensity requirements. Each emitting zone also includes a wavelength conversion member on its effective emission area configured to convert an emitting wavelength of the emitting light to a different color. The single (LED) structure can include multiple colors at different zones to produce a desired spectra or design.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 30, 2021
    Assignee: SemiLEDs Optoelectronics Co., Ltd.
    Inventors: Trung Tri Doan, David Trung Doan
  • Patent number: 10948635
    Abstract: A light direction control film is provided. The light direction control film has, in a direction perpendicular to a thickness direction of the light direction control film, a refractive index decreasing from a central region of the light direction control film to each of both sides of the light direction control film gradually. A method for manufacturing a light direction control film and a fingerprint recognition panel including the light direction control film are further provided.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: March 16, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Jifeng Tan
  • Patent number: 10886444
    Abstract: A wafer-level process for manufacturing solid state lighting (“SSL”) devices using large-diameter preformed metal substrates is disclosed. A light emitting structure is formed on a growth substrate, and a preformed metal substrate is bonded to the light emitting structure opposite the growth substrate. The preformed metal substrate can be bonded to the light emitting structure via a metal-metal bond, such as a copper-copper bond, or with an inter-metallic compound bond.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Vladimir Odnoblyudov
  • Patent number: 10876997
    Abstract: A bioFET device includes a semiconductor substrate having a first surface and an opposite, parallel second surface and a plurality of bioFET sensors on the semiconductor substrate. Each of the bioFET sensors includes a gate formed on the first surface of the semiconductor substrate and a channel region formed within the semiconductor substrate beneath the gate and between source/drain (S/D) regions in the semiconductor substrate. The channel region includes a portion of the second surface of the semiconductor substrate. An isolation layer is disposed on the second surface of the semiconductor substrate. The isolation layer has an opening positioned over the channel region of more than one bioFET sensor of the plurality of bioFET sensors. An interface layer is disposed on the channel region of the more than one bioFET sensor in the opening.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 29, 2020
    Inventors: Jui-Cheng Huang, Yi-Hsien Chang, Chin-Hua Wen, Chun-Ren Cheng, Shih-Fen Huang, Tung-Tsun Chen, Yu-Jie Huang, Ching-Hui Lin, Sean Cheng, Hector Chang
  • Patent number: 10843919
    Abstract: A MEMS apparatus with heater includes central part, periphery part, gap and first connecting part. Central part includes center of mass, heater and first joint. Heater is disposed inside central part. First joint is located on boundary of central part. Displacement of first joint is produced when central part is heated by heater. Periphery part surrounds central part. Gap surrounds central part, and is located between central part and periphery part. First connecting part connects central part and periphery part along first reference line and includes first inner connecting portion and first outer connecting portion. First inner connecting portion is connected to first joint. First outer connecting portion is connected to periphery part. First reference line passes through first joint, and first reference line is not parallel to line connecting center of mass and first joint.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: November 24, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Peng-Jen Chen, Bor-Shiun Lee, Chao-Ta Huang
  • Patent number: 10818611
    Abstract: Methods for compensating for bow in a semiconductor structure comprising an epitaxial layer grown on a semiconductor substrate. The methods include forming an adhesion layer on the backside of the wafer, and forming a stress compensation layer on the adhesion layer.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: October 27, 2020
    Assignee: II-VI Delaware, Inc.
    Inventors: Kevin Chi-Wen Chang, David Hensley, William Wilkinson
  • Patent number: 10794374
    Abstract: A microfabricated gas flow structure includes an array of vertical gas flow channels in a side-by-side parallel flow arrangement. Adjacent gas flow channels are separated by a thin wall having a thickness which can be an order of magnitude or more less than the channel width, offering exceptionally high area efficiency for the array. Channel walls can be formed from a dielectric material to provide the walls with sufficient integrity at nanoscale thicknesses and to provide thermal insulative properties in the lateral direction, thereby controlling power losses when the gas flow structure is employed as a Knudsen pump. The gas flow structure can be microfabricated as a monolithic structure from an SOI wafer, with the gas flow channels formed in the device layer and the heat sink formed from the handle layer.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: October 6, 2020
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Yogesh Gianchandani, Seungdo An, Yutao Qin
  • Patent number: 10777701
    Abstract: A photosensitive transistor device, on a semiconductor on insulator substrate, the photosensitive zone being formed in a substrate support layer and being arranged so that the concentration of photogenerated charges in the photosensitive zone can be increased towards a given zone facing the channel zone of the transistor.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 15, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Lina Kadura, Laurent Grenouillet, Olivier Rozeau, Alexei Tchelnokov
  • Patent number: 10745268
    Abstract: The present disclosure relates to a MEMS apparatus with a patterned anti-stiction layer, and an associated method of formation. The MEMS apparatus has a handle substrate defining a first bonding face and a MEMS substrate having a MEMS device and defining a second bonding face. The handle substrate is bonded to the MEMS substrate through a bonding interface with the first bonding face toward the second bonding face. An anti-stiction layer is arranged between the first and the second bonding faces without residing over the bonding interface.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Sung Chang, Fei-Lung Lai, Shang-Ying Tsai, Cheng Yu Hsieh
  • Patent number: 10697994
    Abstract: Techniques for compensating package stress of a proof mass are provided. In an example, a proof mass can be suspended from a substrate by a proof mass anchor. The first proof mass can have a major surface that defines a first plane. Portions of electrodes forming part of the proof mass can be symmetric with each other across a first line, wherein the first line bisects the first proof mass anchor, extends parallel to the first plane and extends between the first electrode and the second electrode.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: June 30, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Cenk Acar, Brenton Ross Simon, Sandipan Maity
  • Patent number: 10700660
    Abstract: A bulk acoustic wave (BAW) resonator includes: a substrate; an acoustic reflector disposed in the substrate; a first electrode disposed over the acoustic reflector; a second electrode; and a piezoelectric layer between the first and second electrodes. The second electrode is not disposed between the first electrode and the acoustic reflector. The BAW resonator further includes a block disposed over the substrate and beneath the piezoelectric layer. A contacting overlap of the acoustic reflector, the first electrode, the second electrode and the piezoelectric layer defines an active area of the BAW resonator.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: June 30, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: John Choy, Chris Feng, Phil Nikkel
  • Patent number: 10692753
    Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark D. Jaffe, Alvin J. Joseph, Qizhi Liu, Anthony K. Stamper
  • Patent number: 10634696
    Abstract: A multi-axis accelerometer may include a proof mass, a first electrode set, and a second electrode set. The first electrode set may detect acceleration along a second axis of the accelerometer, and may include a first electrode (C1) and a second electrode (C2). The second electrode set may detect acceleration along a first axis of the accelerometer that is orthogonal to the second axis, and may include a third electrode (C3) and a fourth electrode (C4). Application of a force along only the second axis may result in the exhibition of a non-zero change in differential capacitance between at least C1 and C2, but a zero net change in the differential capacitance between at least C3 and C4. As such, the accelerometer may exhibit little or no cross axis sensitivity in response to the applied force.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: April 28, 2020
    Assignee: Khalifa University of Science and Technology
    Inventors: Zakriya Mohammed, Waqas Amin Gill, Mahmoud Rasras
  • Patent number: 10566528
    Abstract: A radio frequency (RF) switch includes a heating element, a phase-change material (PCM) situated over the heating element, and PCM contacts situated over passive segments of the PCM. The heating element extends transverse to the PCM. The heating element can have a heater line underlying an active segment of the PCM. Alternatively, the heating element can have a split heater lines underlying an active segment of the PCM. The split heater lines increase an area of the active segment of the PCM and reduce a heater-to-PCM parasitic capacitance. A fan-out structure having fan-out metal can connect the heater line to a heater contact. The fan-out structure reduces heat generation outside the active segment of the PCM and reduces a heater contact-to-PCM parasitic capacitance. The fan-out structure can have dielectric segments interspersed between the fan-out metal to reduce dishing.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: February 18, 2020
    Assignee: Newport Fab, LLC
    Inventors: Nabil El-Hinnawy, Gregory P. Slovin, Michael J. DeBar, Jefferson E. Rose, David J. Howard
  • Patent number: 10566224
    Abstract: Methods, systems and devices for protecting partially processed electronic parts, are disclosed. In some embodiments, a method for protecting electronic parts includes applying a first protective sheet on one or more partially-processed semiconductor devices, removing the first protective sheet, and performing a semiconductor-processing operation on the one or more partially-processed semiconductor devices. In some embodiments, a semiconductor processing system for protecting electronic parts includes one or more partially-processed semiconductor devices, and a first protective sheet applied on the one or more partially-processed semiconductor devices, the first protective sheet being subsequently removed, and a semiconductor-processing operation being performed on the one or more partially-processed semiconductor devices.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: February 18, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventor: John D Steeves
  • Patent number: 10556792
    Abstract: The present disclosure relates to a micro-electro mechanical system (MEMS) package and a method of achieving differential pressure adjustment in multiple MEMS cavities at a wafer-to-wafer bonding level. A device substrate comprising first and second MEMS devices is bonded to a capping substrate comprising first and second recessed regions. A ventilation trench is laterally spaced apart from the recessed regions and within the second cavity. A sealing structure is arranged within the ventilation trench and defines a vent in fluid communication with the second cavity. A cap is arranged within the vent to seal the second cavity at a second gas pressure that is different than a first gas pressure of the first cavity.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: February 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Chia Lee, Chin-Min Lin, Cheng San Chou, Hsiang-Fu Chen, Wen-Chuan Tai, Ching-Kai Shen, Hua-Shu Ivan Wu, Fan Hu
  • Patent number: 10510662
    Abstract: One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh, Hui Zang
  • Patent number: 10508051
    Abstract: There are provided a lens forming mold, and a manufacturing method for a cylindrical lens, with which cylindrical lenses having good mass productivity can be manufactured. A lens forming mold for forming a molding on which a plurality of cylindrical surfaces are arranged in parallel includes: a first mold including a plurality of cylindrical surface forming portions that are arranged in parallel at equal intervals; and a first flat surface forming portion that is provided between adjacent cylindrical surface forming portions; and a second mold that sandwiches the glass material and faces the first mold when the molding is molded, in which the second mold includes a second flat surface forming portion that faces the plurality of cylindrical surface forming portions and the first flat surface forming portion.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: December 17, 2019
    Assignee: FANUC CORPORATION
    Inventor: Risa Ito
  • Patent number: 10446697
    Abstract: A bifacial solar cell includes a substrate of an n-type; an emitter layer positioned on a first surface of the substrate; a plurality of first electrodes locally positioned on the emitter layer and electrically connected to the emitter layer; a first passivation layer positioned on the emitter layer; a silicon oxide layer formed at an interface between the first passivation layer and the emitter layer, the silicon oxide layer having a thickness of about 1 nm to 3 nm; a first anti-reflection layer positioned on the first passivation layer; a plurality of back surface field layers locally positioned on a second surface of the substrate; a plurality of second electrodes respectively positioned on the plurality of back surface field layers and electrically connected to the plurality of back surface field layers; and a second passivation layer positioned on the second surface of the substrate.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: October 15, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Changseo Park, Yoonsil Jin, Youngho Choe
  • Patent number: 10431624
    Abstract: A method of manufacturing an image sensor includes: preparing a sensor substrate including: a sensor layer including a photosensitive cell; and a signal line layer including lines to receive electric signals from the photosensitive cell; forming a first material layer having a first refractive index on the sensor substrate; and forming a nanopattern layer on the first material layer, the nanopattern layer including a material having a second refractive index different from the first refractive index.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: October 1, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Seunghoon Han, Yongsung Kim, Seyedeh Mahsa Kamali, Amir Arbabi, Yu Horie, Andrei Faraon, Sungwoo Hwang
  • Patent number: 10418111
    Abstract: There are provided a memory system and an operating method thereof. A memory system includes: a memory device including a plurality of memory blocks, the memory device configured to perform a read operation on a selected memory block among the plurality of memory blocks; and a memory controller for controlling the memory device to perform the read operation, wherein an Initial turn-on period of the read operation is controlled based on information on an erase number of source line sharing blocks of the selected memory block.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventor: Chi Wook An
  • Patent number: 10374114
    Abstract: The lateral single-photon avalanche diode comprises a semiconductor body comprising a semiconductor material of a first type of electric conductivity, a trench in the semiconductor body, and anode and cathode terminals. A junction region of the first type of electric conductivity is located near the sidewall of the trench, and the electric conductivity is higher in the junction region than at a farther distance from the sidewall. A semiconductor layer of an opposite second type of electric conductivity is arranged at the sidewall of the trench adjacent to the junction region. The anode and cathode terminals are electrically connected with the semiconductor layer and with the junction region, respectively. The junction region may be formed by a sidewall implantation.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: August 6, 2019
    Assignee: ams AG
    Inventors: Jordi Teva, Frederic Roger, Ewald Stueckler, Stefan Jessenig, Rainer Minixhofer, Ewald Wachmann, Martin Schrems, Guenther Koppitsch
  • Patent number: 10338429
    Abstract: The present invention provides a method for manufacturing a quantum dot color filter, which uses a printing mold to pick up quantum dots and printing the quantum dots into a partially cured photoresist layer and then separates the quantum dots and the printing mold, followed by irradiation of UV light to completely cure the photoresist layer so that the quantum dots may uniformly distributed in the photoresist layer. This simplifies the process of transferring a quantum dot layer and reduces cost; requires no process of forming a sacrifice layer and no step of dissolving the sacrifice layer to prevent damage to the quantum dot layer; allows the quantum dots to be uniformly distributed in the photoresist layer to thereby improve the utilization of the quantum dots; and allows a quantum dot color filter so manufactured to be used with white backlighting or blue backlighting for achieving displaying of three primary colors of red, green, and blue.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: July 2, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Hongquan Wei
  • Patent number: 10310695
    Abstract: A sensor having a set of plates that are in contact from their bottom at the corners with a set of protrusions that are in contact from above with a plurality of intersections, each having a sensing element, of a grid of wires disposed on a base, and a top surface layer that is disposed atop the set of plates, so that force imparted from above onto the top surface layer is transmitted to the plates and then to the protrusions, and then to the intersections of the grid of wires which are thereby compressed between the base and protrusions; and that the protrusions above thereby focus the imparted force directly onto the intersections. A sensor includes a computer in communication with the grid which causes prompting signals to be sent to the grid and reconstructs a continuous position of force on the surface from interpolation based on data signals received from the grid. A method for sensing.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 4, 2019
    Assignees: Tactonic Technologies, LLC, New York University
    Inventors: Kenneth Perlin, Charles Hendee, Alex Grau, Gerald Seidman
  • Patent number: 10306372
    Abstract: The present invention provides a method for manufacturing a fully wafer-level-packaged MEMS microphone and a microphone manufactured with the same, the method comprises: separately manufacturing a first packaging wafer, an MEMS microphone wafer and a second packaging wafer; performing wafer-to-wafer bonding for the three wafers to form a plurality of fully wafer-level-packaged MEMS microphone units; singulating the fully wafer-level-packaged MEMS microphone units to form a plurality of fully wafer-level-packaged MEMS microphones, which are fully packaged at wafer level and do not need any further process after die singulation. The method can improve cost-effectiveness, performance consistency, manufacturability, quality, scaling capability of the packaged MEMS microphone.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: May 28, 2019
    Assignee: GOERTEK INC.
    Inventors: Quanbo Zou, Zhe Wang
  • Patent number: 10290670
    Abstract: A resonant-filter image sensor includes a pixel array including a plurality of pixels and a microresonator layer above the pixel array. The microresonator layer includes a plurality of microresonators formed of a first material with an extinction coefficient less than 0.02 at a free-space wavelength of five hundred nanometers. Each of the plurality of pixels may have at least one of the plurality of microresonators at least partially thereabove. The resonant-filter image sensor may further include a layer covering the microresonator layer that has a second refractive index less than a first refractive index, the first refractive index being the refractive index of the first material. Each microresonator may be one of a parallelepiped, a cylinder, a spheroid, and a sphere.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 14, 2019
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yuanwei Zheng, Gang Chen, Duli Mao, Dyson H. Tai, Lequn Liu
  • Patent number: 10274450
    Abstract: A capacitive environmental sensor and a method for determining the presence of a target substance (e.g. water) using differential capacitive measurements. The sensor includes a semiconductor substrate having a surface. The sensor also includes a plurality of sensor electrodes located on the surface. The electrodes are laterally separated on the surface by intervening spaces. The sensor further includes a sensor layer covering the electrodes. The sensor layer has a permittivity that is sensitive to the presence of the target substance. The surface of the substrate, in a space separating at least one pair of electrodes, includes a recess. The surface of the substrate, in a space separating at least one pair of electrodes, does not include a recess. The sensor may be provided in a Radio Frequency Identification (RFID) tag. The sensor may be provided in a smart building.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: April 30, 2019
    Assignee: ams International AG
    Inventors: Hilco Suy, Zoran Zivkovic, Franciscus Petrus Widdershoven, Nebojsa Nenadovic