Abstract: A method and system for verifying a correct orientation of a module during installation of the module into a circuit board mounting site. The module housing is symmetric in at least one respect such that the module may be positioned in at least one alternate orientation with respect to the mounting site in addition to the correct orientation. Within the module, a module test contact is electrically connected to a common plane mode contact. A mounting site test contact that engages the module test pin when the module is correctly aligned with respect to the mounting site is preselected to be tested upon placement of the module onto the mounting site. A test signal is applied to a conductive common plane within the mounting site to which a common plane mounting site contact is connected. Prior to installation of the module into the mounting site, the mounting site test contact is electrically isolated from the conductive common plane to which a test signal is applied.

Abstract: A mark structure (100) consists of a gate oxide film (102) formed on a semiconductor substrate (101), a gate wiring layer (103) formed on the gate oxide film (102), an insulating film (104) formed on the gate wiring layer (103) and a sidewall (105) formed in contact with side surfaces of the insulating film (104), the gate wiring layer (103) and the gate oxide film (102). An opaque bit line layer (113) is formed of a polycide consisting of a doped polysilicon layer (1131) and a tungsten silicide layer (1132), extending from on the interlayer insulating film (107) to on the mark structure (100). With this structure, a semiconductor device which allows measurement of alignment mark and overlay check mark with high precision in a lithography process, has no structure unnecessary for a mark and suppresses creation of extraneous matter in a process of manufacturing a semiconductor device to prevent deterioration in manufacturing process yield and a method of manufacturing the semiconductor device can be provided.

Abstract: A process of etching a semiconductor substrate and forming a trench which becomes a positioning mark on the semiconductor substrate, forming a burying film to fill the trench, forming a mask layer having an aperture to expose the trench, introducing an impurity to the trench with the mask layer used as the mask, and recessing the burying film in the trench which becomes the positioning mark.

Abstract: An alignment mark is formed in an SOI substrate comprised of a support substrate, an insulating layer and a semiconductor film by etching through first oxide and nitride films formed on the semiconductor film and etching through the semiconductor film and the insulating layer so that the hole extends to the support substrate. The first oxide film is formed on the semiconductor film and the first nitride film is formed thereover. The first nitride film is etched to expose part of the first oxide film and a well is formed in the semiconductor film by ion implantation in the region where the first nitride film is etched. The alignment mark is then formed by etching through the first nitride film, the first oxide film, the semiconductor film and the insulation layer so that the hole extends to the support substrate. Remaining portions of the first nitride film and the first oxide film are removed and second oxide and nitride films are formed on the semiconductor film.

Abstract: A method for fabricating a locally reinforced metallic microfeature on a substrate provided preferably with an electrical contacting or a driving circuit, and on an organic, patterned sacrificial layer, which is removed after the metallic microfeature is applied, is described. In fabricating the local reinforcement of the microfeature, at least one further organic layer, formed as a mask, is deposited, which is likewise removed following pattern delineation of the metallic layer.

Abstract: A mask overlay measurement target includes nested boxes on three levels or has adjacent boxes sharing a common side, saving substantial area. The nested overlay measurement target also provides savings in measurement time since multiple overlay combinations can be measured at once. The nested target provides more level-to-level overlay information than has been available with standard box-in-box targets. The nested boxes are also used on a single level to provide area savings for stepper field placement metrology.

Abstract: A method for realizing alignment marks on a semiconductor device employs a thicker dielectric layer than in the prior art. The method is used during a manufacturing process including at least a Chemical Mechanical Polishing process step, and includes forming alignment marks on a portion of a semiconductor substrate; masking the marks portion during a further deposition step of a first conductive layer covered by a first dielectric layer; depositing a first conformal metal layer over the first dielectric layer and over the marks portion; depositing a second dielectric layer over the first metal layer; and performing a CMP process step to planarize the second dielectric layer; wherein the thickness of the first dielectric layer is high enough that the second dielectric layer covers the alignment marks portion under the level of the first dielectric top surface thereby preventing the CMP process step to planarize the marks portion.

Abstract: In a method of manufacturing a semiconductor device, a plurality of inter layer conductive path is formed through a first resist pattern which in turn is formed by an exposure of a hole pattern mask. A plurality of conductive lines is formed, adjacent to the layer of the conductive paths, through a second resist pattern which in turn is formed by double exposure of a line pattern mask and the hole pattern mask. Each conductive line is positioned on at least one of the conductive paths. Or alternatively, each conductive path is positioned between the lines.

Abstract: A semiconductor device enabling precise and accurate measurement of an inspection mark in a simple manner is obtained. The semiconductor device includes a device forming area and a dicing line area arranged to surround the device forming area on a semiconductor substrate. In the dicing line area, first and second registration marks formed in different shots are provided, and the first and second registration marks include auxiliary marks for identifying the first and second registration marks.

Abstract: First, a conductive layer is formed on a semiconductor substrate having an alignment mark formed thereon. Next, a photoresist is selectively formed on a region of the conductive layer in which a wiring layer is to be formed and on the alignment mark. Subsequently, the conductive layer is etched by using the photoresist as a mask.

Abstract: A fabrication method for a semiconductor device is provided, which is able to increase pattern-to pattern lithography overlay accuracy. After a first layer made of a first material is formed, first and second slits serving as a first alignment mark are formed in the first layer. The first and second slits are spaced with a specific distance and are approximately parallel to each other. Each of the first and second slits is filled with a second material. Then, a second layer made of a third material is formed on the first layer. Subsequently, a mask is formed on the second layer. The mask has a first pattern serving as a second alignment mark. The second alignment mark is overlapped with the first and second slits serving as the first alignment mark. Preferably, the first alignment mark provides the main scale of a caliper, and the second alignment mark provides the vernier scale of the caliper.

Abstract: The present invention provides a semiconductor substrate comprising a semiconductor layer 3 formed on a supporting substrate 1 with interposition of an insulating layer 3 therebetween, wherein a mark is formed in a region other than a surface region of the semiconductor layer; and a process for producing the semiconductor substrate.

Abstract: The semiconductor device with the alignment mark includes a convex portion as a film growth control region for forming side surfaces approximately parallel to sidewalls on surfaces opposite to the sidewalls of first metal interconnection layer formed in a recess portion of the alignment mark at the time of deposition of first metal interconnection layer. Thus, the semiconductor device with the alignment mark and manufacturing method thereof allowing the easy and accurate detection of the location of a layer deposited on side surfaces of the alignment mark can be provided.

Abstract: A new method is provided for creating an aluminum pad on the surface of a semiconductor substrate. A passivation layer is deposited over the surface of the substrate; a layer of TaN is deposited over the passivation layer. A masked layer of aluminum is next deposited; this layer of aluminum is patterned such that the surface of the barrier layer that aligns with the alignment marker remains free of aluminum. Under the first embodiment of the invention, the exposed surface of the layer of TaN is etched to reduce the thickness of the layer of TaN to the point where the alignment marker is visible. Under the second embodiment of the invention, the exposed surface of the layer of TaN is oxidized to form a layer of Ta2O5 over this surface; this layer of Ta2O5 is transparent making the alignment marker visible.

Abstract: An etching mask is made of a metal such as Permalloy (NiFe) and has a T-shaped cross section made up of a vertical bar having width W1 and a lateral bar having width W2. Through ion beam etching with the etching mask, the region in the surface of a workpiece not covered with the mask is selectively removed by the ion beams applied thereto. In the mask the vertical bar has a region obstructed by the lateral bar and a redeposit portion. As a result, the region of the vertical bar near the interface between the workpiece and the vertical bar that substantially determines the pattern width does not change in width. Consequently, a pattern of the workpiece on which etching has been performed has the top width and bottom width substantially equal to width W1 of the vertical bar of the mask. The pattern is rectangular in cross section.

Abstract: According a method of manufacturing a semiconductor device, a polysilicon layer is formed on a semiconductor substrate and is patterned, thereby forming a storage electrode and plate electrode in a memory cell region and leaving the polysilicon layer in an aligning mark formation region. An interlevel insulating film is formed on the semiconductor substrate including the storage electrode, plate electrode, and polysilicon layer. An upper interconnection layer is formed on the polysilicon layer and is patterned, thereby forming an upper interconnection layer in the memory cell region and an aligning mark in the aligning mark formation region. An interlevel insulating film is formed on the upper interconnection layer and aligning mark and is etched back, thereby planarizing the memory cell region and aligning mark formation region and removing the interlevel insulating film on the aligning mark.

Abstract: The invention relates to a method of manufacturing an integrated semiconductor device on a substrate (1), comprising steps to manufacture a stack of layers (2, 3, 4, 5) on the substrate, and steps to manufacture circuit elements by means of photolithography including the formation of a centering mask, the formation of a reference pattern through an opening in this mask, and the formation of masks for defining circuit elements centered on the reference pattern.

Abstract: A semiconductor wafer having dot mark groups which are excellent in optical visibility and which have a peculiar configuration indicating the orientation of a crystallographic axis and a method of specifying the orientation of a crystallographic axis by the dot mark groups are provided. After a plurality of marks in a dot shape a part of which rising from the wafer surface within the predetermined region of a semiconductor wafer are formed, a group of epitaxial growth dot marks in which s single crystal is formed on the entire surface of the foregoing semiconductor wafer by the epitaxial growth, and a group of non-epitaxial growth dot marks in which no or little epitaxial growth is formed are made. By extracting the dot mark which is most excellent in visibility in the foregoing group of non-epitaxial growth dot marks, the orientation of a crystallographic axis is spsecified from this dot mark and the wafer center.

Abstract: A single multifunctional structure can be used to determine the alignment accuracy of the contact layer and the interconnect layer by inline visual inspection and by determination of the end of line electrical resistance properties.

Abstract: A method for determining the quality of features of a photoresist pattern, especially for vias and contacts, formed on a semiconductor wafer. A photoresist mask layer having a pattern of openings therein is deposited onto the wafer, and a test region (kerf) of the wafer is marked through the openings in the mask layer. In a preferred embodiment, the mask layer is a photoresist layer, although in alternative embodiments the mask layer could be provided as an insulator mask layer or a metal mask layer. The marking transfers an image of the bottom of the mask layer into the substrate by etching, such as by rastering a focused ion beam over the openings in the mask layer in the presence of an etchant gas. This provides an etched mark in the wafer defined by the passage of the focused ion beam through the mask opening. In alternative embodiments, the marking could be performed by staining or dyeing.

Abstract: A mark of a semiconductor device is formed of a molten trace obtained by selectively applying a laser to a ground back surface of a semiconductor substrate. Since the molten trace mark is formed in a form of a planarized surface on a back surface of a wafer or a chip which has been rendered uneven by grinding, visual recognition of the mark can be improved. Furthermore, since the mark is not deeply inscribed into the wafer or the chip, unlike the case of a dot mark, it is possible to maintain a die strength at a high level. In particular, when the molten trace mark is formed by using SHG-YAG laser, it is possible to suppress the depth of the layer from being thermally influenced, up to about several &mgr;m. As a result, it is possible to suppress thermal influence upon the inner circuit formed in a silicon chip and wiring formed therein.

Abstract: Offset alignment marks and a method of forming offset alignment marks within a kerf region of a semiconductor wafer in the manufacture of semiconductor devices includes the steps of forming a first track of a kerf and forming a second track of the kerf. The first track includes at least one alignment mark region having a first alignment mark disposed therein for use in an alignment of a first field of a first semiconductor chip active area. The second track includes at least one alignment mark region having a second alignment mark disposed therein for use in an alignment of a second field of a second semiconductor chip active area. The alignment mark regions of the first track and the second track are complementary and interlocking alignment mark regions extending across a centerline of the kerf and arranged in an offset manner with respect to one another along the kerf.

Abstract: A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a planar-surfaced layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the planar-surfaced layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers.

Abstract: Accurate photolighographic processing is achieved employing a stepper global alignment structure enabling formation thereon of a substantially transparent layer having a substantially planar upper surface. Embodiments include a set of global alignment marks comprising spaced apart trenches, each trench segmented into a plurality of narrow trenches spaced apart by uprights and forming a dummy topographical area of narrow trenches surrounding the set of alignment marks. The segmented trenches and the dummy topographical area effectively provide a substantially uniform topography enabling deposition of a transparent layer without steps and effective local planarization. Since the upper surface of the transparent layer is substantially planar, layers of material deposited on the transparent layer during subsequent processing also have a substantially planar upper surface, thereby enabling transmission of the signal produced by the alignment marks to the stepper with minimal distortion.

Abstract: A multi-segment alignment mark useful for a variety of processes is described. The multi-segment alignment mark comprises a plurality of segments wherein each of the segments comprises a series of sub-segments wherein each of the sub-segments comprises a series of spaces and lines, each sub-segment having the same width but having a different number of spaces and lines within the width depending on the relative width of the spaces and lines. A wafer stepper detects signals from each of the sub-segments and uses the best signal to achieve alignment.

Abstract: In this method of reconstructing an alignment mark during shallow trench isolation process, a mask layer is formed on the substrate and a cap layer is further formed to fill a recess within the mask layer above the alignment mark. A trench is then formed within the substrate. An insulating layer is formed to fill the trench and a CMP process is carried out to globally planarize the wafer until exposing the mask layer. The cap layer, the mask layer and the pad oxide layer are then successively removed. An isolation region is therefore formed in the trench and the alignment mark can be reconstructed.

Abstract: A semiconductor wafer (101) includes a first semiconductor die (103) having a first alignment mark (165) disposed in an alignment region (163) to align the first semiconductor die on the wafer. A second semiconductor die (181) has a second alignment mark (167) disposed in the alignment region such that the second alignment mark overlaps the first alignment mark. The area occupied by the overlapping alignment marks is shared between the first and second semiconductor dice to reduce the area and the cost of each die.

Abstract: A calibration standard comprises a supporting structure (1) of single crystal material with at least one pair of different kinds of structures consisting of a raised line (2) and a trench (3). These structures have the identical width in the range of about 500 nm. The single crystal material preferably is silicon with (110)-orientation.

Abstract: The present invention provides a semiconductor device which includes trench-type element isolation which performs accurate alignment without deteriorating a device capability, and a method of manufacturing such a semiconductor device. Since a dummy gate electrode (14A) is formed in an edge proximity region of a trench (10A), a structure which does not create an etching remainder is realized. In addition, since a height difference is provided in a surface of the dummy gate electrode (14A) in such a manner that the height difference reflects a preliminary height difference between a surface of a silicon oxide films (2A) and a surface of a silicon substrate (1), it is possible to use the dummy gate electrode itself (14A) as an alignment mark.

Abstract: A method for forming alignment keys on the scribe line areas of a semiconductor wafer. An etch blocking layer is used to reduce the depth of the channels forming the alignment key. One of the layers of material deposited on the semiconductor wafer to form integrated circuit devices on the wafer may be used as the etch blocking layer. A portion of this layer of material may be left intact on the scribe line areas during the manufacturing process. The subsequently deposited layers have an etch selectivity with respect to the etch blocking layer and the subsequently deposited layers are etched down to the etch blocking layer to form the alignment keys.

Abstract: A semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns.

Abstract: The object of the present invention is to provide a method of manufacturing an improved semiconductor device in which overlay-accuracy can be enhanced even when a halftone mask is used. An oxide film is formed on an antireflection film. Resist films are selectively irradiated with light using a halftone phase shift mask. Subsequently, it is developed to form resist patterns for a connecting hole and an overlay mark. According to the, present invention, the provision of an antireflection film under an oxide film prevents formation of a ghost pattern in an overlay mark portion.

Abstract: Various alignment targets are disclosed having improved visibility. A first embodiment includes an alignment target having a first reflective layer of a first material such as tungsten having a roughened surface; and a second layer of a second material, such as aluminum, deposited on the first layer. The surface of the second layer is roughened by conforming with the roughened surface of the first layer to provide both layers with a uniform optical layers. The edges of the second layer provides an optical signal to contrast between the two layers for alignment. A second embodiment includes an alignment target with a plurality of parallel elongated trenches; a first material fills each of the trenches; and a patterned layer of a second material is deposited on top the elongated trenches and the insulator layer.

Abstract: Partial wafer processing is achieved by down loading the wafer map of the whole wafer from a host (12) and if the partial wafer contains the reference die (14) move table to a locator die (15) and upload locator die coordinates to wafer map data host (16) and remove other partial wafer die coordinates from the map (17). If the partial wafer does not have the reference die and is not the last partial wafer, position wafer table to auxiliary reference die (18), validate the auxiliary reference die position (19) and compute auxiliary reference die coordinates from locator die coordinates (20) and move wafer table to locator die (22) and upload locator die coordinates to wafer map data host (23) and then using auxiliary reference die and locator die coordinates as information remove other partial wafer die coordinates from the map (24).

Abstract: An aberration estimation reticle is provided with a plurality of units spaced from each other. The unit is provided with a first determination mark having a square planar configuration, and a second determination mark located in the first determination mark and including a plurality of holes arranged along a square. These structures provide an overlay error determination reticle and a method of determining an overlay error with the reticle taking an influence by aberration into consideration.

Abstract: A test device and method for determining parameters of a plurality of vias formed into a dielectric material making contact to a buried conductive layer. The present invention is comprised of a sample structure disposed within the material through which a plurality of vias are to be formed. The sample structure is adapted to enhance secondary electron yield from the via bottom during a scanning electron microscope examination of the vias. Additionally, the plurality of vias to be formed are disposed intentionally offset with respect to the sample structure. As a result, the enhanced secondary electron yield from the sample structure characterizes the degree of misalignment present in the via formation process. In so doing, the present invention simultaneously quantifies the critical dimension of the vias, the alignment/registration of the via formation process, and determines whether or not the vias are etched to a minimum desired depth.

Abstract: Partial wafer processing is achieved by down loading the wafer map of the whole wafer from a host (2) and display the whole wafer in the die bonder monitor (3) move the wafer table to a first die pickup position (4) and move the display cursor to the first die pickup position (5) and teach two limit die coordinates in X direction (6) and teach two limit die coordinates in Y direction (7) and then using limit die coordinates as information remove other partial wafer die coordinates from the map (8) and select die pickup sequence (9).

Abstract: Provided is a method and composition for protecting alignment mark trench walls from attack by CMP slurry accumulating in an alignment mark trench during CMP processing. In a preferred embodiment, a metal organic chemical vapor deposition titanium nitride (MOCVDTiN) layer is deposited over a conventionally applied bulk tungsten layer prior to commencing CMP operations. This MOCVDTiN layer is resistant to CMP slurry attack. As a result, the tungsten trench profile remains a consistent and reliable alignment mark.

Abstract: On a semiconductor substrate, a registration measurement mark and intended patterns monitored by the registration measurement mark are provided. Step or level difference between the surface of registration measurement mark and the surface of intended patterns is made to be within .+-.0.2 .mu.m. By such structure, it becomes possible to accurately monitor the intended patterns by utilizing the registration measurement mark.

Abstract: A structure suitable for aligning two patterned conductive layers that are separated by a dielectric layer is described. Included in the lower pattern is a square and, as part of the upper pattern, four T-shaped capacitor electrodes are provided. The latter are positioned so that, when the alignment is exact, they all overlap the square by the same amount. Thus, under conditions of exact alignment, the capacitance value measured between any one of the top electrodes and the square will be the same for all electrodes. When, however, misalignment occurs, the degree of overlap will change, increasing on one side of the square while decreasing at the opposite side. In this way a comparison of measured capacitance values between electrodes located on opposing sides of the square will indicate whether, and what extent, misalignment has occurred.

Abstract: An integrated circuit and method for making it is described. The integrated circuit includes an insulating layer, formed within a trench that separates conductive elements of a conductive layer, that has a low dielectric constant. The insulating layer is convertible at least in part into a layer that is resistant to a plasma that may be used for a photoresist ashing step or to a solvent that may be used for a via clean step. Preferably the insulating layer comprises a silicon containing block copolymer that is convertible at least in part into a silicon dioxide layer. The silicon dioxide layer protects the remainder of the insulating layer from subsequent processing, such as photoresist ashing and via clean steps.

Abstract: A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The method also includes the step of fabricating a number of alignment trenches in the first conductor layer. Moreover, the method includes the step of depositing a first insulator layer on the first conductor layer so as to fill the number of alignment trenches. Yet further, the method includes the step of removing material associated with the first insulator layer from the number of alignment trenches such that an upper surface of the first conductor layer and an upper surface of the first insulator layer define a first alignment step feature which possesses a predetermined height. The method also includes the step of depositing a second conductor layer on the semiconductor wafer subsequent to the removing step. A semiconductor wafer is also disclosed.

Abstract: A plurality of alignment marks are formed on a semiconductor wafer in an area which is separate from or non-coincident with outside a plurality of chip regions, such as in a periphery of the wafer, irrespectively of the size and arrangement of the chip regions. Such wafers, which are previously manufactured, are then subjected to electron beam exposure in accordance with circuit design data. The electron beam exposure is typically implemented through global alignment using the alignment marks.

Abstract: The circuit board (1) has a component (101) mounted on it by means of a soldering process which causes an automatic, passive alignment of the component (101) due to the surface tension in a melted piece of solder which electrically connects two pads (2, 102), one (102) of which is on the component and the other (2) of which is on the circuit board. Stand-offs (20) are used to provide a suitable spacing or distance between the component (101) and the circuit board (1). The other pad (2) has a surface that is divided into a central part (3) and an edge part (4), both wettable by the solder. The second or edge part (4) is shaped like a ring and surrounds the central part and is composed so that it is more slowly wettable by the solder than the central part. The spacing established by the stand-offs is dimensioned so that a melted piece of the solder between the pads produces a force drawing the component (101) toward the circuit board (1) because of surface tension in the melted solder.

Abstract: An improvement in the box-in-box overlay measurement method has been achieved by forming the outer box from a segmented trench comprised of a number of concentric ridges that project upwards from the floor of the trench. When the segmented trench has been overfilled with tungsten (or similar metal) the excess metal is removed using either etch-back or chem. mech. polishing as the planarizing technique. Because of the presence of the ridges, the trench (i.e. the outer box) becomes reproducibly easy to see when the inner box (which will be etched from a second layer deposited on the first one) is being positioned inside it. Furthermore, the tendency for the outer box to be broken in critical places (often seen in the prior art) is now largely eliminated.

Abstract: A method is described for fabricating a module having a chip attached to a carrier substrate, wherein a guide substrate transparent to ablation radiation is used. A removable layer is provided on a surface of the guide substrate. A first alignment guide is formed on the removable layer, and a second alignment guide is formed on a front surface of the chip. The chip is aligned to the guide substrate by contacting the second alignment guide to the first alignment guide; the chip is then attached to the guide substrate. The carrier substrate is attached to the chip at the back surface of the chip. The interface between the removable layer and the guide substrate is then ablated using radiation (typically laser radiation) transmitted through the guide substrate, thereby detaching the guide substrate. Thin films with metal interconnections may then be provided on the front surface of the chip.

Abstract: A method for forming a field effect transistor on a substrate includes providing a wordline on the substrate; providing composite masking spacers laterally outward relative to the wordline, the composite masking spacers comprising at least two different materials; removing at least one of the materials of the composite masking spacers to effectively expose the substrate area adjacent to the wordline for conductivity enhancing doping; and subjecting the effectively exposed substrate to conductivity enhancing doping to form source/drain regions.

Abstract: A method for aligning and bonding balls to substrates, such as semiconductor wafers, dice and packages, is provided. The method employs a ball retaining plate having a pattern of micromachined cavities and vacuum conduits for retaining the balls. In addition, a substrate alignment member attached to the ball retaining plate, aligns the substrate to the balls. Using the substrate alignment member, bonding sites on the substrate can be placed in physical contact with the balls which are held by vacuum on the ball retaining plate. Next, the ball alignment plate and substrate can be place in a furnace for reflowing and bonding the balls to the bonding sites. An apparatus for performing the method includes the ball retaining plate and the substrate alignment member. A system for performing the method includes a ball loader mechanism for loading balls onto the ball retaining plate, and a vacuum fixture for applying a vacuum to the ball retaining cavities.

Abstract: The present invention provides a method of making CSP type semiconductor devices by the use of an general-purpose gang bonding type bonder while improving the yield. The method includes the steps of forming an imitation film carrier tape (20), disposing the imitation film carrier tape (20) relative to a semiconductor chip (12) so that an imitation junction (26a) and an electrode (13) face in a direction of opposing each other, positioning the imitation junctions (26a) with the electrode (13) while being observed through an aperture (22), removing the imitation film carrier tape (20) from the semiconductor chip and disposing a film carrier tape (30) at the same position as occupied by the imitation film carrier tape (20).

Abstract: The outer box of a box-in-box alignment pattern can be difficult to see if implemented in damascene technology. The present invention solves this problem by forming its outline from a trench that is substantially deeper than the channel used to contain the damascene wiring. This trench is formed at the same time that first vias are etched so no extra processing steps are needed, only one extra mask. The metal used for the damascene wiring also lines the inside of the trench, resulting in a structure that is easily seen during the alignment step. These outer box trenches may be simple squares or they may be ring shaped (hollow squares). Three different embodiments of the invention are described.