Abstract: A shot region includes a device region for forming a semiconductor device therein and a dicing region used for dicing. A portion of the peripheral edge portion of the shot region is defined by a portion of the peripheral edge portion of the device region. An alignment mark is arranged within the device region, and additional alignment marks are arranged within the dicing region. Thus, the number of the devices manufactured per wafer can be increased without degrading precision of alignment.

Abstract: A semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns.

Abstract: A first insulating film is formed on the surface of a silicon substrate, and a first silicide wiring layer is deposited on the insulating film. A first mark is formed by transferring the pattern of a first reticle formed on the silicide wiring layer. A second insulation film is deposited on the mark and the first insulation film, and a second mark is formed on the first mark by transferring the pattern of a second reticle formed on the second insulation film. A second silicide wiring layer is deposited in the second mark and on the second insulating film. An anti dust deposit and a third mark are formed by transferring the pattern of a third reticle formed on the second silicide wiring layer. Thus, dusts from the marks produced by transferring the reticle inspection marks of the reticles can be effectively prevented to improve the yield of LSIs.

Abstract: An alignment method for a semiconductor device having a conductive thin film on a conductive substrate surface across an insulation film, comprises steps of: forming in the insulation film, at least two apertures exposing the substrate surface therein; selectively depositing a conductive material in the apertures thereby forming a stepped portion in at least one of said apertures; and forming the conductive thin film at least on said insulation film. The alignment is conducted utilizing the stepped portion.

Abstract: A method is disclosed for connecting two components with functional parts in a predetermined alignment such as a semiconductor laser and motherboard including forming the laser by processing in which a radiation outlet and alignment structure are provided in a predetermined position with respect to each other, similarly forming on the motherboard, a waveguide and alignment structure, mounting the laser on the motherboard in a generally aligned position, providing solder between metal pads on the laser and motherboard and utilizing the surface tension of the molten metal extending between the pads to move the laser into an accurately aligned position on the motherboard.

Abstract: Method for the preparation of pattern overlay accuracy-measuring mark consisting of an inner box and an outer box. The method is characterized in that a groove is formed along the inside boundary line of the outer box, so as to enlarge step thereat. The enlarged step prevents inaccuracy in defining the boundary line, of the outer box whose inaccuracy is mainly attributed to smooth flow which occurs at the boundary line as a metal layer is coated over the outer box. Accordingly, the method can easily define the boundary line and thus, definitely measure the overlay accuracy.

Abstract: A method of fabricating a semiconductor device includes the steps of forming an inner circuit, a cell test pattern, and a superposition error measurement pattern. The inner circuit includes a plurality of recurring basic cells. The cell test pattern includes a test cell array having at least one test basic cell of the same design as the basic cells in the inner circuit and a plurality of test dummy cells disposed around the test cell array. The superposition error measurement pattern includes a first and a second pattern formed in the steps of a first and a second lithographic step, respectively, performed in the formation of the basic cells. The inner circuit, said cell test pattern and said superposition error measure pattern are integrated on the same semiconductor substrate.

Abstract: A method of fabricating semiconductor devices which eliminates the need to use additional window mask process to expose topographical marks, such as alignment targets, on a wafer when chemical-mechanical polish planarization technique are used to substantially planarize the surface of the wafer prior to metal deposition.

Abstract: A contact region for a trench in a semiconductor device and a method for electrically contacting the conductive material in a trench that is too narrow for conventional electrical contacts may include a contact region in which the trench is divided into two or more trench sections, each section having the same narrow width as the undivided trench. The two or more trench sections are separated by one or more islands that are isolated from the semiconductor device. An aperture through the material above the contact region provides access for electrically contacting the conductive material in the trench sections.

Abstract: Process for producing metrological structures particularly for direct measurement of errors introduced by alignment systems, whose peculiarity consists in performing, on a same substrate, metrological alignment markings and processed alignment markings according to arrays of preset numerical size.

Abstract: A method for forming an electrode on a mesa structure of a semiconductor substrate. The method comprises the steps of: selectively forming an electrode on a predetermined area in a surface of the semiconductor substrate; and subjecting the substrate to a selective etching by use of the electrode as a mask to form a mesa structure on the substrate so that the mesa structure is self-aligned just under the electrode.

Abstract: For end-to-end alignment of two optical waveguides one of which is in the form of a strip buried in a semiconductor wafer, a longitudinal lateral mark is used constituted by the flank of a valley etched in the wafer and self-aligned to the strip formed beforehand. To achieve this self-alignment a protection layer is deposited in the area in which the mark is to be formed, a register layer is deposited on top of the protection layer and a photosensitive resin is deposited on top of these layers and the substrate. First selective etching eliminates the register layer at the location of the valley of the mark. Second and third selective etching respectively etch the lateral channels of the strip and then the valley of the mark.