Abstract: A method of mending and testing a semiconductor apparatus. Only one L-shaped laser target or one set of targets forming a T-shaped target is in use. By choosing a primary laser target on the device with a damaged circuit, and a reference laser target on a device peripheral to the device with the damaged circuit, the laser mending machine is fed with the data of the coordinates of the primary and reference targets. The positions of these targets are scanned and calculated by the laser mending machine. With the feeding of the relative coordinates of these targets into the laser mending machine, the position to be mended, that is, the position with a damaged circuit, is obtained correctly. The fuse in the damaged circuit is then blown, and the circuit replaced by a new circuit with the same function.

Abstract: The present invention is intended to provide a semiconductor optoelectric device with high luminescent efficiency and a method of manufacturing the same. The semiconductor optoelectric device 18 according to the present invention is constructed by depositing compound-semiconductor layers 13 and 14 on a monocrystalline substrate 11 of a hexagonal close-packed structure. The shape of the monocrystalline substrate 11 is a parallelogram. Individual sides of the parallelogram are parallel to a <11-20> orientation. As the monocrystalline substrate, sapphire, zinc oxide or silicon carbide may be used. As the compound-semiconductor layers, an n-type GaN layer 13 and p-type GaN layer 14 may be used.

Abstract: A method is disclosed for forming alignment marks at the outer perimeter of wafers where they are not susceptible to much damage during chemical-mechanical polishing (CMP) process. Complete protection is provided by recessing the alignment mark into the substrate by etching. Recess etching is accomplished at the same time the isolation trenches are formed to delineate device areas. Thus, alignment marks are provided with a protective recess without extra steps. Furthermore, by forming alignment marks at the outer perimeter of the wafer, productivity is improved by providing maximum usage of wafer area for integrated circuits.

Abstract: Novel overlay targets and an algorithm metrology are provided that minimize the overlay measurement error for fabricating integrated circuits. The method is particularly useful for accurately measuring layer-to-layer overlay on a substrate having material layers, such insulating, polysilicon, and metal layers that have asymmetric profiles over the overlay targets resulting from asymmetric deposition or chemical/mechanically polishing. The novel method involves forming a triangular-shaped first overlay target in a first material layer on a substrate. A second material layer, having the asymmetric profile is formed over the first material layer. During patterning of the second material layer, smaller triangular-shaped second overlay target are etched. The vertices of the smaller second overlay targets are aligned to the midpoints of the sides of the first overlay target, which are less sensitive to the asymmetries in the second material layer.

Abstract: Process for making an integrated circuit module and product thereof including a carrier supporting a plurality of precisely aligned semiconductor circuit chips having uniform thicknesses.

Abstract: Disclosed is an overlay accuracy measurement mark used in measuring an overlay accuracy between any two selected device patterns in a semiconductor device having two or more multi-patterns. The mark is applied to a semiconductor device comprising a first pattern which is first formed, and second patterns consisting of at least one or more target patterns for alignment with the first pattern, which are formed after the formation of the first pattern.

Abstract: An alignment feature that avoids comet tail formation in spin-on materials and production method therefor. In one embodiment, the present invention alignment feature that comprises a trench is anisotropically etched into a surface of a substrate layer. The alignment feature exhibits a cross-sectional profile with sidewalls that are oriented substantially orthogonal to the surface of the substrate layer. Importantly, the present invention alignment feature does not have protruding structures disposed proximate to an intersection of the sidewalls and the surface of the substrate layer. The profile of the present invention alignment feature, with the absence of protruding structures as described above, averts the formation of comet tails in subsequently deposited spin-on materials. Thus, the present invention provides an alignment feature that completely avoids the deleterious effects of comet tails in spin-on materials without having to waste voluminous amounts of expensive spin-on materials.

Abstract: An alignment mark is formed in a planar semiconductor IC structure coated by a layer opaque to the radiations of the photo-stepper used to perform a photolithographic step. First, there is provided a structure comprised of a silicon substrate (11) having at least one shallow isolation trench (17A) in the chip region (13) and one shallow alignment trench (17B') in the kerf region (14) of the substrate wherein said alignment trench has a determined width (W'). Then, a layer (18) of an insulating material is conformally deposited onto the structure. Its thickness is adequate to over fill the trenches so that depressions (18A, 18B') are created above the locations of said isolation and alignment trenches. Next, the structure is planarized by filling the depression over said isolation trench but not the depression (18B') formed over said alignment trench to preserve it.

Abstract: A multi-segment alignment mark useful for a variety of processes is described. The multi-segment alignment mark comprises a plurality of segments wherein each of the segments comprises a series of sub-segments wherein each of the sub-segments comprises a series of spaces and lines, each sub-segment having the same width but having a different number of spaces and lines within the width depending on the relative width of the spaces and lines. A wafer stepper detects signals from each of the sub-segments and uses the best signal to achieve alignment.

Abstract: For electron beam wafer or mask processing, a registration mark is capacitively coupled to the top surface of an overlying resist layer on a substrate to form a voltage potential on the surface of the resist layer directly over the registration mark. The registration mark is directly connected to an electrical lead that produces an AC voltage on the registration mark, which is capacitively induced on the surface of the resist layer. Alternatively, the registration mark itself is capacitively coupled to a conductive plate placed on the bottom surface of the semiconductor substrate. An AC voltage is then applied to the conductive plate that induces a charge on the registration mark, which then capacitively induces a charge on the surface of the layer of resist. An electron beam scanning across the surface of the resist layer generates secondary electrons. The secondary electrons have a low energy and are affected by the voltage potential created at the surface of the resist layer.

Abstract: A shot region includes a device region for forming a semiconductor device therein and a dicing region used for dicing. A portion of the peripheral edge portion of the shot region is defined by a portion of the peripheral edge portion of the device region. An alignment mark is arranged within the device region, and additional alignment marks are arranged within the dicing region. Thus, the number of the devices manufactured per wafer can be increased without degrading precision of alignment.

Abstract: A fiducial for aligning an integrated circuit die. In one embodiment, the fiducial is configured to be exposed by laser chemical etching through a silicon substrate through the back side of a C4 packaged integrated circuit die. The presently described fiducial includes floating diffusion regions disposed in the substrate. An oxide layer free of metal contacts is disposed over the diffusion regions within the fiducial region of the integrated circuit. A metal pattern layer is disposed beneath the oxide layer to provide alignment information. The metal pattern layer is configured to be visible through the oxide layer after the silicon substrate has been removed from the fiducial region. A light block is disposed between the metal pattern layer and an underlying epoxy underfill layer to minimize the risk of an excessive amount of light from being exposed to the underlying epoxy layer, which minimizes the risk of the epoxy layer from damaging the integrated circuit from excessive light exposure.

Abstract: The system and method of the present invention enable the effective and efficient determination of the misalignment between openings located in the contact layer and the interconnect layer, respectively. In this way, defective semiconductors produced in semiconductor wafer fabrication can be readily identified and segregated for shipment to customers. A single multifunctional structure formed in the contact layer can be used to determine the alignment accuracy of the contact layer and the interconnect layer by (a) inline visual inspection and (b) determination of the end of line electrical resistance properties of the semiconductor wafer. Hence the use of the multi-functional aspects of this invention eliminates the correlation issues with the structure.

Abstract: A method of manufacturing a light-emitting or a light-receiving diode array chip. A first interlayer dielectric is formed in each of a plurality of chip areas on a substrate of a first conductivity type. Impurity diffusion regions of a second conductivity type are formed in the substrate using the first interlayer dielectric as a diffusion mask. An electrode is formed in contact with each of the impurity diffusion regions. The substrate is separated so that the plurality of chip areas are separated into individual chips. A second interlayer dielectric may be formed on the first interlayer dielectric after forming the impurity diffusion regions. The second interlayer dielectric is formed such that the second interlayer dielectric is absent from a second area along which the substrate is separated into the individual chips, at least in the vicinity of the last one of a plurality of windows.

Abstract: A method of manufacturing power semiconductor device, having an area of 3 cm.sup.2 or more, comprises the step of preparing a power semiconductor device divided into cell blocks and forming power semiconductor elements whose minimum linewidth is less than 10 .mu.m and having at least main electrodes completed in the cell blocks, the step of determining cell blocks having faulty portions, and the step of selectively electrically separating the main electrodes in the faulty cell blocks from the main electrodes in the good cell blocks.

Abstract: A method of removing a planarized insulating layer from over an alignment mark on a wafer. The invention allows steppers to see alignment marks without the difficulty of viewing the alignment marks through the insulating layer overlying the alignment marks. The method begins by chemical mechanical polishing a conformal oxide layer over a substrate. Next, a first photoresist layer is formed over the conformal oxide layer. Then vias are etched in the conformal oxide layer in the device area and etch the conformal oxide layer in the alignment mark area. Subsequently, we form a second photoresist layer over the first photoresist layer and the conformal oxide layer. The second photoresist layer filling the vias, but not the alignment mark resist opening. Then etch the second photoresist layer leaving sidewall spacers on the sidewall of the first photoresist layer in the alignment mark area and leaving photoresist plugs filling the vias.

Abstract: An apparatus in accordance with this invention includes an alignment mark that is formed in a substrate. The alignment mark extends across a dice line so that, upon dicing the substrate, the mark is exposed in the substrate's side edge. The mark is formed at a predetermined distance from a position at which a feature is desired to be formed on the substrate's side edge using a mask. Accordingly, the mark is a positional reference that can be used for highly accurate placement of the feature on the side surface of the substrate with the mask. Preferably, the mark is formed of metal or other material enhanced to a size that is readily detectable by an alignment system with which the mark is to be used. The invention also includes methods for making the alignment mark.

Abstract: A method for aliging a shallow trench isolation is provided. An aligning mark which is deeper than a prior technique is formed in a provided substrate. A trench is formed and an aligning trench is formed in the position over the aligning mark. A thick oxide layer is deposited on the semiconiductol substrate, in the trench and in the aligning trench. After a portion of the thick oxide layer removed, another portion of the thick oxide layer is removed by etching back. A gate oxide layer is formed on a substrate comprising the trench and the aligning trench. A polysilicon layer with the step-height profile in the position over the aligning mark is formed on the gate oxide layer.

Abstract: An engraved recess (4) is formed in a resin stencil (1) at a position on a surface of the resin stencil where the resin stencil, when registered with a circuit board, agrees with a fiducial mark of the circuit board. The recess is formed by a laser (3) and serves as a fiducial mark.

Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.

Abstract: On a semiconductor substrate, chips to be products and alignment chips located at a portion a part thereof is left out from a peripheral part of the semiconductor substrate are formed. Contact holes and alignment marks are formed at the chips to be products and the alignment chips. Covering the alignment chips with alignment mark cover parts of a substrate holder, a material for metal wiring is deposited on the semiconductor substrate to form a metal film on the substrate. A mask pattern is formed on the metal film using the alignment marks of the alignment chips on which the metal film is not formed.

Abstract: A method of alignment for a chemical mechanical polishing includes previously patterning a primary zero alignment mark on a surface of a wafer. A first dielectric layer is deposited on the wafer for isolation. Then, an etching is used to etch the first dielectric layer using a photoresist as a mask. First conductive plugs are formed in the first dielectric layer. Next, a first conductive layer is formed on the surface of the first dielectric layer and on the tungsten plugs. Thus, the first non-zero alignment mark pattern is formed on the surface of the first conductive layer and aligned to the first conductive plugs. Next, a second non-zero alignment mark pattern is thus formed on the surface of a second conductive layer and aligned to the a second conductive plugs. By repeating the aforementioned method, odd non-zero alignment mark patterns will be formed over the first non-zero alignment mark pattern, and even non-zero alignment mark patterns will be formed over the second non-zero alignment mark pattern.

Abstract: A semiconductor processing method of forming integrated cicuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective-series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns.

Abstract: A method for fabricating a thin film transistor of a liquid crystal display device comprising the steps of introducing a dopant into an indium tin oxide layer or gate insulating layer with an ion shower doping process, forming an amorphous silicon layer thereon, exposing the amorphous silicon layer with a laser beam to diffuse the dopant into the amorphous layer and activate the dopant. As a result of the laser annealing, an n or p-type ohmic polysilicon layer and an intrinsic polysilicon channel layer can be formed. A gate electrode can also be formed on a gate insulating layer using a gate mask.

Abstract: The contact hole via mask used in the manufacture of semiconductor integrated circuits is modified to produce a multiplicity of lines and spaces adjacent to the edge of an alignment mark in the via hole pattern. This line-space pattern is etched simultaneously with the contact via holes, and allows the regeneration of the alignment mark after tungsten deposition and planarization of the surface by conventional oxide etching and metallization steps.

Abstract: The present invention concerns a process that maintains a second (or "replica") set of alignment marks during existing processing steps used in manufacturing a semiconductor device or integrated circuit, including CMP and other planarization methods. The present invention avoids alignment problems encountered in conventional CMP processes, particularly tungsten CMP. All alignment steps can be realized through one or more subsequent second (or "replica") alignment marks, set and preserved throughout the remaining process steps, thus maintaining alignment integrity. The present method and apparatus concerns a new alignment mark that may be "printed" in a metal layer on the wafer, for example, a local interconnect or contact layer. The new alignment mark is generally not subjected to planarization or to an "open frame" process. The new alignment mark may also be used to re-etch other alignment marks directly onto the layer conventionally causing alignment problems, such as those created following CMP.

Abstract: Various alignment targets are disclosed having improved visibility. A first embodiment includes an alignment target having a first reflective layer of a first material such as tungsten having a roughened surface; and a second layer of a second material, such as aluminum, deposited on the first layer. The surface of the second layer is roughened by conforming with the roughened surface of the first layer to provide both layers with a uniform optical layers. The edges of the second layer provides an optical signal to contrast between the two layers for alignment. A second embodiment includes an alignment target with a plurality of parallel elongated trenches; a first material fills each of the trenches; and a patterned layer of a second material is deposited on top the elongated trenches and the insulator layer.

Abstract: A method of forming an alignment mark in a wafer during the manufacture of shallow isolation trenches for semiconductor devices provides a nitride layer on a substrate prior to the formation of the alignment mark. Once the nitride layer has been formed, etching is performed to create the alignment mark in the substrate. Further processing steps of the shallow trench isolation technique do not require the depositing of nitride into the alignment mark. Since the alignment mark is etched only after the nitride layer has been deposited, no further nitride enters into the alignment mark and a nitride-free alignment mark is provided.

Abstract: The present invention provides a semiconductor device which includes trench-type element isolation which performs accurate alignment without deteriorating a device capability, and a method of manufacturing such a semiconductor device. Since a dummy gate electrode (14A) is formed in an edge proximity region of a trench (10A), a structure which does not create an etching remainder is realized. In addition, since a height difference is provided in a surface of the dummy gate electrode (14A) in such a manner that the height difference reflects a preliminary height difference between a surface of a silicon oxide films (2A) and a surface of a silicon substrate (1), it is possible to use the dummy gate electrode itself (14A) as an alignment mark.

Abstract: An integrated circuit and associated method for reducing total signal propagation delay as well as power consumption and thermal dissipation. The integrated circuit comprises a plurality of active layers coupled together in close proximity. In order to produce the integrated circuit, at least two active layers are removed from their respective substrate after integrated circuit processing. Some of the methods that may be used include Silicon on Insulator ("SOI") and epitaxial etch stop ("EES") processes. After removal of the active layers, at least one via is implemented on a bottom surface of each active layer in order to establish a mechanical and electrical connection between the via and its associated metal interconnects. Thereafter, the active layers are coupled together by ultrasonic welding or through nitride lamination using Titanium Nitride for conductive regions and Silicon Nitride for insulative regions.

Abstract: An active mask is used to etch field oxide in active areas down to an n- epitaxial substrate. After gate oxide growth, a polysilicon layer is deposited and planarized. The active mask defines the polysilicon gate critical dimension for a terrace gate DMOS structure. The edges of the polysilicon gates are self-aligned to the edges of the thick terrace gate oxide. Because no interlayer alignment is required to delineate the polysilicon gate, the design need not provide for alignment tolerance. A non-critical mask is deposited overlapping the terrace oxide. An etch back to field oxide in exposed areas is performed. An oxide-selective etch is performed to reduce the oxide thickness in source regions. Self-aligned body implantation, body contact masking and implantation, and source masking and implantation are performed. A dielectric is deposited. A source contact mask is deposited and a contact etch is performed. Source metal is deposited, and passivation layer is formed.

Abstract: A semiconductor substrate with no reduction in the effective usage area and mechanical strength, and non-uniformity of the resist film thickness, and method of manufacturing and using the same are obtained. A detection mark for detecting the crystal orientation of a silicon wafer having an outer perimeter entirely of a circular contour is formed at a predetermined region of the silicon wafer. The crystal orientation of the semiconductor wafer can easily be detected with the outer perimeter still taking a circular contour. Therefore, various problems encountered in a conventional semiconductor substrate having an orientation flat or notch such as reduction in mechanical strength and effective usage area, and non-uniformity of the resist film can be circumvented.

Abstract: The contact or via hole etch pattern photomask used in fabrication of integrated circuits is modified to provide a series of grooves or trenches to be etched in the silicon oxide layer simultaneously with the contact or via holes. These trenches, after deposition and planarization of tungsten metal layer, afford regenerated alignment marks with sharply-defined edges even after deposition of a second conductive layer.

Abstract: Disclosed herein is a composite SOI substrate which allows, by use of a conventional visible light aligner, high-precision alignment of insulator film patterns buried in an SOI substrate and patterns which are to be formed on the SOI layer located above it. The composite SOI substrate is fabricated by forming alignment oxide film patterns I a on the periphery of a main surface of a first silicon substrate 10 which also has buried oxide film patterns formed thereon; preparing a second silicon substrate having preferably V-shaped notch sections 9 on its periphery to expose the alignment patterns provided on the first silicon substrate; bonding the second silicon substrate to the main surface side of the first silicon substrate 10 while exposing the alignment oxide film patterns 1a; and then thinning the second silicon substrate to form an SOI layer 20a.

Abstract: A method of fabricating vertically integrated microelectronic systems by CMOS-compatible standard semiconductor process technology, by independently processing individual component layers of at least two separate substrates, including the formation of via holes penetrating through all existing component layers and connecting together the front surfaces of the two substrates, thinning the reverse surface of one of the substrates down to the via holes, increasing the depth of the via holes to a metallization plane of the other substrate and forming electrically conductive connections between the two substrates through the via holes.

Abstract: In order to provide a search alignment method capable of high-speed alignment without a relative movement between an alignment system and a substrate, an alignment mark is constituted by a plurality of element marks having shapes different from each other, the plurality of element marks are provided in such a manner that each two of them has a gap a little shorter than the size of the field of view of the alignment system therebetween, and if even one of the element marks constituting the alignment mark comes into the field of view of the alignment system, said element mark is identified out of all of said element marks, whereby the position of the entire alignment is measured from the position of said one element mark. Therefore, if the alignment mark is moved in a range wider than the field of view of the alignment system, it is possible to detect the position of the alignment mark by one measurement.

Abstract: A mask, which does not require additional reticles, and a method of using the mask for recovering alignment marks in a wafer after an inter-level dielectric layer has been planarized and a second layer of metal has been deposited on the planarized inter-level dielectric layer are described. An alignment mark protection pattern and a clearout window pattern are sub-divided so they can be formed from a first and a second mask element. These mask elements can be formed in the peripheral region of the reticle used to pattern the device region of the wafer. The mask elements are used to expose the alignment mark protection pattern in a first layer of photoresist and the clearout window pattern in a second layer of photoresist.

Abstract: To form NPN and PNP transistors on the same base for example to obtain a complementary bipolar transistor it has been necessary to make an epitaxial layer a thick film, and this has resulted in deterioration of the characteristics of the NPN transistor. Also, because a step of forming an alignment mark has been necessary this has increased the number of manufacturing steps needed to make a complementary bipolar transistor. This invention provides a semiconductor device manufacturing method which solves this problem as follows: After a first opening 13 (alignment mark 16) and a second opening 14 are formed in an insulating film 12 formed on a semiconductor base 11 and a doping mask 15 is then formed on the semiconductor base 11, a third opening 17 is formed thereon with the alignment mark 16 as a reference.

Abstract: A method for forming interconnections for semiconductor fabrication and semiconductor devices have such interconnections are described. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filled with conductive material. Another patterned dielectric layer is formed over the first dielectric layer and has a second opening over at least a portion of the conductive material. The first patterned dielectric layer may serve as an etch-stop in patterning the other patterned dielectric layer. Also, a dielectric etch-stop layer may be formed over the first patterned dielectric layer and over the conductive material before the other patterned dielectric layer has been formed. This dielectric etch-stop layer may serve as an etch-stop in patterning the other patterned dielectric layer. The second opening exposes a portion of the dielectric etch-stop layer. The exposed portion of the dielectric etch-stop layer is removed.

Abstract: A method of fabricating high step alignment marks on a twin-well integrated circuit. An alignment mark photoresist pattern is formed overlaying the nitride layer using lithography technique. The nitride layer is partially etched to form a nitride alignment pattern using the alignment mark photoresist pattern as a mask. After the formation of N-well and P-well regions using lithography technique, the N-doped and P-doped impurities are subject to a thermally drive in process to activate and form N-well and P-well regions, respectively. At the same time, the pad oxide layer overlaying the N-well and P-well regions and the region not covered by the nitride alignment pattern is converted to a thermal oxide layer. The thermal oxide layer can be removed to reveal a recessed portion on the surface of the P-type silicon substrate, whereby the thickness of the nitride layer plus the depth of the recessed portion causes high step alignment marks to be formed.

Abstract: The present invention is a method of protecting an alignment mark in semiconductor manufacturing process with CMP. This invention utilizes a via mask or masking blade to remove the intermetal dielectric layer on a wide clear -out window using two etching steps. One etching step is performed before intermetal dielectric layer polish. The other etching step is performed after intermetal dielectric layer polish. Thus, there is no intermetal dielectric layer remained on the alignment mark and the alignment mark keeps the original shape.

Abstract: Shot regions on a wafer are exposed and a first reticle pattern image is transferred thereon, and an LSA mark is formed in the center of each shot region of a chip positioned centrosymmetrically with respect to the center of the wafer. The wafer is prealigned, a rotation is corrected, and the position of the LSA mark is measured. The error parameter is produced by means of least squares method based on designed values and measured values to produce a new chip arrangement map, based on which the second and on reticle patterns are transferred by exposure. Thus, an offset correction fault with the rotation component of the reticle pattern is eliminated, thereby increasing throughput.

Abstract: Disclosed is an alignment mark for the X directional alignment of a chip area on a semiconductor wafer, for example. The alignment mark comprises recesses and projections formed on a semiconductor substrate. The recesses or projections are repeatedly arranged in the X direction. The X directional width of the recesses or projections is set smaller than the X directional width of a grain on a metal film formed on the recesses and projections or the average particle size, as viewed from above the semiconductor substrate. The projections may be formed by an insulating layer formed on the semiconductor substrate.

Abstract: A structure of a readable alignment mark and method of manufacturing the readable alignment mark in an alignment mark area on a semiconductor substrate. A semiconductor substrate 10 comprising a product area 12 and an alignment mark area 30 is provided. The alignment mark area 30 has an outer area 40 and an inner area 50. The outer area surrounds 40 the inner area 50. A plurality of alignment mark trenches 24 is formed in the substrate 10 within the inner area 50. A pad oxide layer 20 and a silicon nitride layer 44 are formed sequentially in at least the alignment mark area 12. An isolation trench 43 is formed in the substrate 10 in at least the outer area 40. An insulating layer 46 is formed at least over the alignment mark area 30. The insulating layer 46 is chemical-mechanical polished thereby removing a first thickness of the insulating layer from the inner alignment mark area 50 and leaving a residual insulating layer 46A in the alignment mark trenches 48.

Abstract: A method of fabricating alignment marks on an integrated circuit device including steps of: forming first pad oxide layer and first nitride layer on a P-type semiconductor substrate; coating and patterning first photoresist layer by lithography; partially etching first nitride layer to form first nitride pattern by first photoresist etching mask; and ion implanting N-type ions to form an N-doped region; coating and patterning second photoresist layer by lithography; partially etching first nitride pattern to form second nitride pattern; and ion implanting P-type ions to formed a P-doped region. Next, performing thermally drive in N-type and P-type impurities to form N-well and P-well regions, and growing an oxide layer simultaneously. Finally, the height difference between the oxide layer and the second nitride pattern producing a ladder topography can be used as an alignment mark for the succeeding lithographic processes.

Abstract: An overlay mark for detecting focus and exposure energy during an alignment process for forming a pattern of a semiconductor device is disclosed. The overlay mark includes an inner box and an outer box to concurrently measure exposure energy and focus, wherein, the changes of the exposure energy and the focus are respectively represented by phase shift between the inner and outer boxes in X-axis and Y-axis, the X-axis and the Y-axis representing phase shift respectively to indicate the exposure energy and the focus.

Abstract: A method of making a vertical integrated circuit by providing first and second substrates surfaces of which have layers with circuit structures and metallization planes therein, by providing an etching mask on a primary surface of the first substrate, forming via holes in the first substrate extending through the masking surface and the layers of the first substrate, reducing the thickness of the first substrate from a surface opposite its layer surface, alignedly connecting the first substrate by its reduced surface to the layer surface of the second substrate, subsequent deepening of the via holes to the metallization plane of the second substrate and forming electrical interconnection between the metallization planes in the first and second substrates through the via holes.

Abstract: A process for forming an integrated circuit structure is described wherein individual integrated circuit devices such as MOS or bipolar transistors are constructed on and in a semiconductor substrate and one or more layers of metal interconnects are constructed on and in a second substrate, preferably of similar thickness, and the two substrates are then aligned and bonded together to thereby provide electrical interconnections of individual integrated circuit devices on the semiconductor substrate with appropriate metal interconnects on the second substrate to provide the desired integrated circuit structure.

Abstract: A method for forming a patterned non-transparent layer over a substrate. There is first provided a substrate which has an alignment mark formed thereupon. There is then formed over the substrate including the alignment mark a blanket non-transparent layer. The blanket non-transparent layer only partially replicates the alignment mark to yield upon the blanket non-transparent layer a partially replicated alignment mark at a location substantially corresponding with the location of the alignment mark formed upon the substrate. There is then removed through a first photolithographic and etch method a first portion of the blanket non-transparent layer to completely expose the alignment mark while simultaneously forming a partially patterned non-transparent layer. The first photolithographic and etch method employs the partially replicated alignment mark to register a first photolithographic mask with respect to the substrate.

Abstract: In a method for mounting an integrated optical component, a starting base structure includes a silica lower confinement layer and the cores of the future optical waveguides. This basic structure includes an alignment abutment so that a component to be mounted can be subsequently aligned with these waveguides. A silicon barrier layer is deposited on the abutment. Flame hydrolysis deposition is then used to deposit an upper silica layer to constitute the upper confinement layer of the waveguides. This silica layer also covers the alignment abutment, however. For this reason the region of the abutment is then etched by reactive ion etching to expose the abutment, which is protected from this etching by the barrier layer. The component to be mounted is then located relative to the abutment.