Abstract: A method of fabricating a polysilicon film by an excimer laser annealing process is introduced. First, an amorphous silicon film is deposited on a substrate composed of glass. The amorphous silicon film includes a first region, which is located in the center, with a first thickness, and a second region, which is located in the periphery, with a slant sidewall. The thickness of the amorphous silicon film is measured so as to obtain the profile of the sidewall in the second region. According to the profile of the sidewall, a pre-cursor region is determined for performing an excimer laser annealing process wherein a second thickness in the boundary of the pre-curser regionis smaller than the first thickness so as to increase area of produced polysilicon film.

Abstract: A nanoscopic tunnel is disclosed. The tunnel can be formed in or on a substrate, such as a semiconductor.

Abstract: For fabricating a shallow trench isolation structure, a notched masking structure is formed over an active area of a semiconductor substrate. A shallow trench opening is formed at a side of the active area with a top corner of the shallow trench opening being exposed and facing a notched surface of the notched masking structure. Liner oxide is formed in a thermal oxidation process at the top corner of the shallow trench opening to round the top corner of the shallow trench opening. The liner oxide may also be formed on walls including the bottom corner of the shallow trench opening during the thermal oxidation process. The shallow trench opening is then filled with a trench dielectric material to form the shallow trench isolation structure.

Abstract: A semiconductor memory device having a floating gate and a method of manufacturing the same, where a conductive layer for a floating gate is deposited on a semiconductor substrate and etched to form a conductive layer pattern. An annealing of the semiconductor substrate is carried out in an ambient atmosphere of hydrogen gas. Alternatively, an entire surface of the conductive layer pattern is etched by a dry etching method or a wet etching method. As a result, at least one edge of the conductive layer pattern is rounded, which reduces the likelihood that an electric field is concentrated at the edge and reduces a likelihood that the dielectric layer formed on the floating gate is thinner at the edge.

Abstract: A method for forming trenches in a device layer disposed on a silicon semiconductor substrate comprises: covering the device layer with an etch resistant masking layer to define at least two trench regions; removing semiconductor material from the exposed trench regions by applying an etching agent that selectively etches the semiconductor substrate with respect to the trench masking layer, thereby forming at least two trenches each comprising a floor and sidewalls; and, during the removal of semiconductor material, exposing the sidewalls to a passivating agent in increasing amounts, thereby passivating the sidewalls while reducing lateral etching of semiconductor material from them.

Abstract: A hard mask made from polysilicon is used to etch a layer to be patterned. The hard mask is patterned using a resist mask. The etching of the hard mask is carried out in such a way that the openings which are etched into the hard mask have inclined sidewalls. This reduces the cross section of the openings, with the result that smaller openings can be formed in the layer that is to be patterned than the openings which have been predetermined by the resist mask. The hard mask is etched using only HBr. The inclination of the openings etched into the hard mask can be set by way of the TCP power and/or the bias power of a TCP etching chamber, and/or by way of the HBr flow rate.

Abstract: A transistor includes a substrate and a gate electrode formed on the substrate and having a wider upper portion than lower portion. A spacer is formed on the side wall of the gate electrode from the upper portion to the lower portion of the gate electrode. A first impurity doped region is formed at an upper portion of the substrate and a second impurity doped region having a higher concentration is formed at a narrower and deeper region than the first impurity doped region.

Abstract: A method of fabricating a nitride read only memory. A trapping dielectric sandwiched structure, including an insulation layer, a charge trap layer and an insulation layer, is formed on a substrate. An opening with indented sidewalls is formed in the insulation layer. A thermal oxide layer is formed to fill the opening, such that the indented sidewalls are completely sealed. The charge trap layer is thus sealed by the insulation layers and the thermal oxide layer to avoid the direct contact between the control gate and the charge trap layer, so as to prevent the data loss.

Abstract: A method of manufacturing a group III nitride compound semiconductor device, includes providing a substrate, forming a group III nitride compound semiconductor layer having a device function, and forming an undercoat layer between the substrate and the group III nitride semiconductor layer, the undercoat layer having a surface of a peak and trough structure.

Abstract: A process of forming an anti-fuse. First, an inter-metal dielectric layer, in which a funnel-shaped via is formed, is formed on a substrate. Next, a first conductive layer is formed over the substrate and filled into the funnel-shaped via. Subsequently, by, for example, a chemical mechanical polishing process, the first conductive layer outside the funnel-shaped via is removed to form a conductive plug. Afterward, an oxide chemical mechanical polishing process is performed to smooth the surface of the conductive plug. Next, a dielectric layer is formed on the top side of the conductive plug, and then a top plate is formed on the dielectric layer. Subsequently, an insulating layer is formed over the substrate, wherein the insulating layer is provided with a via and the via exposes the top plate. Finally, a second conductive layer is formed over the substrate and filled into the via.

Abstract: A method of forming metal fuses and bonding pads. A conductive layer is formed in a substrate. A dielectric layer is formed over the substrate. The dielectric layer has an opening that exposes a portion of the conductive layer. A metallic layer is formed over the dielectric layer. The metallic layer is patterned to form a metal fuse and a bonding pad. The bonding pad is electrically connected to the conductive layer via the opening. Both the metal fuse and the bonding pad have undercut sidewalls. Spacers are formed on the undercut sidewalls of the metal fuse and the bonding pad. Finally, a passivation layer that exposes the metal fuse and the bonding pad is formed over the substrate.

Abstract: In the method, a substrate is coated with different films to be patterned. These films have different etch rates. The films and substrate are then coated with a primary etch mask, and subsequently patterned to produce an electrode that has a gradual taper at the electrode edge. The formed electrode eliminates any abrupt substrate to electrode step, so that any subsequent thin-film deposition of piezoelectric material is continuous over the entire electrode surface and the electrode/substrate interface.

Abstract: In a semiconductor device functioning as a three-dimensional device composed of two semiconductor chips bonded to each other, the back surface of the upper semiconductor chip is polished, the entire side surfaces of the upper semiconductor chip are covered with a resin layer, or the center portion of the upper semiconductor chip is formed to be thicker than the peripheral portion thereof. This suppresses the occurrence of a package crack and improves the reliability of the semiconductor device.

Abstract: An interconnect structure of a semiconductor device includes a tungsten plug (14) deposited in a via or contact window (11). A barrier layer (15) separates the tungsten plug (14) from the surface of a dielectric material (16) within which the contact window or via (11) is formed. The barrier layer (15) is a composite of at least two films. The first film formed on the surface of the dielectric material (16) within the via (11) is a tungsten silicide film (12). The second film is a tungsten film (13) formed on the tungsten silicide film (12). A tungsten plug (14) is formed on the tungsten film (13) to complete interconnect structure. The barrier layer (15) is deposited using a sputtering technique performed in a deposition chamber. The chamber includes tungsten silicide target (19) from which the tungsten silicide film (12) is deposited, and a tungsten coil (20) from which the tungsten film (20) is deposited.

Abstract: A method of manufacturing a microstrip termination is provided, the microstrip termination containing a transmission line, a tapered edge ground and a thin film resistor connecting a transmission line to the tapered edge ground. Circuits are manufactured by first cutting holes in a substrate forming alignment holes for dicing the substrate into separate circuits. A saw is then used to cut tapered grooves along the alignment holes for forming tapered edges. The substrate is then plated and etched to form the transmission lines, thin film resistors, and ground planes. Finally, the substrate is diced into the separate termination circuits.

Abstract: This invention concerns a method of forming vertical knife-edge cold-cathode field emission electron sources with self-aligned gate electrodes and sub-micron electrode separations. The method exploits the enhancement of ion-beam erosion rates obtained in metals at oblique ion incidence, which allows the preferential removal of a metal layer at the convex edge of a mesa 2 to create a well-defined separation between the horizontal and vertical surfaces of the metal. The horizontal surface may be used as the gate and the vertical surface as the cathode in a vacuum triode structure. Electrical isolation is obtained by forming the mesa 2 in an insulating layer or substrate 1. Isolation may be improved by removing the insulating material in the vicinity of the metal edges. Field-induced electron emission from the cathode may be obtained at low voltage based on the enhancement of the electric field at the sharp tip of the cathode.

Abstract: A method for manufacturing a semiconductor device having a circuit made up by a TFT (Thin Film Transistor) having GOLD (Gate-Drain Overlapped LDD) structure, which an LDD region overlaps which a portion of a gate electrode, wherein the formation of a concentration depth profile peak of hydrogen in a semiconductor film is avoided to thereby improve the electrical characteristics of the TFT. The use of the semiconductor film manufactured in this manner allows manufacturing of a semiconductor device with good electrical characteristics only by hydrogenating treatment even when the activation of impurity elements does not carried out.

Abstract: Method and apparatus for etching a tapered trench in a layer of material with a highly controllable wall profile. The layer of material has a mask adjacent a surface thereof having an opening which defines a location on the layer of material at which the trench is to be formed. Vertical etch process steps and opening enlarging process steps are then performed in an alternating manner until the trench has been etched to a desired depth. The method permits very deep tapered trenches of up to 80-100 um or more to be formed in a silicon substrate or other layer of material in a highly controllable manner. The method can be incorporated into processes for manufacturing numerous devices including MEMS devices and high power RF devices such as LDMOS and VDMOS devices.

Abstract: A microelectronic device fabricating method includes providing a substrate having a beveled portion and forming a layer of structural material on the beveled portion. Some of the structural material can be removed from the beveled portion by anisotropic etching to form a device feature from the structural material. The device feature can be formed on the beveled portion as with a pair of spaced, adjacent barrier material lines that are substantially void of residual shorting stringers extending therebetween. Structural material can be removed from the beveled portion to form an edge defined feature on a substantially perpendicular edge of the substrate. The beveled portion and perpendicular edge can be part of a mandril. The mandril can be removed from the substrate after forming the edge defined feature.

Abstract: A thin film transistor is provided that includes a substrate, a gate electrode formed on the substrate, and a gate insulating layer formed all over the substrate including the gate electrode. A first semiconductor layer is formed on the gate insulating layer, and a second semiconductor layer is formed on the first semiconductor layer. Source and drain electrodes are separately etched together to expose a prescribed portion surface of the second semiconductor layer over the gate electrode. The source and drain electrodes adjacent to the prescribed portion of the second semiconductor layer are non-linearly inclined at their edges. A method of fabricating a thin film transistor includes forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode and the substrate, forming a first semiconductor layer on the gate insulating layer and forming a second semiconductor layer on the first semiconductor layer.

Abstract: Disclosed is a method for forming a contact portion of a semiconductor element. An exemplary method includes the steps of depositing an insulation layer on a lower thin film on which there is formed a semiconductor element electrode or a metal wiring pattern, and then realizing an even upper surface of the insulation layer; forming a photosensitive film pattern thereon having a contact or via hole pattern in which inner walls of the contact holes or via holes smoothly curve downward to reach an upper surface of the insulation layer; dry-etching the insulation layer using a mask following the photosensitive film pattern to form contact holes or via holes; removing the photosensitive film pattern, then depositing a barrier metal and tungsten to fill the contact holes or the via holes; and performing a chemical mechanical polishing process to remove the barrier metal and the tungsten from the upper surface of the semiconductor element until the insulation layer is exposed and a flat surface is realized.

Abstract: A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation. The enhanced vias are useful in a wide variety of semiconductor devices, including SRAMS and DRAMs.

Abstract: A method of performing a shallow trench isolation etch in a silicon layer of a layer stack is disclosed. The layer stack includes a silicon layer being disposed below a pad oxide layer, the pad oxide being disposed below a nitride layer, and the nitride layer being disposed below a photoresist mask. The etching takes place in a plasma processing chamber. The method includes flowing a first etchant source gas into the plasma processing chamber, forming a first plasma from the first etchant source gas, and etching through the nitride layer with the first plasma. The method further includes flowing a second etchant source gas into the plasma processing chamber, forming a second plasma from the second etchant source gas, and substantially removing the photoresist mask with the second plasma, wherein a substantial portion of the photoresist mask is removed from above the nitride layer before the silicon layer.

Abstract: The present invention provides a semiconductive substrate which includes front and back surfaces and a hole which extends through the substrate and between the front and back surfaces. The hole is defined in part by an interior wall portion and forms an outer conductive sheath. Conductive material is formed proximate at least some of the interior wall portion. Subsequently, a layer of dielectric material is formed within the hole, over and radially inwardly of the conductive material. A second conductive material is then formed within the hole over and radially inwardly of the dielectric material layer. The latter conductive material constitutes an inner conductive coaxial line component.

Abstract: A light absorbing layer composed of intentionally undoped n-type InGaAs and a window layer composed of intentionally undoped n-type InP are formed sequentially on a first principal surface of a semiconductor substrate composed of n-type InP. A cathode is provided on a p-type diffused region forming an island pattern in the window layer, while an anode is provided on a second principal surface of the semiconductor substrate. A side edge portion of the second principal surface of the semiconductor substrate is formed with a gradient portion having an exposed surface with a (112) plane orientation and forming an angle of 35.3° with respect to the second principal surface. The gradient portion is formed to have a mirrored surface by using an etching solution containing hydrochloric acid and nitric acid at a volume ratio of approximately 5:1 to 3:1.

Abstract: There is provided a method of fabricating a semiconductor memory device including a memory cell having transistor and a capacitor, and a cylindrical accumulation electrode, the method including the steps of (a) forming a first insulating film on a lower interlayer insulating film, (b) forming at least one hole through the first insulating film so that the hole reaches the lower interlayer insulating film, (c) forming a polysilicon layer in the hole so that an upper surface of the polysilicon layer is located lower than an upper surface of the first insulating film, (d) covering the first insulating film and the polysilicon layer with a second insulating film, (e) etching back the second insulating film so that the second insulating film remains only on a sidewall of the first insulating film, and (f) etching the polysilicon layer with the second insulating film being used as a mask so that the polysilicon layer has a thickness different from a thickness of the first insulating film after the polysilicon layer

Abstract: A method for fabricating a MIM capacitor of a MDL logic or analog circuit of a semiconductor device. A conductivity layer is formed on a semiconductor substrate having a first inter-level insulating layer. A capping metal layer having an etching rate higher than an oxide layer is formed on the conductivity layer. A lower electrode comprising a “conductivity layer/capping metal layer” deposition is formed by selectively etching the capping metal layer and the conductivity layer in order to expose a predetermined part of the surface of the first inter-level insulating layer. A second inter-level insulating layer is formed on the first inter-level insulating layer covering the lower electrode. A via hole is formed by selectively etching both the second inter-level insulating layer and the lower electrode thereby to expose a portion of the lower electrode so that a tapered capping metal layer remains along the lower edges of the via hole.

Abstract: A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming grooves of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing the grooves formed on the semiconductor substrate in the range of 0<C≦0.88t-924 in which the oxidizing atmosphere is dry oxidation (H2/O2≈0), the oxygen partial pressure in the air corresponding to the oxygen partial pressure ratio is C %, and the oxidizing temperature is t (° C.

Abstract: An improved apparatus and method for manufacturing semiconductor devices, and, in particular, for depositing material at the bottom of a contact hole, comprises sputtering a material onto a semiconductor substrate; applying a first bias voltage to the substrate, simultaneously removing the material surrounding the contact hole to form a facet at the top of the recess; and applying a second bias voltage to the substrate, simultaneously sputter-depositing the first material onto the bottom of the recess. A further embodiment of the invention utilizes an electrically isolated collimator for the sputtering apparatus. Another embodiment of the invention resputters a first material onto sidewalls of a contact hole during physical vapor deposition.

Abstract: A method for fabricating a Y-gate structure is provided. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second sacrificial layer over the first sacrificial layer. An inwardly sloping opening is formed in the second sacrificial layer and the opening is extended vertically in the first sacrificial layer. A contact material is deposited over the second sacrificial layer filling the opening with the contact material and forming a contact layer and portions of the contact material outside a gate region are removed. The first sacrificial layer and the second sacrificial layer are then removed.

Abstract: An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer, forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles, and implanting the semiconductor substrate with a dopant to penetrate portions of the sidewalls to form one or more graded shallow junctions with gradual doping profiles.

Abstract: A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming grooves of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing the grooves formed on the semiconductor substrate in the range of 0<C≦0.88t−924 in which the oxidizing atmosphere is dry oxidation (H2/O2≈0), the oxygen partial pressure in the air corresponding to the oxygen partial pressure ratio is C %, and the oxidizing temperature is t (° C.

Abstract: On a transparent substrate, on which is positioned a gate electrode, a silicon nitride film and a silicon oxide film are formed as gate insulating films, and furthermore a polycrystalline silicon film is formed as a semiconductor film to become an active region. A stopper is positioned on the polycrystalline silicon film to correspond to a gate electrode, and a silicon oxide film, a silicon nitride film, and a silicon oxide film are formed as interlayer insulating film so as to cover the stopper. Contact holes are formed in the layer insulating film to correspond to a source region and a drain region, and a source electrode and a drain electrode are positioned through these contact holes.

Abstract: Methods for fabricating a free-standing thin metal film are provided. In one method, a sacrificial silicon nitride membrane structure is provided comprising a silicon wafer having first and second surfaces, a first silicon nitride layer applied to the first surface of the silicon wafer and a second silicon nitride layer applied to the second surface of the silicon wafer. The second silicon nitride layer and the silicon wafer are etched to provide a window that exposes a predetermined area of the first silicon nitride layer, whereby the exposed predetermined area of the front silicon nitride layer comprises a sacrificial silicon nitride membrane unsupported by any auxiliary substrate over the predetermined area. A thin metal film is then deposited on the first silicon nitride layer. Finally, the sacrificial silicon nitride membrane is removed, whereby the portion of the thin metal film exposed by the removal of the silicon nitride membrane comprises the free-standing thin metal film.

Abstract: There is provided a technique of connecting easily the lead terminal to the board of the module. A plurality of clip lead terminals each has at one end thereof clip portions which are connected electrically to connecting terminals by sandwiching an end portion of a board of a module and the connecting terminals formed thereon between clip members of said clip portions and has a lead portion at the other end thereof. The clip lead terminals are arranged so as to be spaced from one another in parallel with one another with the leading edges of the respective clip portions aligned on a straight line. The clip lead terminals are connected to one another through a tie bar and a guide as a connecting portion, respectively, whereby the connecting clip lead terminal 18 is formed as one-body. The lead portions are bent on every other one, leading end portions of the bent lead portions and leading end portions of the non-bent lead portions are in parallel with each other viewing from a side of the board.

Abstract: Under the first embodiment of the invention, a three layer composite layer of insulation is deposited. The trench is etched into this composite layer of insulation followed by a hard bake. The via etch is performed, completing the formation of the dual damascene profile. The created dual damascene profile is transferred into the underlying substrate; the layer of photoresist is removed. Under the second embodiment of the invention, a two layer composite layer of insulation is deposited over a semiconductor surface. The trench is etched into this composite layer of insulation. A layer of positive photoresist is deposited over the second layer of cross-linked negative resist and masked for the via etch. The via etch is performed, the created dual damascene profile is transferred into the underlying substrate. The removal of the layers of patterned photoresist completes the formation of the dual damascene structure.

Abstract: A method of manufacturing a semiconductor device with high reliability is provided in which an insulating property of an insulating layer is high and connection failure is prevented. The semiconductor device includes: a silicon substrate; a low-temperature aluminum film formed on silicon substrate and including a polycrystal; and a high-temperature aluminum film. An opening is formed in a surface of a high-temperature aluminum film by a crystal grain boundary. A distance between side walls of the opening becomes small as closer to silicon substrate.

Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions. Likewise, the present invention provides a method for fabricating a semiconductor component containing this semiconductor insulation layer.

Abstract: A method for forming a shallow trench isolation used to isolate a device is provided. A pad oxide and a mask layer are formed on a substrate and patterned. A trench is formed within the substrate under the patterned region and the trench is filled with insulator to form an insulation plug, which is a shallow trench isolation. A dielectric layer is formed on the whole substrate surface to cover the device region and the insulation plug.

Abstract: A method is provided to form a split-gate flash memory not susceptible to inadvertent reverse tunneling during programming. This is accomplished by forming a silicon nitride spacer on the negatively tapered walls of the floating gate of the cell which serves as a barrier to reverse tunneling. The negatively tapered walls, in contrast to vertical walls, is disclosed to provide a geometry better suited for forming thicker spacers around the floating gate, which in turn serve to act as a more robust barrier to reverse tunneling. Furthermore, it is shown that the method requires fewer steps than practiced in prior art.

Abstract: In order to provide a method for manufacturing a semiconductor device in which, in a trench isolation process of the semiconductor device, any void is not formed in trenches and a repeating pitch of the trench isolation can be reduced to the limitations of a lithography technique, the method of the present invention comprises, in the trench isolation process, a step of etching a silicon substrate through a hard mask to form trenches, and a step of processing the hard mask so that its upper portion may be tapered.

Abstract: A semiconductor device and a manufacturing method for a hyperfine structure wherein contact of a gate electrode with a side-wall composed of a silicon nitride layer within a contact hole due to an alignment deviation may be prevented. The semiconductor device is structured such that the contact hole is formed in an inter-layer insulating layer and the side-wall is formed along a wall surface within the contact hole. A bottom of the side-wall is composed of a silicon oxide layer or a silicon oxide nitride layer, and an upper portion of the side-wall is formed of a silicon nitride layer.

Abstract: A post-etch structure resulting in the inverse of a sidewall spacer etch, i.e. removal of the spacer. A vertical portion of a film is removed while leaving horizontal portions substantially intact. A facet is left in the film in register with an upper corner formed by the vertical and horizontal portions of the underlying body.

Abstract: There is provided a method for fabricating a semiconductor device, by which passivation layers are formed with good step coverage to prevent crack or void from being occurred in high aspect ratio of metallization layers and the time for performing the processes can be decreased to enhance the productability and the yield of the device. The method is performed as follows. Over a substrate having completed metallization layers, an oxide layer is formed as a first passivation layer by high-density plasma chemical vapor deposition (HDP-CVD). On the HDP-CVD oxide layer, a nitride layer is formed as a second passivation layer by plasma enhanced chemical vapor deposition (PECVD) or HDP-CVD.

Abstract: A method for forming a shallow trench isolation structure. A mask layer having an opening is formed over a substrate to pattern a shallow trench. A sloped spacer is formed on the sidewalls of the opening. The mask layer and the spacer are used as a hard mask, and a portion of the substrate is removed by anisotropic etching to form a shallow trench isolation structure. The sloped sidewalls of the shallow trench isolation structure and the substrate surface intersect at an obtuse angle. Therefore, the structure prevents stress and avoids leakage current.

Abstract: A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; and siliciding the top surfaces of the source and drain regions.

Abstract: A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; and siliciding the top surfaces of the source and drain regions.

Abstract: Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle with of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier.

Abstract: A semiconductor device having shallow junctions is provided by providing a semiconductor substrate having source and drain regions and polysilicon gate regions; depositing selective silicon on the source and drain regions; providing dopant into the source and drain regions forming shallow junctions; forming first insulating spacers on sidewalls of the gate regions; forming second insulating sidewall spacers on the first insulating spacers; and siliciding the top surfaces of the source and drain regions and polysilicon gate regions.

Abstract: In a semiconductor single crystalline substrate provided with a protecting film to prevent autodoping on the reverse surface thereof, for growing a vapor-phase epitaxial layer on the main obverse surface thereof, a width of a chamfer is set for locating an edge-crown occurred in consequence of a vapor-phase epitaxial growth on the chamfer, and a gap of a distance is formed between a periphery of the protecting film and an innermost part of the chamfer on the reverse surface.