Forming Tapered Edges On Substrate Or Adjacent Layers Patents (Class 438/978)
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Patent number: 5981397Abstract: A method of forming integrated circuitry includes, a) providing a pair of spaced and adjacent electrically conductive elongated lines; and b) providing electrically insulative material over the pair of spaced lines in a manner which leaves an elongated void between the lines, the elongated void being top sealed along its substantial elongated length. Preferably, the electrically insulative material is provided by depositing electrically insulative material over the pair of lines in a manner which produces a retrograde cross-sectional profile of the insulating material relative to the respective line sidewalls and which leaves an elongated top sealed void within the insulating material between the lines, the elongated void being open at at least one end. The void at the one end is subsequently sealed.Type: GrantFiled: November 4, 1998Date of Patent: November 9, 1999Assignee: Micron Technology, Inc.Inventor: Monte Manning
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Patent number: 5966615Abstract: A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.Type: GrantFiled: February 17, 1998Date of Patent: October 12, 1999Assignee: Micron Technology, Inc.Inventors: Pierre C. Fazan, Martin C. Roberts, Gurtej S. Sandhu
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Patent number: 5966588Abstract: An improved field emission display device fabrication method which adopts both a silicon wafer direct bonding method and a mold method so as to fabricate an improved field emission display device, which includes the steps of a first step which forms a tip array by a molding method; and a second step which bonds the tip array to a second semiconductor substrate.Type: GrantFiled: April 4, 1996Date of Patent: October 12, 1999Assignee: Korea Institute of Science and TechnologyInventors: Byeong Kwon Ju, Myung Hwan Oh, Yun Hi Lee, Nam Yang Lee
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Patent number: 5937309Abstract: A method for fabricating a shallow trench isolation (STI) structure in a semiconductor substrate. A stop layer is formed on the substrate and a first sacrificial layer is formed on the stop layer. The first sacrificial layer and the stop layer are defined to form an opening on the substrate. A conformal second sacrificial layer with rounded corners is formed on the substrate. The second sacrificial layer, the first sacrificial layer, and a portion of the substrate are anisotropically removed to form a trench in the substrate using the stop layer as a removal stop layer. The substrate is over removed using the stop layer as a mask layer so that spacers of the second sacrificial layer are remained on the substrate to cover portions of sidewalls of the stop layer.Type: GrantFiled: February 1, 1999Date of Patent: August 10, 1999Assignee: United Semiconductor Corp.Inventor: Shu-Ya Chuang
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Patent number: 5933749Abstract: A method for removing the top corner of the trench is disclosed. After the formation of an oxide layer and then a nitride layer over a substrate, a portion of the nitride layer, the oxide layer and the substrate are removed to form a trench. A mask is next formed on the nitride layer, wherein the opening of the mask is larger than the corresponding trench. A dry etching is performed to etch the exposed nitride layer and the substrate, using said mask. After removing the mask and the nitride layer, a liner oxide layer is then formed. The dry etching process removes the top corner to form a grading corner which consequently avoids charge accumulation and point discharging.Type: GrantFiled: December 30, 1997Date of Patent: August 3, 1999Assignee: United Microelectronics Corp.Inventor: Tzung-Han Lee
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Patent number: 5932490Abstract: A method of forming integrated circuitry includes, a) providing a pair of spaced and adjacent electrically conductive elongated lines; and b) providing electrically insulative material over the pair of spaced lines in a manner which leaves an elongated void between the lines, the elongated void being top sealed along its substantial elongated length. Preferably, the electrically insulative material is provided by depositing electrically insulative material over the pair of lines in a manner which produces a retrograde cross-sectional profile of the insulating material relative to the respective line sidewalls and which leaves an elongated top sealed void within the insulating material between the lines, the elongated void being open at at least one end. The void at the one end is subsequently sealed.Type: GrantFiled: July 22, 1997Date of Patent: August 3, 1999Assignee: Micron Technology, Inc.Inventor: Monte Manning
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Patent number: 5933715Abstract: A process for manufacturing discrete electronic devices with active structures in an SOI (silicon-on-insulator) substrate which is thickened by an epitaxial layer and whose surface has a <100> orientation, said process comprising the steps of: anisotropically etching the first silicon layer to form a moat having a diameter tapering in the direction of the insulator layer, said moat extending to the insulator layer; forming an insulating layer on the sidewalls of the moat; removing a portion of the insulator layer adjoining the moat to expose a portion of the second silicon layer, which is separated from the first silicon layer by the insulator layer; forming the active structure in the second silicon layer below the portion of the insulator layer which was removed; and depositing a contact layer on the insulating layer and the active element for making contact to the active structure.Type: GrantFiled: March 7, 1997Date of Patent: August 3, 1999Assignee: Micronas Intermetall GmbHInventors: Gunter Igel, Ruediger Joachim Stroh
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Patent number: 5920781Abstract: A semiconductor device with a longer channel length is made by first forming an insulating film over a semiconductor substrate, next forming on this insulating film an electrode having a main part and side parts which are thinner than the main part and may each have a tapered surface, then doping a surface of the semiconductor substrate by using the electrode as a mask and by ion-implanting impurities towards surfaces of the insulating film and the electrode through these side parts, and carrying out an annealing process and thereby causing the impurities to diffuse.Type: GrantFiled: October 16, 1997Date of Patent: July 6, 1999Assignee: Rohm Co., Ltd.Inventor: Shinya Imoto
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Patent number: 5895937Abstract: A method of etching openings in a dielectric layer of a semiconductor device by utilizing a novel etchant gas system of sulfur hexafluoride/chlorine such that sloped sidewalls can be formed in the openings having a desired taper of between about 20.degree. and about 85.degree. for achieving improved step coverage and profile control of the TFT fabrication process.Type: GrantFiled: October 21, 1997Date of Patent: April 20, 1999Assignee: Applied Komatsu Technology, Inc.Inventors: Yuh-Jia (Jim) Su, Yuen-Kui (Jerry) Wong, Kam S. Law, Haruhiro (Harry) Goto
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Patent number: 5895271Abstract: A metal film forming method by which a metal film having a desired pattern can be formed with good reproducibility and satisfactory precision. In a metal film forming method for forming a metal film into the desired pattern on a surface of an object by the lift-off method, a resist layer is laminated on the surface of the object, the resist layer is exposed to light with the desired pattern and it is developed. Radio frequency sputtering is then performed against the resist layer so that the opening is deformed into a shape which is suited for the lift-off process. A metal film is then laminated on the surfaces of the resist layer and the metal film forming object. Then the resist layer is subjected to lift-off processing, whereby the metal film can be formed with good precision and satisfactory reproducibility. In this way, such a metal film forming method can be realized that a metal film having the desired pattern can be formed with good reproducibility and satisfactory precision.Type: GrantFiled: December 27, 1995Date of Patent: April 20, 1999Assignee: Sony CorporationInventors: Kiyoshi Hasegawa, Hiroshi Ozaki
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Patent number: 5882488Abstract: An improved apparatus and method for manufacturing semiconductor devices, and, in particular, for depositing material at the bottom of a contact hole, comprises sputtering a material onto a semiconductor substrate; applying a first bias voltage to the substrate, simultaneously removing the material surrounding the contact hole to form a facet at the top of the recess; and applying a second bias voltage to the substrate, simultaneously sputter-depositing the first material onto the bottom of the recess. A further embodiment of the invention utilizes an electrically isolated collimator for the sputtering apparatus. Another embodiment of the invention resputters a first material onto sidewalls of a contact hole during physical vapor deposition.Type: GrantFiled: February 26, 1998Date of Patent: March 16, 1999Assignee: Micron Technology, Inc.Inventor: Shane P. Leiphart
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Patent number: 5883002Abstract: A contact opening formation process is disclosed for forming an opening having a positive base profile. This opening is formed by etching a pre-metal dielectric layer of an undoped oxide underlayer covered by a BPSG overlayer. The etching is performed using an etchant that etches the BPSG layer faster than the oxide underlayer. The etching solution is by weight at least 97.35% distilled water, 0.45% of HF and 2.2% of NH.sub.4 F.Type: GrantFiled: August 29, 1996Date of Patent: March 16, 1999Assignee: Winbond Electronics Corp.Inventors: Hsueh-Hao Shih, Jing-Hua Chiang
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Patent number: 5882982Abstract: A shallow trench isolation structure and method for forming such structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall sloping inwardly towards the center of a substantially planar bottom surface, and a second sidewall sloping inwardly towards the center of the substantially planar bottom surface. Additionally, a cross section of the trench has a first rounded bottom trench corner at an interface of the first sidewall and the substantially planar bottom surface, and a second rounded bottom trench corner at an interface of the second sidewall and the substantially planar bottom surface.Type: GrantFiled: January 16, 1997Date of Patent: March 16, 1999Assignee: VLSI Technology, Inc.Inventors: Jie Zheng, Calvin Todd Gabriel, Suzanne Monsees
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Patent number: 5880030Abstract: A high density, low capacitance, interconnect structure for microelectronic devices has unlanded vias formed with organic polymer intralayer dielectric material having substantially vertical sidewalls. A method of producing unlanded vias includes forming a planarized organic polymer intra-layer dielectric between conductors, forming an inorganic dielectric over the conductor and organic polymer layer, patterning a photoresist layer such that openings in the photoresist layer overlap portions of both the conductor and the intra-layer dielectric, etching the inorganic dielectric and then concurrently stripping the photoresist and anisotropically etching the organic polymer intra-layer dielectric. A second conductor is typically deposited into the via opening so as to form an electrical connection to the first conductor. A silicon based insulator containing an organic polymer can alternatively be used to form the intra-layer dielectric.Type: GrantFiled: November 25, 1997Date of Patent: March 9, 1999Assignee: Intel CorporationInventors: Sychyi Fang, Chien Chiang, David B. Fraser
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Patent number: 5880004Abstract: A method of providing isolation structure in a semiconductor device having a shallow trench with a rounded top corner is provided for preventing stress centralization as well as current leakage of a device.Type: GrantFiled: June 10, 1997Date of Patent: March 9, 1999Assignee: Winbond Electronics Corp.Inventor: Michael Ho
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Patent number: 5858857Abstract: A method of forming shallow trenches in a semiconductor substrate is provided. This method allows the thus-formed trenches to be shaped with a rounded top corner having a desired radius of curvature in accordance with actual requirements. From experiments, it is learned that the radius of curvature of the top corners of the trenches decreases linearly with the depth of a pre-trench formed by over-etching in the substrate. The relationship between radius of curvature and depth of pre-trench can be pre-established by experimentation. After that, the top corners of the shallow trenches in the substrate can be controlled to be shaped with a desired radius of curvature by adjusting the depth of the pre-trench based on the pre-established linear relationship.Type: GrantFiled: April 17, 1997Date of Patent: January 12, 1999Assignee: Winbond Electronics Corp.Inventor: Michael Ho
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Patent number: 5858865Abstract: Within an integrated circuit, a contact plug with a height not extending above the level of the gate/wordline nitride is nonetheless provided with a relatively large contact area or landing pad, significantly larger than the source/drain region to which the contact plug is electrically connected. Methods for producing the inventive contact plug include (1) use of a nitride facet etch, either (a) during a nitride spacer formation etch or (b) during a BPSG etch; (2) using at least one of (a) an isotropic photoresist etch or partial descum to narrow BPSG spacers above the gate/wordline nitride, and (b) a nitride step etch to etch the shoulder area of the gate/wordline nitride exposed by a BPSG etch; and (3) polishing a BPSG layer down to the top of a gate/wordline nitride before any doped polysilicon plug fill, masking for BPSG etch and performing a BPSG etch, etching the photoresist layer through a partial descum, and etching the shoulder area of the gate/wordline nitride exposed thereby.Type: GrantFiled: December 7, 1995Date of Patent: January 12, 1999Assignee: Micron Technology, Inc.Inventors: Werner Juengling, Kirk Prall, Gordon Haller, David Keller, Tyler Lowrey
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Patent number: 5858859Abstract: A device-isolating trench having a taper at its upper portion is formed in a silicon semiconductor substrate. Then, a silicon oxide film is formed on the inner wall of the trench and the surface of the semiconductor substrate near the trench by an oxidizing method, and polycrystalline silicon is buried in the trench.Type: GrantFiled: June 13, 1997Date of Patent: January 12, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Naoto Miyashita, Koichi Takahashi
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Patent number: 5858860Abstract: Isolated semiconductor devices are formed by forming field oxide regions in a face of a semiconductor substrate to define active regions therebetween. The field oxide regions extend to above the substrate face and include an oblique surface which extends from above the substrate face to the substrate face. A step reducing region is formed on a respective one of the oblique surfaces of the field oxide regions, extending onto the active regions at the substrate face. The step reducing region can reduce the steepness of the step between the substrate face and the field oxide regions, thereby facilitating further processing and reliability of the semiconductor devices.Type: GrantFiled: February 6, 1997Date of Patent: January 12, 1999Assignee: Samsung Electronics Co., Ltd.Inventors: Myoung-seob Shim, Won-taek Choi, Yun-seung Shin
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Patent number: 5854089Abstract: A semiconductor structure including: a substrate having a step portion; a first semiconductor layer formed on a region of the substrate which is selectively irradiated by light at an angle with respect to the projecting portion by using the step portion as a mask; and a second semiconductor layer formed on a region of the substrate shaded by the step portion.Type: GrantFiled: June 28, 1996Date of Patent: December 29, 1998Assignee: Sharp Kabushiki KaishaInventor: Hiroshi Nakatsu
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Patent number: 5807789Abstract: The present invention is a method for forming a shallow trench with tapered profile and round corners for the application of shallow trench isolation (STI). This invention utilizes a multiple-step dry etching process with reduced RF power and increased pressure to etch a shallow trench. This takes advantage of different degree of polymer deposition in different steps by varing the pressure and the RF power. Thus, a shallow trench with tapered profile and round corners is achieved.Type: GrantFiled: March 20, 1997Date of Patent: September 15, 1998Assignee: Taiwan Semiconductor Manufacturing, Co., Ltd.Inventors: Chao-Cheng Chen, C. S. Tsai, C. H. Yu
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Patent number: 5801083Abstract: A method for forming insulator filled, shallow trench isolation regions, with rounded corners, has been developed. The process features the use of a polymer coated opening, in an insulator layer, used as a mask to define the shallow trench region in silicon. After completion of the shallow trench formation the polymer spacers are removed, exposing a region of unetched semiconductor, that had been protected by the polymer spacers, during the shallow trench dry etching procedure. The sharp corner, at the intersection between the shallow trench and the unetched region of semiconductor, is then converted to a rounded corner, via thermal oxidation of exposed silicon surfaces. The polymer spacers also eliminate the top corner wraparound.Type: GrantFiled: October 20, 1997Date of Patent: September 1, 1998Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Bo Yu, Qing Hua Zhong, Jian Hui Ye, Mei Sheng Zhou
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Patent number: 5728608Abstract: A method of etching openings in a dielectric layer of a semiconductor device by utilizing a novel etchant gas system of sulfur hexafluoride/chlorine such that sloped sidewalls can be formed in the openings having a desired taper of between about 20.degree. and about 85.degree. for achieving improved step coverage and profile control of the TFT fabrication process.Type: GrantFiled: October 11, 1995Date of Patent: March 17, 1998Assignee: Applied Komatsu Technology, Inc.Inventors: Yuh-Jia (Jim) Su, Yuen-Kui (Jerry) Wong, Kam S. Law, Haruhiro (Harry) Goto
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Patent number: 5726100Abstract: A process is disclosed for forming interconnect channels and contact vias using a single mask. The interconnect channels are formed in an upper silicon dioxide dielectric layer, while the contact vias are formed in both the upper dielectric layer and a lower silicon dioxide dielectric layer. A primary silicon nitride etch stop layer is sandwiched between the upper dielectric layer and the lower dielectric layer, and an optional secondary silicon nitride etch stop layer is sandwiched between a subjacent conductive region and the lower dielectric layer. A contact via/interconnect channel photomask is formed on top of the upper dielectric layer. The critical dimension of the contact via openings is about twice the critical dimension of the interconnect channel openings. A reactive-ion etch, that is selective for silicon dioxide over silicon nitride is performed, exposing the primary etch stop layer in the contact via openings, but not along the length of the interconnect channels.Type: GrantFiled: June 27, 1996Date of Patent: March 10, 1998Assignee: Micron Technology, Inc.Inventor: John H. Givens
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Patent number: 5723371Abstract: A method for fabricating a thin film transistor having a taper-etched semiconductor film includes the steps of forming a gate electrode on a bare substrate; forming an insulating film on the gate electrode;p forming a semiconductor film by forming an amorphous silicon film layer on the insulating film and forming an N.sup.+ amorphous silicon film on the amorphous silicon film layer, descumming photoresist residue from the semiconductor film by using a specified gas and taper etching a part of the semiconductor film, which is uncoated with the photoresist, by using HCl and SF.sub.6, to form a gentle slope in the etching profile resulting from overetching.Type: GrantFiled: August 23, 1995Date of Patent: March 3, 1998Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Kap Seo, Chi-Woo Kim, Ho-Chul Kang
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Patent number: 5632854Abstract: A pressure sensor (11) and its method of fabrication include etching a V-groove (19) in a first surface (16) of a first substrate (12), bonding a second substrate (24) to the first substrate (12), thinning the second substrate (24) to form a diaphragm (32) overlying the V-groove (19), and etching a port (38) from the second surface (18) of the first substrate (12) to the V-groove (19). Tetra-methyl-ammonium-hydroxide is preferably used to anisotropically etch the V-groove (19), and an anisotropic plasma reactive ion etch is preferably used to etch the port (38).Type: GrantFiled: August 21, 1995Date of Patent: May 27, 1997Assignee: Motorola, Inc.Inventors: Andy Mirza, Ljubisa Ristic
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Patent number: 5633197Abstract: A new method of metallization using a new design of metal contact shape, contact/via profile, and metal lines having considerably reduced current density and improved electromigration of metal lines is achieved. Metal contacts are formed in a rectangular shape instead of a square shape with the wider side perpendicular to the current direction. Contact openings are made having concavo-concave profiles which can provide a wider conducting cross-sectional area than can conventional openings with a vertical profile near the contact bottom. Gaps are formed within wide and high current metal lines so that current density can be effectively lowered by utilizing the whole metal line uniformly.Type: GrantFiled: September 29, 1995Date of Patent: May 27, 1997Assignee: United Microelectronics CorporationInventors: Water Lur, Jiun Y. Wu
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Patent number: 5631174Abstract: A method for forming spacers having a prograde profile includes providing a semiconductor substrate having raised structures thereon having top and lateral surfaces. A layer of spacer material is then deposited conformably over the raised objects and the semiconductor substrate. A layer of compatible material having a lower viscosity at high temperature than the spacer material is then deposited conformably over the layer of spacer material. The layer of compatible material is then reflowed. The portions of the layer of spacer material and the layer of compatible material laterally enclosing the raised structures constitute spacers. The layer of compatible material is reflowed sufficiently to result in spacers having a prograde profile, i.e., to result in laterally outward facing surfaces of the spacers that slope laterally outward from the top surfaces of the raised objects downward.Type: GrantFiled: December 21, 1995Date of Patent: May 20, 1997Assignee: Micron Technology, Inc.Inventor: Ravi Iyer
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Patent number: 5629237Abstract: A method is described for forming tapered contact via holes in large scale integrated circuit structures which avoids the formation of a re-entrance profile. The re-entrance profile can form at the entrance to the contact via hole when a dry etch is used as a first etching step by redepositing material removed during the dry etch at the entrance of the contact via hole. This re-entrance profile makes the angle of entrance into the contact via hole greater than 90.degree. and the step coverage of metal filling the hole poor. This invention uses wet etching with a greater lateral etch rate than vertical etch rate as a first etching step in the formation of the contact via hole and avoids the formation of the re-entrance profile. The edges of the resulting contact via hole are smooth and the entrance angle into the contact via hole is substantially less than 90.degree.. The step coverage of metal later filling the contact via hole is substantially improved.Type: GrantFiled: October 19, 1995Date of Patent: May 13, 1997Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Pei-Jan Wang, Kuei-Lung Chou, Jiunn-Jyi Lin, Hsien-Wen Chang