Panel Member Having Planar Surface For Supporting Circuit And Parallel Surface For Supporting Second Circuit Patents (Class 439/47)
  • Patent number: 11602800
    Abstract: Systems and methods for applying solder to a pin. The methods comprising: disposing a given amount of solder on a non-wetable surface of a planar substrate; aligning the pin with the solder disposed on the non-wetable surface of the planar substrate; inserting the pin in the solder; and performing a reflow process to cause the solder to transfer from the planar substrate to the pin.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: March 14, 2023
    Assignee: EAGLE TECHNOLOGY, LLC
    Inventors: Michael T. De Roy, Phillip K. Nickel, Jay S. Nelson, Andres M. Gonzalez, William A. Marquart
  • Patent number: 8592881
    Abstract: An organic light emitting element includes an organic light emitting diode formed on a substrate, coupled to a transistor including a gate, a source and a drain and including a first electrode, an organic thin film layer and a second electrode; a photo diode formed on the substrate and having a semiconductor layer including a high-concentration P doping region, a low-concentration P doping region, an intrinsic region and a high-concentration N doping region; and a controller that controls luminance of light emitted from the organic light emitting diode, to a constant level by controlling a voltage applied to the first electrode and the second electrode according to the voltage outputted from the photo diode.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: November 26, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-gyu Lee, Byoung-deog Choi, Hye-hyang Park, Ki-ju Im
  • Patent number: 8262550
    Abstract: An apparatus and associated method is provided for forming a rod for use in the manufacture of cigarette filter elements. A continuous supply of a filter material is formed into a continuous filter rod by a rod-forming unit. An object insertion unit is configured to insert a plurality of first objects and a plurality of second objects into the continuous filter rod. A rod-dividing unit is configured to subdivide the continuous filter rod, at predetermined intervals along the longitudinal axis thereof, into a plurality of filter rod portions such that each filter rod portion includes at least one first object and at least one second object disposed therein, with the first objects being different from the second objects.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: September 11, 2012
    Assignee: R. J. Reynolds Tobacco Company
    Inventors: Vernon Brent Barnes, Robert William Benford, Timothy Frederick Thomas, Stephen Thomas Matthews, John Larkin Nelson, Travis Eugene Howard
  • Patent number: 7791185
    Abstract: An electrically conductive pin comprising a pin stern and a pin head attached to the pin stem. The pin head is adapted to be mounted onto a surface of a microelectronic substrate to support the pin stem. The pin head has an underside surface defining a continuous curve configured to allow gases to escape from a pin-attach solder region adjacent the underside surface.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: September 7, 2010
    Assignee: Intel Corporation
    Inventor: Mengzhi Pang
  • Publication number: 20080220623
    Abstract: The invention discloses a connector, which includes a first connecting unit, a second connecting unit, a third connecting unit, and a determining unit. Moreover, the first connecting unit is capable of being electrically connected to a first power source and/or a first data source; and the second connecting unit is capable of being electrically connected to a second power source and/or a second data source. Additionally, the determining unit is electrically connected to the first connecting unit and the second connecting unit respectively, for selectively outputting a data signal and/or a power signal based on a connecting status. Furthermore, the third connecting unit is electrically connected to the determining unit and an electronic device, for transmitting the data signal and/or the power signal from the determining unit to the electronic device.
    Type: Application
    Filed: January 15, 2008
    Publication date: September 11, 2008
    Inventor: Sea-Weng Young
  • Patent number: 7409052
    Abstract: An intercom adapter used for selecting optionally one of three popular in-place residential wiring systems, in which two switches, each with two circuit-selecting contacts provide four permutations for selecting a circuit compatible for the in-place residential wiring system, to thereby reduce inventory to only the one switch-operated adapter.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: August 5, 2008
    Inventors: Lawrence D. Schilsky, Alan Schilsky
  • Patent number: 7288430
    Abstract: An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a heteroepitaxial microstructure fabricated from such method.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: October 30, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technolgoies
    Inventors: Bruce Faure, Fabrice Letertre, Bruno Ghyselen
  • Patent number: 7172429
    Abstract: The present invention provides a semiconductor light emitting device where a spatial change in an In composition ratio is small within a plane of an active layer and device properties such as efficiency of light emission are excellent, and a manufacturing method thereof. An active layer having an InGaN quantum well structure is formed in such a manner that a ratio of a photoluminescence light emission intensity at 300 K to a photoluminescence light emission intensity at 5 K becomes 0.1 or less. The ratio of the photoluminescence light emission intensity reflects the degree of the spatial change in an In composition ratio in a quantum confined structure. In addition, a smaller value indicates a higher spatial uniformity in the In composition ratio. Therefore, there is greater spatial uniformity in the In composition ratio in the active layer, increasing the probability of radiative recombination of carriers occurring, by making the ratio of photoluminescence light emission intensity 0.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: February 6, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuyuki Tomita, Masayoshi Takemi, Akihito Ohno
  • Patent number: 7045817
    Abstract: The invention provides a TFT electrode structure and its manufacturing method that can prevent metal diffusion occurring in the fabrication of a TFT, and thereby reduce the risk of contamination of the chemical vapor deposition process due to metallic ion diffusion. The transparent pixel electrode is formed after the gate electrode metal so that the pixel transparent electrode can be used as a barrier layer to prevent metal diffusion under high temperature from the gate electrode metal to adjacent insulating layers or the active layer. Further, the method used to form the transparent pixel electrode is a low-temperature physical vapor deposition process, which affected less by the processing environment, and the transparent pixel electrode is a conductive layer that is not affected by metal diffusion.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: May 16, 2006
    Assignees: Taiwan TFT LCD Association, Chunghwa Picture Tubes, Ltd., Au Optronics Corp, Quanta Display Inc., Hannstar Display Corp, Chi Mei Optoelectronics Corp., Industrial Technology Research Institute, Toppoly Optoelectronics Corp.
    Inventors: Cheng-Chung Chen, Yu-Chang Sun, Yi-Hsun Huang, Chien-Wei Wu, Shuo-Wei Liang, Chia-Hsiang Chen, Chi-Shen Lee, Chai-Yuan Sheu, Yu-Chi Lee, Te-Ming Chu, Cheng-Hsing Chen
  • Patent number: 6804123
    Abstract: A computer mainframe includes a housing, a motherboard, an intermediate circuit board, and a supporting bracket. A CD-ROM and a hard disk are attached to upper and lower sides, respectively, of the intermediate circuit board to sequentially superpose on and electrically connect to the motherboard via various connecting terminals provided at specific positions on the upper and the lower side of the intermediate circuit board. With the vertically superposed architecture of the mainframe, no space-occupying flat cable is needed for wiring the mainframe, enabling the mainframe to have a largely reduced volume.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: October 12, 2004
    Assignee: King Young Technology Co., Ltd.
    Inventor: Wan Chen Cheng
  • Patent number: 6488551
    Abstract: A flat (horizontal) press-fit busbar terminal structure for use in junction boxes, power distribution boxes, and the like at vehicle wiring junctions. Instead of the usual vertical busbar terminal extending through one or more insulation plate layers to be connected to the vertical terminals of a pluggable component, flat press-fit terminals are fastened in horizontal, essentially flush fashion to the surfaces of the flat insulation plates, with horizontally disposed terminal ends for receiving pluggable component terminals therethrough in perpendicular fashion. The flat terminals of the invention greatly reduce the overall height of the junction box, PDB, etc., thereby allowing the vertical component terminals to be used in place of peripheral jumper connections to interconnect one or more layers of busbar terminals.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: December 3, 2002
    Assignee: Yazaki North America
    Inventors: Jeromy William Tomlin, Roderick Rhys Jenkins, Jerome Adam David Duhr
  • Patent number: 6415504
    Abstract: A method for altering a circuit pattern of a printed-circuit board includes the steps of removing a portion of the printed-circuit board so that the circuit pattern inside the printed-circuit board is exposed, and connecting an exposed portion of the circuit pattern to another portion of the printed-circuit board by a conductive body so that a circuit path is formed between the exposed portion of the circuit pattern and the other portion of the printed-circuit board.
    Type: Grant
    Filed: September 9, 1996
    Date of Patent: July 9, 2002
    Assignee: Fujitsu Limited
    Inventor: Shinji Matsuda
  • Patent number: 5768106
    Abstract: A layered circuit-board designing method and layered circuit-board where circuit-boards to be overlaid are connected at the center or an arbitrary position of each circuit-board. The layered circuit-board includes an upper-layer first circuit-board, a lower-layer third circuit-board, and an intermediate-layer second circuit-board between the first and third circuit-boards. A first connector is mounted on the first circuit-board, a second connector is mounted on the third circuit-board, a third connector is mounted on the top surface of the second circuit-board, while maintaining the positional relation between the third connector and the first connector, and a fourth connector is mounted on the bottom surface of the second circuit-board, while maintaining the positional relation between the fourth connector and the second connector. In addition, through holes are provided at pins of the third and fourth connectors for passing through the front and bottom surfaces of the second circuit-board.
    Type: Grant
    Filed: June 11, 1996
    Date of Patent: June 16, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventor: Akira Ichimura
  • Patent number: 5610801
    Abstract: A motherboard assembly which has an integrated circuit socket that can be mated with either a single integrated circuit package or a multiple integrated circuit package module. The motherboard has a socket connector which can receive the external pins of an integrated circuit package. The motherboard also has an auxiliary connector that can mate with a corresponding connector-mounted to a daughterboard. Mounted to the daughterboard are a first integrated circuit package and a second integrated circuit package. Each package may contain a multi-processing microprocessor. The first integrated circuit package has a plurality of pins that mate with the socket connector. The daughterboard can be coupled to the motherboard by pressing the external pins of the first integrated circuit package into the socket connector and mating the auxiliary connectors. The present invention allows a plurality of processors to be plugged into a single socket without occupying a significant amount of space on the motherboard.
    Type: Grant
    Filed: November 15, 1995
    Date of Patent: March 11, 1997
    Assignee: Intel Corporation
    Inventor: Glenn Begis
  • Patent number: 5530625
    Abstract: An interface board for use, for example, in a motor vehicle to provide electrical interconnection between a plurality of electrical circuit control elements and a wiring harness. The board comprises a box structure including a plurality of circuit outlets on the upper face of the structure for plug in receipt of the electrical circuit control elements, a plurality of power outlets on a lower face of the structure for plug in receipt of electrical power input and output elements, and a series of electrical paths extending between the power outlets and a circuit control outlets. Each electrical path includes a first conductor extending generally parallel to the first and second faces and second conductors extending generally perpendicular to the first and second faces. The first conductors comprise flat ribbon elements and the second conductors comprise flat ribbon elements connected to the flat sides of the first conductors utilizing clinch joints.
    Type: Grant
    Filed: September 7, 1994
    Date of Patent: June 25, 1996
    Assignee: Electro-Wire Products, Inc.
    Inventors: Allen VanDerStuyf, Dewey Mobley, James P. Burgess
  • Patent number: 5515241
    Abstract: Assemblies and methods for interconnecting integrated circuits, particularly prepackaged ones, are disclosed. A multi-level electrical assembly--composed of a pin carrier, a set of pads, such as for receiving a surface-mounted integrated circuit, and a set of conductive pathways coupling the pads and the pins--can connect one or more integrated circuits to the socket or other attachment area of a circuit board. The pathways pass through a multi-layered interconnect board, which can be configured to permit any translation of pads to pins for different purposes, or to permit the coupling of additional circuit elements, such as a coprocessor or passive circuits, to the pathways. Inventive methods for forming the assemblies, and inventive systems in which the embodiment of the assembly can be used to increase circuit board density, are also disclosed.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 7, 1996
    Assignee: Interconnect Systems, Inc.
    Inventor: William E. Werther
  • Patent number: 5513077
    Abstract: An arrangement for a motor vehicle for central connection of electrical components, the arrangement comprises a housing, a plurality of supply circuits and control circuits, a plurality of circuit straps punched out of metal sheets and printed circuit boards, the supply circuits and the control circuits being formed so that the supply circuits are formed exclusively from the punched circuit straps and the control circuits are formed exclusively from the printed circuit boards, the printed circuit boards with the punched circuit straps and their intermediate insulations being assembled in a plurality of layers in a substantially identical surface configuration to form a printed circuit pack.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: April 30, 1996
    Assignee: Stribe GmbH
    Inventor: Hans P. Stribel
  • Patent number: 5513076
    Abstract: Assemblies and methods for interconnecting integrated circuits, particularly prepackaged ones, are disclosed. A multi-level electrical assembly--composed of a pin carrier, a set of pads, such as for receiving a surface-mounted integrated circuit, and a set of conductive pathways coupling the pads and the pins--can connect one or more integrated circuits to the socket or other attachment area of a circuit board. The pathways pass through a multi-layered interconnect board, which can be configured to permit any translation of pads to pins for different purposes, or to permit the coupling of additional circuit elements, such as a coprocessor or passive circuits, to the pathways. Inventive methods for forming the assemblies, and inventive systems in which the embodiment of the assembly can be used to increase circuit board density, are also disclosed.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 30, 1996
    Assignee: Interconnect Systems, Inc.
    Inventor: William E. Werther
  • Patent number: 5481436
    Abstract: Assemblies and methods for interconnecting integrated circuits, particularly prepackaged ones, are disclosed. A multi-level electrical assembly--composed of a pin carrier, a set of pads, such as for receiving a surface-mounted integrated circuit, and a set of conductive pathways coupling the pads and the pins--can connect one or more integrated circuits to the socket or other attachment area of a circuit board. The pathways pass through a multi-layered interconnect board, which can be configured to permit any translation of pads to pins for different purposes, or to permit the coupling of additional circuit elements, such as a coprocessor or passive circuits, to the pathways. Inventive methods for forming the assemblies, and inventive systems in which the embodiment of the assembly can be used to increase circuit board density, are also disclosed. The interconnect board can have layers assigned to specific voltages, in a power-translation design.
    Type: Grant
    Filed: October 18, 1994
    Date of Patent: January 2, 1996
    Assignee: Interconnect Systems, Inc.
    Inventor: William E. Werther
  • Patent number: 5481435
    Abstract: Assemblies and methods for interconnecting integrated circuits, particularly prepackaged ones, are disclosed. A multi-level electrical assembly--composed of a pin carrier, a set of pads, such as for receiving a surface-mounted integrated circuit, and a set of conductive pathways coupling the pads and the pins--can connect one or more integrated circuits to the socket or other attachment area of a circuit board. The pathways pass through a multi-layered interconnect board, which can be configured to permit any translation of pads to pins for different purposes, or to permit the coupling of additional circuit elements, such as a coprocessor or passive circuits, to the pathways. Inventive methods for forming the assemblies, and inventive systems in which the embodiment of the assembly can be used to increase circuit board density, are also disclosed.
    Type: Grant
    Filed: July 22, 1994
    Date of Patent: January 2, 1996
    Assignee: Interconnect Systems, Inc.
    Inventor: William E. Werther
  • Patent number: 5479319
    Abstract: Assemblies and methods for interconnecting integrated circuits, particularly prepackaged ones, are disclosed. A multi-level electrical assembly--composed of a pin carrier, a set of pads, such as for receiving a surface-mounted integrated circuit, and a set of conductive pathways coupling the pads and the pins--can connect one or more integrated circuits to the socket or other attachment area of a circuit board. The pathways pass through a multi-layered interconnect board, which can be configured to permit any translation of pads to pins for different purposes, or to permit the coupling of additional circuit elements, such as a coprocessor or passive circuits, to the pathways. Inventive methods for forming the assemblies, and inventive systems in which the embodiment of the assembly can be used to increase circuit board density, are also disclosed.
    Type: Grant
    Filed: December 30, 1992
    Date of Patent: December 26, 1995
    Assignee: Interconnect Systems, Inc.
    Inventor: William E. Werther
  • Patent number: 5430618
    Abstract: An adaptor includes an adaptor casing, a circuit board and a cover piece. The adaptor casing includes lower and upper casing halves which are made of plastic and which are coated entirely with a layer of conductive material. A circuit board is disposed in the adaptor casing and has a top surface provided with a switch unit that is aligned with an opening formed in the upper casing half and that extends out of the adaptor casing via the opening, a first edge provided with a first connector, and an opposite second edge provided with a second connector. Each of the first and second connectors has a support plate which closes a respective one of front and rear open ends of the adaptor casing. The support plates and the adaptor casing cooperatively form an enclosure for confining the circuit board therein. The cover piece is made of plastic and is coated entirely with a layer of conductive material. The cover piece is fitted detachably in the opening of the upper casing half.
    Type: Grant
    Filed: April 18, 1994
    Date of Patent: July 4, 1995
    Inventor: George Y. Huang
  • Patent number: 5426568
    Abstract: A launch-protected electronic assembly including a printed circuit board having several conductor paths. An electronic component is provided that is secured to the printed circuit board. The electronic component has several electrical connections each contacting a corresponding conductor path. The assembly further includes a support and at least one of a flexible adhesive layer and a dot-shaped flexible adhesive location connecting the printed circuit board to the support.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: June 20, 1995
    Assignee: Rheinmetall GmbH
    Inventors: Johannes Lamers, Norbert von der Lippe, Peter Sommer, Dietmar Stoffels
  • Patent number: 5418691
    Abstract: A printed circuit board device comprising at least two printed circuit boards in superposition to connect their interconnection patterns, and a positioning member for putting the two boards into registry when being superimposed, the positioning member including a hole provided in one of the boards, an extension provided on the other board and arranged to be inserted into the hole, and a pair of marks for position registry provided on the respective boards.
    Type: Grant
    Filed: November 18, 1992
    Date of Patent: May 23, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventor: Go Tokura
  • Patent number: 5365407
    Abstract: A DC power supply device for use with a video tape recorder with a built-in camera has a plurality of power supply blocks for supplying a plurality of voltages, each of the power supply blocks being composed of a switching circuit for being supplied with a DC voltage and a smoothing circuit connected to an output terminal of the switching circuit. The power supply blocks are mounted on a multilayer circuit board which includes a layer of a ground pattern with an electric conductor extending substantially fully thereover, the ground pattern being separated into a plurality of ground pattern portions by a plurality of recesses defined therein, the power supply blocks having respective ground terminals connected to the ground pattern portions, respectively.
    Type: Grant
    Filed: January 27, 1993
    Date of Patent: November 15, 1994
    Assignee: Sony Corporation
    Inventors: Toshiya Nakabayashi, Hirokazu Nakayoshi, Kazuo Hashimoto
  • Patent number: 5337219
    Abstract: A method for altering an electrical connection in an electronic package including one or more semiconductor chips overlying, i.e., mounted directly onto, or mounted onto one or more modules which are mounted onto, a substrate such as a printed circuit card or printed circuit board, as well as the resulting electronic package, is disclosed. In accordance with a preferred embodiment of the inventive method, at least one plated, solder-filled hole in the substrate is drilled out to eliminate an unwanted electrical connection. A solder region, e.g., a solder ball, is inserted into the drilled out hole into contact with an electrically conductive member, e.g., an electrically conductive pin, extending from, for example, a module into the hole. A cylinder, including a central core of electrically conductive material, encircled by an annulus of electrically insulating material, is inserted into the hole.
    Type: Grant
    Filed: June 24, 1991
    Date of Patent: August 9, 1994
    Assignee: International Business Machines Corporation
    Inventors: Dennis C. Carr, Edward P. McLeskey, Frank H. Sarnacki
  • Patent number: 5329428
    Abstract: Packaging for an electronics assembly. A base card has a row of elongated slots. A number of individually insertable subassemblies have standoff feet and a pair of offset hooks at their sides. The hooks snap into the slots in such a way that each slot can hold the hooks for four different subassemblies, which are positioned adjacent each other and on both sides of the base card.
    Type: Grant
    Filed: June 21, 1993
    Date of Patent: July 12, 1994
    Assignee: International Business Machines Corporation
    Inventors: Timothy R. Block, David P. Gaio, Ronald L. Soderstrom
  • Patent number: 5213521
    Abstract: A high frequency electrical connector assembly comprises first and second intermatable connectors including first and second intermatable housings, respectively, containing first and second board assemblies each comprising a series of conductive and insulating dielectric layers located alternately in overlying relation and extending transversely of a mating direction. Intermatable ground contacts extend between and interconnect all the conductive layers of respective board assemblies thereby forming ground planes, and, a first and second series of signal contacts having intermatable portions and anchoring portions extending through the respective board assemblies. The respective conductive layers extend to locations adjacent and spaced from the anchoring portions so that mating portions of the connector assembly are shieldingly enclosed between the board assemblies when the connectors are mated. The ground contacts are mating pin and socket portions or intermatable metal portions of the respective housings.
    Type: Grant
    Filed: January 22, 1992
    Date of Patent: May 25, 1993
    Assignee: Kel Corporation
    Inventor: Hiroshi Arisaka
  • Patent number: 5132879
    Abstract: A system of interconnecting electrical components having conflicting bonding requirements for mounting the components to a printed circuit board. The system includes a primary printed circuit board having a pattern of through-holes and having arrangements of connection sites to receive electrical components. For example, the connection sites of the primary printed circuit board may be of the type to receive components associated with the bonding requirements of surface mounting. A secondary printed circuit board has a pattern of through-holes corresponding to the pattern of through-holes of the primary printed circuit board. The circuit boards are wave soldered or surface mounted together by means of the corresponding patterns of through-holes. Attached to the secondary printed circuit board is one or more electrical component having bonding requirements which conflict with those of the primary printed circuit board.
    Type: Grant
    Filed: October 1, 1990
    Date of Patent: July 21, 1992
    Assignee: Hewlett-Packard Company
    Inventors: Cheng-Cheng Chang, Lawrence R. Hanlon
  • Patent number: 5102352
    Abstract: A high frequency electrical connector for an integrated circuit such as a microprocessor comprises a board assembly comprising a series of conductive and insulating layers of preselected thicknesses arranged alternately, one on top of the other, with conductive layers adjacent front and rear faces. Ground and current source pins are implanted in the layers with connecting portions for external circuitry outstanding from at least one of the faces and with conductive layer contacting portions establishing electrical connection with selected conductive layers. Ground pins connect the conductive layers adjacent the front and rear faces providing front and rear ground shield layers. The layers may be corrugated providing shielding portions extending in the direction of the pins. The thicknesses of the layers and the separation of the pins are preselected to provide pin impedances matching those of other connecting devices.
    Type: Grant
    Filed: January 17, 1991
    Date of Patent: April 7, 1992
    Assignee: Kel Corporation
    Inventor: Hiroshi Arisaka
  • Patent number: 5048166
    Abstract: Mounting only electronic parts on a printed circuit board puts a limit on the mounting density. According to the invention, electronic parts are mounted on a flexible board. This flexible board is then mounted on a printed circuit board to thereby increase the mounting density.
    Type: Grant
    Filed: April 6, 1990
    Date of Patent: September 17, 1991
    Assignee: Mitsubishi Denki K.K.
    Inventor: Chiharu Wakamatsu
  • Patent number: 4859806
    Abstract: A discretionary interconnect which includes orthogonal arrays of conductors sandwiched between conductive planes and accessible through a number of selectively arranged vias for interconnection and interruption. Also disclosed is a process of personalizing an interconnect of this type by selectively connecting and disconnecting the conductors.
    Type: Grant
    Filed: May 17, 1988
    Date of Patent: August 22, 1989
    Assignee: Microelectronics and Computer Technology Corporation
    Inventor: Robert T. Smith