Planar Circuit Overlying A Second Planar Circuit, Both Adapted To Be Electrically Connected Patents (Class 439/44)
  • Patent number: 10057982
    Abstract: Embodiments of the invention provide a solderless breadboard for prototyping electrical circuits. The breadboard includes a plurality of electrically conductive lines arranged parallel to each other on an electrically non-conductive breadboard structure. An electrically conductive line includes a plurality of electrical insertion positions and at an electrical insertion position a moveable electrically conductive line section which is operable for breaking the electrically conductive line in moving from a closed to an open position. A plurality of pegs are inserted into the breadboard structure at electrical insertion positions to contact the moveable sections. A peg is rotatable after insertion and includes a head portion and a cylindrical shaft extending from the head portion to a terminating foot. The shaft includes a centrally arranged channel extending from an opening in the head portion towards the terminating foot.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Fraser I. MacIntosh
  • Patent number: 9705224
    Abstract: A card connector includes an insulative housing defining a front-and-rear direction, a number of contacts accommodated in the insulative housing, a metallic shell enclosing the insulative housing to form a receiving space and an ejector having a shaft received in the right of the receiving space and an actuator driven by the ejector. The metallic shell has a receiving slot receiving the shaft, and an upper wall and a lower wall around the receiving slot. The upper wall and the lower wall restrict the shaft in an up-and-down direction perpendicular to the front-and-rear direction.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: July 11, 2017
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventor: Gang Hu
  • Patent number: 9281586
    Abstract: In a connector, a socket fitting portion of the socket housing and a header fitting portion of the header housing are fitted to each other to bring socket and header terminals and into contact with each other. In the socket housing, a socket terminal group including the plural socket terminals arranged in the longitudinal direction of the socket housing is provided only in a single line. In the header housing, a header terminal group including the plural header terminals arranged in the longitudinal direction of the header housing is provided only in a single line. It is, therefore, possible to minimize the connector in the width direction.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: March 8, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Yoji Miyazaki
  • Patent number: 8934263
    Abstract: The present disclosure relates to sensors including pressure sensors, humidity sensors, flow sensors, etc. In some cases, a cover for use with a sensor assembly may include an electrically insulating body having perimeter features extending a majority of the way around perimeters of upper and lower printed circuit boards that the cover may vertically separate. In one example, the body of the cover may include support features that extend from a lower side of the cover and those support features may contact the lower printed circuit board in at least two locations. The support features of the cover may be separated by a gap and a sensor connected to the lower printed circuit board may be situated within the gap.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: January 13, 2015
    Assignee: Honeywell International Inc.
    Inventors: Todd Eckhardt, Jim Machir, Palani Thanigachalam, Sunil Job
  • Patent number: 8923003
    Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: December 30, 2014
    Assignee: Apple Inc.
    Inventors: Alexander D. Schlaupitz, Joshua G. Wurzel
  • Publication number: 20130251052
    Abstract: Techniques are provided for an adapter device configured to enable communications between a quad small form-factor pluggable (QSFP) transceiver unit and a CXP host port. The adapter device comprises a first connector unit, a second connector unit, a microcontroller unit and a plurality of reception equalizer units. Data signals are sent by the transceiver unit to a first equalizer unit via the first connector unit. The first equalizer unit adjusts the data signals and sends the data signals to the host port via the second connector unit. Likewise, data signals are sent by the host port to a second equalizer unit via the second connector unit. The second equalizer unit adjusts the data signals and sends the data signals to the transceiver unit via the first connector unit.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 26, 2013
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Norman Tang, Liang Ping Peng, David Lai, Alex Hu
  • Patent number: 8430674
    Abstract: The present invention relates to a connector with a blade comprising a housing. The housing comprises a lateral opening designed to receive an electric wire, a flexible blade and an opening opposite a free part of the blade. The flexible blade is designed to make contact with the electric wire and to retain the wire by applying pressure on it towards a wall of the housing. The opening has a shape designed to guide the head of a tool and make the head of the tool follow a helical motion. The opening may be threaded and cylindrical and the opening's thread may comprise only one helical groove formed in the wall of the opening.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: April 30, 2013
    Assignee: Finsecur
    Inventors: Laurent Pichard, Stéphane Di Marco, Christophe Bonazzi
  • Patent number: 8325759
    Abstract: A device, network and method wherein a standard wireless modem is coupled to wiring for carrying a wireless baseband signal that may be OFDM based, and may be directly generated by the wireless IF modem, or extracted from the modem RF signal. The wiring may be a building utility wiring, such as telephone, AC power or CATV wiring. The baseband signal is carried simultaneously with the utility service signal over the utility wiring using Frequency Division Multiplexing. The device may be enclosed with a data unit, a standalone dedicated enclosure, within an outlet or as a plug-in outlet adapter. Data units may couple the device by a wiring port such as standard data connector, or via wireless connection. The device may be locally powered or via a power signal carried over the wiring. This abstract is not intended to limit or construe the scope of the claims.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: December 4, 2012
    Assignee: Corning MobileAccess Ltd
    Inventors: Ami Hazani, Shlomo Butbul, Yehuda Binder
  • Patent number: 8243470
    Abstract: An input/output cable port assembly and electromagnetic interference attenuation method are provided. The cable port assembly includes a cable port structure mounted to an electronics rack with an opening for input/output cables to pass therethrough, and multiple bottom ferrite inductor portions and multiple top ferrite inductor portions. The bottom and top ferrite inductor portions include first and second surfaces, respectively. The inductor portions are configured to be stacked within the cable port structure with their first and second surfaces in opposing relation to define at least one ferrite inductor with a central opening defined by the first and second surfaces for input/output cable(s) of the electronics rack to pass. The ferrite inductor attenuates electromagnetic interference resulting from transient or steady state current on the cable(s) passing therethrough.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Alma Jaze, Alan H. Knight, John M. Skillman, Kwok M. Soohoo
  • Patent number: 8096049
    Abstract: First, a unilayer wiring board is fabricated, which has wiring layers formed in desired shapes on both sides of an insulating base member; and a metal bump formed on the wiring layer on one side of the insulating base member. Then, a desired number of unilayer boards are prepared and stacked up. On that case, the board disposed in the uppermost layer is prepared without having a metal bump. The boards are positioned and stacked up in such a manner that a metal bump of one of adjacent boards is connected to a corresponding wiring layer of the other board. Thereafter, resin is filled into gaps between the stacked boards, and insulating layers are formed on both sides of a multilayer board obtained through the above steps, in such a manner as to cover the entire surface except pad areas defined at predetermined positions on the wiring layers.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: January 17, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Tetsuya Koyama, Tsuyoshi Kobayashi, Hiroyuki Kato, Yoshihiro Machida
  • Patent number: 8087164
    Abstract: A method of manufacturing a printed wiring board with solder bumps includes forming a solder-resist layer having small and large apertures exposing a respective conductive pad of the printed wiring board, loading a solder ball in each of the small and large apertures using a mask with aperture areas corresponding to the apertures of the solder-resist layer, forming a first bump having a first height, from the solder ball in the small aperture, and a second bump having a second height, from the solder ball in the large aperture, the first height being greater than the second height, and pressing a top of the first bump such that the first height becomes substantially the same as the second height. A multilayer printed wiring board includes a solder-resist layer with apertures of differing sizes and solder bumps having substantially equal volumes but a difference in height no greater than 10 ?m.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: January 3, 2012
    Assignee: IBIDEN Co., Ltd.
    Inventors: Katsuhiko Tanno, Youichirou Kawamura
  • Patent number: 8009437
    Abstract: The present disclosure generally pertains to wireless communication modules that can be used for enabling wireless communication in various applications. A wireless communication module in accordance with one embodiment may be interfaced with other devices, such as nodes of a wireless sensor network (WSN). The module has rows of male integrated circuit (IC) pins that may be interfaced with female pin receptacles of another device. The module receives wireless signals and provides the data of such wireless signals to the other device. The module also receives data from the other devices and packetizes such data for wireless communication.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: August 30, 2011
    Assignee: Synapse Wireless, Inc.
    Inventors: Gary W. Shelton, Terry G. Phillips, Thomas J. Watson
  • Patent number: 7994443
    Abstract: A first wiring layer 16 is disposed on an insulating film 14 on the lower surface of an upper substrate 15, while a second wiring layer 13three-dimensionally crossing the first wiring layer 16 is provided on the insulating film 12 on a lower substrate 11. A cantilever 17 has one end connected to the first wiring layer 16 and the other end opposed to the second wiring layer 13 with a space therebetween. A thermoplastic sheet 19 is arranged on the upper substrate 15 so as to cover the through-hole 18. The thermoplastic sheet 19 is pressed by a heated pin 20 against the cantilever 17 and deformed so as to maintain the connection between the cantilever 17and the second wiring layer 13, and therefore close the switch 10.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: August 9, 2011
    Assignees: Tokyo Electron Limited, Octec Inc.
    Inventors: Masato Hayashi, Masami Yakabe, Tetsuya Hasebe, Muneo Harada, Katsuya Okumura
  • Patent number: 7882627
    Abstract: First, a unilayer wiring board is fabricated, which has wiring layers formed in desired shapes on both sides of an insulating base member; and a metal bump formed on the wiring layer on one side of the insulating base member. Then, a desired number of unilayer boards are prepared and stacked up. On that case, the board disposed in the uppermost layer is prepared without having a metal bump. The boards are positioned and stacked up in such a manner that a metal bump of one of adjacent boards is connected to a corresponding wiring layer of the other board. Thereafter, resin is filled into gaps between the stacked boards, and insulating layers are formed on both sides of a multilayer board obtained through the above steps, in such a manner as to cover the entire surface except pad areas defined at predetermined positions on the wiring layers.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: February 8, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Tetsuya Koyama, Tsuyoshi Kobayashi, Hiroyuki Kato, Yoshihiro Machida
  • Patent number: 7854541
    Abstract: A backlight unit with socket connecter includes: a bottom frame having a topside and a backside; at least one lamp on the topside of the bottom frame; a socket connector disposed on a backside of the bottom frame, the socket connector being connected to the lamp; and a backlight circuit board having a plug connector connected to the socket connector.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: December 21, 2010
    Assignee: LG Display Co., Ltd.
    Inventor: Eun-Seok Kim
  • Patent number: 7854631
    Abstract: Featured is a controller for a motor that is ultra-compact, with a power density of at least about 20 watts per cubic cm (W/cm3). The controller utilizes a common ground for power circuitry, which energizes the windings of the motor, and the signal circuitry, which controls this energization responsive to signals from one or more sensors. Also, the ground is held at a stable potential without galvanic isolation. The circuits, their components and connectors are sized and located to minimize their inductance and heat is dissipated by conduction to the controller's exterior such as by a thermally conductive and electrically insulating material (e.g., potable epoxy). The controller uses a single current sensor for plural windings and preferably a single heat sensor within the controller. The body of the controller can also function as the sole plug connector.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: December 21, 2010
    Assignee: Barrett Technology, Inc.
    Inventors: William T. Townsendl, Adam Crowell, Gill Pratt, Traveler Hauptman
  • Patent number: 7746654
    Abstract: A computer system is provided that includes a chassis, a system board coupled to the chassis, and a first connector extending from the system board at a first height and configured to receive a first printed circuit board, wherein the first printed circuit board is configured to be parallel to the system board when received by the first connector, and a second connector extending from the system board at a second height and configured to receive a second printed circuit board, wherein the second printed circuit board is configured to be parallel to the system board when received by the second connector. Other computer systems are provided that include a first mezzanine card and a second mezzanine card or multiple connectors and a plurality of printed circuit boards.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: June 29, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: John P. Franz, Walton S. Little, Jr., Tuan A. Pham, John D. Nguyen
  • Patent number: 7631199
    Abstract: Various methods, apparatuses, and systems are described in which a chipset controller has circuitry to control communications with a peripheral device in a computing device. The chipset controller has logic configured 1) to detect a plug-in event when the peripheral device connects to the chipset controller and 2) to transition the chipset controller from a low power consumption state to a higher power consumption state based on the logic detecting the plug-in event.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: December 8, 2009
    Assignee: Intel Corporation
    Inventors: James P. Kardach, Barnes Cooper, Seh Kwa, Animesh Mishra, Paul Diefenbaugh
  • Publication number: 20090075492
    Abstract: The invention relates to a distributor connection module used in the telecommunication and data technology field. Said distributor connection module comprises a housing which comprises a cavity wherein at least two conductor plates are arranged, and the housing comprises at least one opening in a front side wherein two connector modules can be inserted. A pivotable protection frame is arranged on the housing, which can adopt at least two positions. In a first pivoted position, the connector module is free and in a second position, the protection frame is arranged in a parallel manner in relation to the front side.
    Type: Application
    Filed: October 31, 2005
    Publication date: March 19, 2009
    Applicant: ADC GmbH
    Inventor: Manfred Stockel
  • Patent number: 7489524
    Abstract: An assembly is provided which includes a first circuit panel having a top surface, a first dielectric element and first conductive traces disposed on the first dielectric element. In addition, a second circuit panel has a bottom surface, a second dielectric element and second conductive traces disposed on the second dielectric element, where at least a portion of the second circuit panel overlies at least a portion of the first circuit panel. The assembly further includes an interconnect circuit panel having a third dielectric element which has a front surface, a rear surface opposite the front surface, a top end extending between the front and rear surfaces, a bottom end extending between the front and rear surfaces, and a plurality of interconnect traces disposed on the dielectric element.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: February 10, 2009
    Assignee: Tessera, Inc.
    Inventors: Ronald Green, Sridhar Krishnan, Stuart E. Wilson, James Gill Shook, Ming Tsai, Andy Stavros
  • Patent number: 7364455
    Abstract: The integration areas, system and method of interconnecting components provide efficient techniques for separating the conductive path between components from the pin-to-pin integration between components through the use of conductive elements that may be interconnected in a variety of manners. The interconnections between the conductive elements may be configured automatically and may be modified relatively easily. The integration area includes component connection receptacles, first conductive elements that extend from each component connection receptacle, second conductive elements that extend across at least one first conductive element, and connections between the conductive elements to interconnect the components. The conductive elements may include flatwire segments and/or printed circuit boards. The connections between the conductive elements may be made with pins and jumpers, connection vias and solder patches and/or various insulation barriers through which the conductive elements connect.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: April 29, 2008
    Assignee: The Boeing Company
    Inventors: Daniel J. Diessner, Bradley J. Mitchell
  • Patent number: 7121875
    Abstract: The integration areas, system and method of interconnecting components provide efficient techniques for separating the conductive path between components from the pin-to-pin integration between components through the use of conductive elements that may be interconnected in a variety of manners. The interconnections between the conductive elements may be configured automatically and may be modified relatively easily. The integration area includes component connection receptacles, first conductive elements that extend from each component connection receptacle, second conductive elements that extend across at least one first conductive element, and connections between the conductive elements to interconnect the components. The conductive elements may include flatwire segments and/or printed circuit boards. The connections between the conductive elements may be made with pins and jumpers, connection vias and solder patches and/or various insulation barriers through which the conductive elements connect.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: October 17, 2006
    Assignee: The Boeing Company
    Inventors: Daniel J. Diessner, Bradley J. Mitchell
  • Patent number: 6898852
    Abstract: A connector assembly is disclosed and claimed. The connector assembly includes a connector and a cable attachable at one end to the connector. The cable includes a first conductive layer and a second conductive layer disposed over the first conductive layer. A layer of insulation material is disposed at least between the first conductive layer and the second conductive layer and a plurality of capacitors are connected between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: May 31, 2005
    Assignee: Intel Corporation
    Inventors: Nader N. Abazarnia, Jeffrey H. Luke, James Neeb
  • Patent number: 6838975
    Abstract: An identification apparatus comprising an array of retractable conductive pins on a base component placed onto a primary device and in communication therewith. A set of shaped identifiers have a plurality of holes through which respective pins on the array of retractable pins pass, each identifier being uniquely configured with at least one distinct location containing a conductive plug or ‘cap’ fitted therein which blocks the passage therethrough of that particular pin thereby forcing said pin to retract into the base component to block further use of that pin by subsequently placed identifiers. Each retractable pin is in individual communication with the primary device such that, once one or more identifiers have been placed onto the pin array, the primary device can thereafter identify the placed identifiers so as to subsequently perform certain functions or other desired operations based on the type, configuration, and/or number of identifiers placed thereon.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: January 4, 2005
    Assignee: Xerox Corporation
    Inventors: Debora Margaret Hejza Litwiller, Philip E. Blair
  • Patent number: 6830176
    Abstract: A new system and method for repairing flexible circuits is disclosed. The flexible circuits conduct electrical signals to and from electronic devices. The system generally includes a flexible circuit substrate, at least one electrical conductor, and a repair patch. The flexible circuit substrate has a cut zone and a repair zone. The at least one electrical conductor is supported by the flexible circuit substrate. The electrical conductors are configured to carry electrical signals. The repair patch is used to electrically interconnect at least two repair zones.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: December 14, 2004
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Peter Joseph Sinkunas, Zhong-You Shi, Jay D. Baker, Robert Edward Belke, Charles Frederick Schweitzer, Raymond Eric Foster, Stephen Edward Fuks
  • Patent number: 6804123
    Abstract: A computer mainframe includes a housing, a motherboard, an intermediate circuit board, and a supporting bracket. A CD-ROM and a hard disk are attached to upper and lower sides, respectively, of the intermediate circuit board to sequentially superpose on and electrically connect to the motherboard via various connecting terminals provided at specific positions on the upper and the lower side of the intermediate circuit board. With the vertically superposed architecture of the mainframe, no space-occupying flat cable is needed for wiring the mainframe, enabling the mainframe to have a largely reduced volume.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: October 12, 2004
    Assignee: King Young Technology Co., Ltd.
    Inventor: Wan Chen Cheng
  • Publication number: 20040002231
    Abstract: An electrical connector (1) for electrically connecting an electronic package with a circuit substrate. The connector includes a base (2), a cover (3) slidably attached on the base, and an actuation device (4) for actuating the cover to slide along the base. The actuation device includes a camshaft (42) and an operation lever (41). The camshaft includes first actuating portions (43), and a central second actuating portion (44). During opening and closing of the cover, the first actuating portions and the second actuating portion are respectively at work. This ensures that diameters of the different portions of the camshaft are different. Thus the camshaft can have sufficiently high tension to minimize the risk of it being distorted. When the lever is rotated to a vertical position, the first actuating portions are engaged with second flat side walls (251) of the base. This helps prevent the lever from being over-rotated.
    Type: Application
    Filed: February 27, 2003
    Publication date: January 1, 2004
    Inventor: Wei Yu
  • Patent number: 6666729
    Abstract: A joint connector includes a connecting unit provided with a bus bar on an insulating plate. The bus bar includes a joint area connecting plural pressure welding areas of the bus bar, to which wires may be pressure welded. The joint connector also includes a joint plate with plural pressure welding slots in which connecting units may be inserted to establish connection between the joint plate and joint areas of the connecting units. By stacking plural pressure-welded connecting units and pressure fitting their insulating plates into pressure welding slots of a joint plate, wires pressure-welded to upper and lower connecting units are connected together.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: December 23, 2003
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventors: Yoshikatsu Takamura, Yukimitsu Hattori
  • Publication number: 20030181070
    Abstract: A plug connector is proposed, in particular for a control device (100), which includes a plug input having at least two input connections (1, 2, 3), a plug output having at least two output connections (4, 5, 6), and at least one connecting part (10, 20) via which the respective associated connections (1, 2, 3, 4, 5, 6)—input connection and output connection—are interconnected.
    Type: Application
    Filed: May 30, 2003
    Publication date: September 25, 2003
    Inventors: Rainer Topp, Achim Henkel, Reinhard Milich
  • Patent number: 6443737
    Abstract: A circuit board has an insulation board and strip bus bars arranged on the opposite faces of the board. On one face, the bus bars extend in parallel in a first direction. On the second face, the bus bars extend in parallel in a second direction crossing the bars extending in said first direction, so that there is an array of crossing points of the bus bars. The insulation board has holes at which the mutually crossing bus bars are bent towards each other and joined to establish electrical connection. In this way, a predetermined wiring pattern is obtained, which can be varied easily.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: September 3, 2002
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventor: Koji Kasai
  • Patent number: 6418034
    Abstract: A stacked printed circuit board memory module in which a plurality of daughter circuit boards can be stacked onto a primary circuit board. The primary board and each of the plurality of daughter boards have electronic memory ICs mounted on the respective surfaces. The primary board and each of the daughter boards have mounted connectors so that the boards can be electronically and mechanically interconnected with another board.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: July 9, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Rick Weber, Corey Larsen, James Howarth
  • Patent number: 6360435
    Abstract: A first printed wiring board (PWB, 102) has a first set of parallel printed wires (108) on one face and a second set of parallel printed wires (214) on the other face. The second set is generally orthogonal to the first set. The first set terminates in a first adaptor (110), which adapts to an interface (1034) having many parallel channels. The second set terminates in a second adaptor (112), which adapts to a second PWB (1036). Development of the second PWB is enhanced when any input or output on the second PWB can be connected to any channel of the interface. Thus, a hole is drilled through the first PWB at the intersection of the appropriate printed wires of the first and second sets, and is plated. The plated hole (416) may be drilled out (rendering it non-conductive) and effectively replated many times. Alternatively, the (inexpensive) first PWB may be replaced.
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: March 26, 2002
    Assignee: Qualcomm Incorporated
    Inventor: Robert B. Ganton
  • Patent number: 6324071
    Abstract: A stacked printed circuit board memory module in which a plurality of daughter circuit boards can be stacked onto a primary circuit board. The primary board and each of the plurality of daughter boards have electronic memory ICs mounted on the respective surfaces. The primary board and each of the daughter boards have mounted connectors so that the boards can be electrically and mechanically interconnected with another board.
    Type: Grant
    Filed: January 14, 1999
    Date of Patent: November 27, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Rick Weber, James Howarth, Corey Larsen
  • Patent number: 6297460
    Abstract: An electrical interconnection medium is provided having first and second overlying interconnection layers. Each interconnection layer includes parallel conductors, and the conductors of the first and second interconnection layers are oriented orthogonally to each other. The conductors can be interconnected to form at least two electrical planes, with the conductors of the electrical planes being substantially interdigitated on each interconnection layer, portions of each plane appearing on both layers. The interconnection medium advantageously is employed as a multichip module. A method of designing such an MCM includes providing arranged conductive regions in a spaced manner, cutting selected sections to form signal conductor paths, and then filling spaces between like power and ground conductors.
    Type: Grant
    Filed: February 28, 1995
    Date of Patent: October 2, 2001
    Assignee: The Board of Trustees of the University of Arkansas
    Inventor: Leonard W. Schaper
  • Patent number: 6274819
    Abstract: An article and method for making and repairing connections between first and second circuits, such as flex circuits. The article 10 includes: a flexible dielectric substrate 12 having first and second edges 14/16, and a plurality of conductive circuit traces 18 arranged on or within the substrate, wherein each of the traces extends from proximate the first edge 14 to proximate the second edge 16. Each of the circuit traces 18 includes: a first connection feature 20 disposed proximate the first edge 14; a second connection feature 22 disposed proximate the second edge 16; and at least one third connection feature 24 disposed between the first and second edges 14/16. Each of the first, second, and third connection features 20/22/24 is a plated through hole, a plated blind via, or a mounting pad. This article 10 may be used to connect together the first and second circuits 50/60 using the first and second connection features 20/22, such as by soldering.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: August 14, 2001
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Delin Li, Jay DeAvis Baker, Achyuta Achari, Brenda Joyce Nation, John Trublowski
  • Patent number: 6056601
    Abstract: A connector for mounting a processor card on a motherboard includes a base and an upper support chassis. The base is electrically and structurally coupled to a motherboard and the upper support chassis is mounted on the base. A processor card is received within the upper support chassis for mounting of the card to the motherboard. When the card is received within the upper support chassis, the processor card is positioned substantially parallel to the motherboard.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: May 2, 2000
    Assignee: Intel Corporation
    Inventors: Steven L. Pollock, Robert Olivier
  • Patent number: 5999097
    Abstract: An electrical lead has a first set of terminals (14) at one end of the lead and a second set of terminals (15) at the other end of the lead. A connector circuit (11,12) respectively connects the terminals (14) to the terminals (15). This circuit (11,12) is adjustable so as to change the connection paths between the first and second sets of terminals (14,15). The connector circuit (11,12) is surrounded by a security enclosure which comprises flexible sheet means of electrically insulating material carrying an array of lines of electrically security conductors. Monitoring means are connected to the security conductors to detect a change in an electrical characteristic thereof resulting from damage to the security enclosure. The invention can be used in a financial terminal, and provides security against a fraudulent attack on the lead intended to gain access to confidential information, such as a personal identification number, transmitted over the lead.
    Type: Grant
    Filed: May 21, 1998
    Date of Patent: December 7, 1999
    Assignee: NCR Corporation
    Inventors: Mark J. D. Liddle, Stephen B. Hunter
  • Patent number: 5919259
    Abstract: A method and apparatus for supplying power to a central processing unit (CPU) in computer systems which normally mount CPUs on a motherboard and supplies power to the CPUs via motherboard circuitry which delivers CPU current from power supply sources connected to the motherboard. The method provides the supply of partial or complete power to a CPU mounted on a computer motherboard directly from a power supply and involves the steps (a) disconnecting the power supply to the motherboard; (b) disconnecting the CPU from a CPU socket or plug on the motherboard; (c) mounting the CPU on an adaptor that can be installed in the CPU socket or plug on the motherboard; (d) installing the adaptor and the mounted CPU in the CPU socket or plug on the motherboard; (e) attaching the power supply to the adaptor to provide partial or complete power to the CPU; and, (f) attaching the power supply to the motherboard.
    Type: Grant
    Filed: April 18, 1997
    Date of Patent: July 6, 1999
    Inventor: Nathaniel H. Dahl
  • Patent number: 5867366
    Abstract: The present invention relates to an electronic module, especially a storage module, having a strip on each of two opposite sides and a plastic substrate to accept and hold the electronic module in grooves in two U-shaped rails corresponding to the strips. The electronic module also has a plastic frame which accepts a fitted printed-circuit board and has at least one electrically conductive covering on either its upper and/or lower side and which extends as far as the strips and is connected to a reference potential. The electrical connection of the coverings to reference potential is ensured by contact components.
    Type: Grant
    Filed: August 14, 1995
    Date of Patent: February 2, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventors: Klaus Klein, Franz Mittnacht, Edgar Starck
  • Patent number: 5841836
    Abstract: A network termination equipment for connecting telecommunications apparatus to a telecommunications network has operative elements to perform terminal functions. The termination may perform line diagnostic functions, remote telemetry functions. Alternative front plates are connectable to intermediate plate to configure the termination equipment to perform the different functions necessary for additional services or to control access to the network to authorized users only.
    Type: Grant
    Filed: February 11, 1997
    Date of Patent: November 24, 1998
    Assignee: British Telecommunications public limited company
    Inventors: Anthony G. Dunn, Jonathan J. Kingan
  • Patent number: 5768106
    Abstract: A layered circuit-board designing method and layered circuit-board where circuit-boards to be overlaid are connected at the center or an arbitrary position of each circuit-board. The layered circuit-board includes an upper-layer first circuit-board, a lower-layer third circuit-board, and an intermediate-layer second circuit-board between the first and third circuit-boards. A first connector is mounted on the first circuit-board, a second connector is mounted on the third circuit-board, a third connector is mounted on the top surface of the second circuit-board, while maintaining the positional relation between the third connector and the first connector, and a fourth connector is mounted on the bottom surface of the second circuit-board, while maintaining the positional relation between the fourth connector and the second connector. In addition, through holes are provided at pins of the third and fourth connectors for passing through the front and bottom surfaces of the second circuit-board.
    Type: Grant
    Filed: June 11, 1996
    Date of Patent: June 16, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventor: Akira Ichimura
  • Patent number: 5691885
    Abstract: Circuit supporting modules form a three-dimensional communication interconnect mesh. A first embodiment three-dimensional communication interconnect is a tetrahedral lattice having a regular, isotropic, three-dimensional topology in which each module connects to its four physically closest neighbors. The structure of the tetrahedral interconnect is isomorphic with a diamond lattice structure. In a second embodiment the interconnect is hexahedral. A characteristic of both is embodiments is that, although connections are made to plural other modules, the physical connections are made along the same direction.
    Type: Grant
    Filed: October 14, 1994
    Date of Patent: November 25, 1997
    Assignee: Massachusetts Institute of Technology
    Inventors: Stephen A. Ward, Gill A. Pratt, John N. Nguyen, John S. Pezaris, Norman Margolus
  • Patent number: 5653607
    Abstract: An electric connection casing comprising a large intensity-current circuit through electric current having a large intensity flows; a small intensity-current circuit through electric current having a small intensity flows; and a fuse and a relay interposed between the large intensity-current circuit and the small intensity-current circuit, wherein the large intensity-current circuit and the small intensity-current circuit comprise a plurality of single core wires, respectively; and a plurality of pressure-contact terminals which penetrates through an insulation coating of the single core wire, thus being connected with the single core wire by pressing the pressure-contact terminal against the single core wire.
    Type: Grant
    Filed: July 25, 1995
    Date of Patent: August 5, 1997
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventors: Yuuji Saka, Nori Inoue, Takahiro Onizuka, Yoshito Oka, Makoto Kobayashi, Hisashi Kounoya
  • Patent number: 5642055
    Abstract: A method and apparatus for electrically interconnecting various electronic elements, including circuit components, assemblies, and subassemblies. A particle enhanced material metal contact layer, having a surface, formed on the electronic elements, includes particles of greater hardness disposed on and/or within the metal contact layer, which particles form protuberances that concentrate stress when said contact surface is brought into contact with an opposing surface under pressure, to thereby penetrate the opposing surface and form a metal matrix between the two surfaces.
    Type: Grant
    Filed: April 12, 1995
    Date of Patent: June 24, 1997
    Assignee: Particle Interconnect, Inc.
    Inventor: Louis Difrancesco
  • Patent number: 5610801
    Abstract: A motherboard assembly which has an integrated circuit socket that can be mated with either a single integrated circuit package or a multiple integrated circuit package module. The motherboard has a socket connector which can receive the external pins of an integrated circuit package. The motherboard also has an auxiliary connector that can mate with a corresponding connector-mounted to a daughterboard. Mounted to the daughterboard are a first integrated circuit package and a second integrated circuit package. Each package may contain a multi-processing microprocessor. The first integrated circuit package has a plurality of pins that mate with the socket connector. The daughterboard can be coupled to the motherboard by pressing the external pins of the first integrated circuit package into the socket connector and mating the auxiliary connectors. The present invention allows a plurality of processors to be plugged into a single socket without occupying a significant amount of space on the motherboard.
    Type: Grant
    Filed: November 15, 1995
    Date of Patent: March 11, 1997
    Assignee: Intel Corporation
    Inventor: Glenn Begis
  • Patent number: 5585602
    Abstract: A method for forming one or more conductive paths by providing a first pattern of pre-formed conductive elements and a second pattern of preformed conductive elements in a substrate and forming, at a single level, one or more lateral conductive links between selected ones of the first and second conductive elements to provide a selected configuration of one or more conductive paths.
    Type: Grant
    Filed: January 9, 1995
    Date of Patent: December 17, 1996
    Assignee: Massachusetts Institute of Technology
    Inventor: Joseph B. Bernstein
  • Patent number: 5583749
    Abstract: A reconfigurable apparatus for computing systems including a set of baseboards and a family of daughtercards, together with a programmable interface to an external bus for a host system. Daughtercards attach to the baseboard through complementary connectors mounted on the baseboard and the daughtercards. In addition, daughtercards are constructed to allow stacking of daughtercards vertically. The baseboard and daughtercard approach of the present invention allows simple, incremental upgrade of installed boards by adding or replacing the daughtercards and allows simple migration to new systems by changing baseboards.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: December 10, 1996
    Assignee: Altera Corporation
    Inventors: Harry L. Tredennick, David E. Van den Bout
  • Patent number: 5537292
    Abstract: The expansion card is inserted into a narrow slot through the outside cover of the subscribers terminal and is guided by a carrier into the external connector. A protective casing on the card includes a pivotable door which permits the card to maintain a slim profile. The door is opened during the insertion process into the external connector by a pair of tongs positioned at an inclined angle on the carrier to expose the terminal end of the expanding card.
    Type: Grant
    Filed: November 21, 1994
    Date of Patent: July 16, 1996
    Assignee: Scientific-Atlanta, Inc.
    Inventor: Donald H. Bowen
  • Patent number: 5530625
    Abstract: An interface board for use, for example, in a motor vehicle to provide electrical interconnection between a plurality of electrical circuit control elements and a wiring harness. The board comprises a box structure including a plurality of circuit outlets on the upper face of the structure for plug in receipt of the electrical circuit control elements, a plurality of power outlets on a lower face of the structure for plug in receipt of electrical power input and output elements, and a series of electrical paths extending between the power outlets and a circuit control outlets. Each electrical path includes a first conductor extending generally parallel to the first and second faces and second conductors extending generally perpendicular to the first and second faces. The first conductors comprise flat ribbon elements and the second conductors comprise flat ribbon elements connected to the flat sides of the first conductors utilizing clinch joints.
    Type: Grant
    Filed: September 7, 1994
    Date of Patent: June 25, 1996
    Assignee: Electro-Wire Products, Inc.
    Inventors: Allen VanDerStuyf, Dewey Mobley, James P. Burgess
  • Patent number: 5513077
    Abstract: An arrangement for a motor vehicle for central connection of electrical components, the arrangement comprises a housing, a plurality of supply circuits and control circuits, a plurality of circuit straps punched out of metal sheets and printed circuit boards, the supply circuits and the control circuits being formed so that the supply circuits are formed exclusively from the punched circuit straps and the control circuits are formed exclusively from the printed circuit boards, the printed circuit boards with the punched circuit straps and their intermediate insulations being assembled in a plurality of layers in a substantially identical surface configuration to form a printed circuit pack.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: April 30, 1996
    Assignee: Stribe GmbH
    Inventor: Hans P. Stribel