Emissive Type Patents (Class 445/50)
  • Patent number: 6045711
    Abstract: A vacuum seal suitable for use with field emission arrays is described. This seal has high reliability because the expansion coefficients of the metal and the glass are closely matched. Materials traditionally used for cathode and gate lines continue to be employed. To achieve this, a gap is introduced into each conductive line near the edges of the display. This gap is bridged by a material having an expansion coefficient that more closely matches that of the glass used for the seal and is the only material that contacts the seal. The bridge may be in the form of a deposited layer or it may be a discrete wire. A description of how the structure is manufactured is also provided.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: April 4, 2000
    Assignee: Industrial Technology Research Institute
    Inventors: Wen-Chun Wang, Chun-hui Tsai, Chih-Hao Tien
  • Patent number: 6043103
    Abstract: A field-emission cold cathode includes a substrate having a sharply pointed emitter disposed on a surface thereof and serving as an emitter electrode, an insulating film disposed on the substrate, and a gate electrode disposed on the insulating film and having an opening defined therein and having an edge surrounding the emitter. The gate electrode and the emitter are spaced from each other across a cavity near the emitter. The insulating film and the substrate have a boundary surface therebetween which is lower than the surface of the substrate. The substrate has a step positioned between the boundary surface and the surface of the substrate on which the emitter is disposed, the step being disposed between the insulating film and the emitter. The insulating film supports the gate electrode and has a thickness greater than the distance between the emitter and the gate electrode.
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: March 28, 2000
    Assignee: NEC Corporation
    Inventor: Hisashi Takemura
  • Patent number: 6042444
    Abstract: A method for fabricating a cathode of a field emission display. A doped polysilicon layer is formed over a substrate, and the doped polysilicon layer is patterned to form a plurality of field emitters. The doped polysilicon layer and the field emitters are patterned to form a plurality of field emission arrays. Then, a sharpening process is performed to form an oxide layer on the field emitters. A first dielectric layer and a second dielectric layer are formed conformal to the substrate, and a third dielectric layer is formed on the second dielectric layer. The third dielectric layer is planarized to expose the second dielectric layer on a top portion of each of the field emitters. The exposed second dielectric layer is removed, and an oxide layer is formed on the third dielectric layer and a top surface of the first dielectric layer on the top portion of the field emitter. A self-aligned metal layer is formed on the oxide layer.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: March 28, 2000
    Assignee: United Semiconductor Corp.
    Inventor: Chih-Chong Wang
  • Patent number: 6036566
    Abstract: The microtips of charge emitting material, which define the cathode of the flat FED screen and face the grid of the screen, are tubular and have portions with a small radius of curvature. The microtips are obtained by forming openings in the dielectric layer separating the cathode connection layer from the grid layer, depositing a conducting material layer to cover the walls of the openings, and anisotropically etching the layer of conducting material to form inwardly-inclined surfaces with emitting tips. Subsequently, the portions of the dielectric layer surrounding the microtips are removed.
    Type: Grant
    Filed: October 2, 1997
    Date of Patent: March 14, 2000
    Assignee: SGS-Thomson Microelectronics S.R.L.
    Inventors: Livio Baldi, Maria Santina Marangon
  • Patent number: 6036565
    Abstract: There is provided a method of fabricating a field emission cold cathode, including the steps, in sequence, of (a) forming a first insulating layer on a substrate and further forming a first electrode layer on first insulating layer, (b) forming at least one opening in first electrode layer, (c) forming a second insulating layer on first electrode layer and further forming a second electrode layer on second insulating layer, (d) forming at least one opening in second electrode layer, (e) optionally repeating steps (c) and (d) predetermined number of times, (f) forming a cavity extending from an uppermost electrode layer to substrate, (g) forming a first sacrifice layer around a first opening of a first electrode layer, (h) forming a second sacrifice layer around a second opening of a second electrode layer, and (i) forming an emitter electrode on substrate with first sacrifice layer being used as a mask.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: March 14, 2000
    Assignee: NEC Corporation
    Inventors: Nobuya Seko, Yoshinori Tomihari
  • Patent number: 6037104
    Abstract: In one aspect the invention includes a method of forming a semiconductor device, comprising: a) forming a layer over a substrate; b) forming a plurality of openings extending into the layer; c) depositing particles on the layer; d) collecting the particles within the openings; and e) using the collected particles as a mask during etching of the underlying substrate to define features of the semiconductor device. In another aspect, the invention includes a method of forming a field emission display, comprising: a) forming a silicon dioxide layer over a conductive substrate; b) forming a plurality of openings extending into the silicon dioxide layer; c) depositing particles on the silicon dioxide layer; d) collecting the particles within the openings; e) while using the collected particles as a mask, etching the conductive substrate to form a plurality of conically shaped emitters from the conductive substrate; and f) forming a display screen spaced from said emitters.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: March 14, 2000
    Assignee: Micron Display Technology, Inc.
    Inventor: Eric A. Lahaug
  • Patent number: 6033277
    Abstract: The present invention provides a method for reshaping up a cone-like electrode which is made of a refractory metal containing silicon. The method comprises the following steps. A surface of the cone-like electrode is subjected to an oxidation of silicon which is contained in the refractory metal. The oxidation is generated at rates which increase toward a top portion of the cone-like electrode. As a result, a silicon oxide film is formed, which coats the cone-like electrode. The silicon oxide film has thickness which gradually increase toward a bottom portion of the cone-like electrode. An interface between the silicon oxide film and the cone-like electrode has sloped angles which increase toward the top portion. The silicon oxide film is removed to thereby expose a reshaped cone electrode which has a sharply pointed top. The reshaped cone electrode has a surface having sloped angles which increase toward the sharply pointed top.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: March 7, 2000
    Assignee: NEC Corporation
    Inventor: Toshio Kaihara
  • Patent number: 6033924
    Abstract: A method for fabricating a field emission device (200) includes the steps of forming on the surface of a substrate (110) a cathode (112), forming on the cathode (112) a dielectric layer (114), forming an emitter well (115) in the dielectric layer (114), forming within the emitter well (115) an electron emitter structure (118) having a surface (123), forming on a portion of the dielectric layer (114) a gate electrode (116), depositing on the dielectric layer (114) a sacrificial layer (210), thereafter depositing on the surface (123) of the electron emitter structure (118) a coating material (220, 320, 420) that has an emission-enhancing material, and then removing the sacrificial layer (210).
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: March 7, 2000
    Assignee: Motorola, Inc.
    Inventors: Sung P. Pack, Babu R. Chalamala
  • Patent number: 6027388
    Abstract: A mask structure may be formed on a field emitter substrate for use in forming emitter wells on and in the substrate. The mask structure may be formed from a multilayered structure on the surface of the substrate using a laser lithography process. From the substrate up, the multilayered structure may include an antireflective coating, a photoresistive layer, an optional etch resistant layer between the antireflective coating and the photoresistive layer, and an optional second antireflective coating between the optional etch resistant layer and the photoresistive layer. The pattern of the mask structure may be transferred to the multilayer structure by exposing the photoresistive layer to laser light. The antireflective coatings may reduce the amount of stray laser light that reflects off the substrate and onto the back of the photoresistive layer.
    Type: Grant
    Filed: August 5, 1997
    Date of Patent: February 22, 2000
    Assignee: Fed Corporation
    Inventors: Gary W. Jones, Susan K. Jones, Amalkumar P. Ghosh
  • Patent number: 6028322
    Abstract: A field emission display includes a substrate, a plurality of emitters formed on the substrate, a semiconductor device formed in or on the substrate for controlling the flow of electrons to the emitters and a dielectric layer formed on the substrate. An extraction grid is formed on the dielectric layer substantially in a plane of tips of the plurality of emitters and includes openings each surrounding one of the emitters. The display also includes a transparent viewing screen, a transparent conductor formed on the viewing screen and a cathodoluminescent layer formed on the transparent conductor. The semiconductor device includes a gate dielectric and a field oxide. Significantly, the field oxide includes an interfacial region acting as a trapping and recombination site for mobile charge carriers.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: February 22, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Behnam Moradi
  • Patent number: 6022256
    Abstract: A low temperature method of sharpening the emission tip of a field emission display includes the step of oxidizing the silicon substrate and the emission tip in an atmosphere of oxygen and ozone at temperatures below 800.degree. C. The oxidation step forms an oxide layer on the emission tip without significant flow of oxide or silicon during oxidation. The oxide layer is subsequently etched to expose the emission tip.
    Type: Grant
    Filed: November 6, 1996
    Date of Patent: February 8, 2000
    Assignee: Micron Display Technology, Inc.
    Inventor: J. Brett Rolfson
  • Patent number: 6020677
    Abstract: Carbon cone and carbon whisker field emitters are disclosed. These field emitters find particular usefulness in field emitter cathodes and display panels utilizing said cathodes. The carbon cone and carbon whisker field emitters can be formed by ion beam bombardment (e.g., ion beam etching) of carbon materials (e.g., bulk carbon, carbon films or carbon fibers).
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: February 1, 2000
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Graciela Beatriz Blanchet-Fincher, William Leo Holstein, Syed Ismat Ullah Shah
  • Patent number: 6019658
    Abstract: A gated electron-emitter having a lower non-insulating emitter region (42), an overlying insulating layer (44), and a gate layer (48A, 60A, 60B, 120A, or 180A/184) is fabricated by a process in which particles (46) are distributed over the insulating layer, the gate layer, a primary layer (50A, 62A, or 72) provided over the gate layer, a further layer (74) provided over the primary layer, or a pattern-transfer layer (182). The particles are utilized in defining gate openings (54, 66, 80, 122, or 186/188) through the gate layer. Spacer material is provided along the edges of the gate openings to form spacers (102A, 110A, 124A, 140, or 150B). Dielectric openings (80, 114, 128, 144, or 154) are formed through the insulating layer. The dielectric openings can be created before or after creating the spacers.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: February 1, 2000
    Assignee: Candescent Technologies Corporation
    Inventors: Paul N. Ludwig, Duane A. Haven, John M. Macaulay, Christopher J. Spindt, James M. Cleeves, N. Johan Knall
  • Patent number: 6017257
    Abstract: A self-gettering electron field emitter has a first portion formed of a low-work-function material for emitting electrons, and it has an integral second portion that acts both as a low-resistance electrical conductor and as a gettering surface. The self-gettering emitter is formed by disposing a thin film of the low-work-function material parallel to a substrate and by disposing a thin film of the low-resistance gettering material parallel to the substrate and in contact with the thin film of the low-work-function material. The self-gettering emitter is particularly suitable for use in lateral field emission devices. The preferred emitter structure has a tapered edge, with a salient portion of the low-work-function material extending a small distance beyond an edge of the gettering and low resistance material. A fabrication process specially adapted for in situ formation of the self-gettering electron field emitters while fabricating microelectronic field emission devices is also disclosed.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: January 25, 2000
    Assignee: Advanced Vision Technologies, Inc.
    Inventor: Michael D Potter
  • Patent number: 6017772
    Abstract: A method of fabricating field emission arrays which employs a single mask to define emitter tips and their corresponding resistors. Column lines may also be defined without requiring the use of an additional mask. The method includes disposing substantially mutually parallel conductive lines onto a substrate of the field emission array. The conductive lines may be patterned from a layer of conductive material or selectively deposited onto the substrate. One or more material layers, from which the emitter tips and resistors will be defined, are disposed onto the conductive lines and the regions of substrate exposed between adjacent conductive lines. The exposed surface of the layer or layers of emitter tip and resistor material or materials may be planarized. A mask is disposed over the substanitially planar surface.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: January 25, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Ammar Derraa
  • Patent number: 6015324
    Abstract: A device useful as a display element has an electron emitter and an anode disposed to receive electrons emitted from the emitter. The anode has surface portions differing in resistivity, providing an electron sink portion at the surface portion of lowest resistivity. A preferred embodiment has a lateral field-emission electron emitter and has an anode formed by processes specially adapted to provide anode portions of differing resistivity, including the electron sink portion. The electron sink portion is preferably disposed at a position laterally spaced apart from the emitting tip of the device's electron emitter.
    Type: Grant
    Filed: November 5, 1997
    Date of Patent: January 18, 2000
    Assignee: Advanced Vision Technologies, Inc.
    Inventor: Michael D Potter
  • Patent number: 6012958
    Abstract: A micropoint assembly of a field emission device ("FED") including a baseplate, one or more conductors formed over the baseplate, and one or more micropoints formed over the conductor(s) is disclosed. The micropoint assembly further indudes resistive structures associated with specific FED elements that limit current to a maximum level and minimize impact to remaining elements of the device. Any variation in resistivity is uniformly distributed since the same process is consistently applied across a plurality of element locations.
    Type: Grant
    Filed: December 14, 1997
    Date of Patent: January 11, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Kevin Tjaden, David A. Cathey, Jr., John K. Lee
  • Patent number: 6010918
    Abstract: Field emission devices may include emitter wells formed in a body of dielectric material. A gate conductor may be provided along the upper surface of the dielectric material. A gate hole may be provided in the gate conductor directly above each of the emitter wells. A method for forming the gate holes and emitter wells is disclosed. The method includes the steps of providing a first gate conductor layer on a dielectric layer. A pattern of second gate conductor material may be formed over the first gate conductor layer, said pattern defining gate holes in the second gate conductor material. The gate holes may then be completed and emitter wells formed by etching through the first gate conductor layer and into the dielectric layer using an etch that selectively etches the first gate conductor layer and the dielectric layer, and does not etch substantially the second gate conductor material.
    Type: Grant
    Filed: February 10, 1998
    Date of Patent: January 4, 2000
    Assignee: FED Corporation
    Inventors: Jeffrey R. Marino, Joseph K. Ho
  • Patent number: 6007399
    Abstract: To improve performance, reliability and lifetime of a plasma-containing electro-optic display device, at least the cathode electrodes have hollows or wells within which plasma discharge occurs. This reduces the tendency of the electrode material to be sputter deposited on the walls of the device. In addition, cathode emission is improved by incorporating emitter materials into the electrodes, either by alloying or by surface coatings.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: December 28, 1999
    Assignee: Philips Electronics North America Corporation
    Inventors: Vivek Mehrotra, Babar A. Khan
  • Patent number: 6008062
    Abstract: A technique for creating a patterned coating entails forming a first region (26) over a primary component (22). A second region (28) is formed over part of the first region. The first region is etched so as to undercut the second region, thereby forming a gap (30) below part of the second region. Coating material is then provided over the structure. Due to the presence of the gap, the coating material accumulates over the structure in a pair of segments spaced apart along the gap. One coating segment (32A) overlies the primary component. The other coating segment (32B) overlies the second region.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: December 28, 1999
    Assignee: Candescent Technologies Corporation
    Inventor: N. Johan Knall
  • Patent number: 6004180
    Abstract: Multiple procedures are presented for removing contaminant material (12) from electron-emissive elements (10) of an electron-emitting device (30). One procedure involves converting the contaminant material into gaseous products (14), typically by operating the electron-emissive elements, that move away from the electron-emissive elements. Another procedure entails converting the contaminant material into further material (16) and removing the further material. An additional procedure involves forming surface coatings (18 or 20) over the electron-emissive elements. The contaminant material is then removed directly from the surface coatings or by removing at least part of each surface coating.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: December 21, 1999
    Assignee: Candescent Technologies Corporation
    Inventors: N. Johan Knall, John D. Porter, Colin D. Stanners, Christopher J. Spindt, Victoria A. Bascom
  • Patent number: 5993281
    Abstract: A process for sharpening arrays of field emitter tips of field emission cathodes, such as found in field-emission, flat-panel video displays. The process uses sputtering by high-energy (more than 30 keV) ions incident along or near the longitudinal axis of the field emitter to sharpen the emitter with a taper from the tip or top of the emitter down to the shank of the emitter. The process is particularly applicable to sharpening tips of emitters having cylindrical or similar (e.g., pyramidal) symmetry. The process will sharpen tips down to radii of less than 12 nm with an included angle of about 20 degrees. Because the ions are incident along or near the longitudinal axis of each emitter, the tips of gated arrays can be sharpened by high-energy ion beams rastered over the arrays using standard ion implantation equipment.
    Type: Grant
    Filed: June 10, 1997
    Date of Patent: November 30, 1999
    Assignee: The Regents of the University of California
    Inventor: Ronald G. Musket
  • Patent number: 5993277
    Abstract: A method for manufacturing a field emission device includes the steps of: forming a first sacrificial film on a substrate; forming a recess which has side walls almost perpendicular to the first sacrificial film and which extends up to the substrate; forming a second sacrificial film on the first sacrificial film and in the recess; etching back the second sacrificial film so as to leave side spacers on the side walls of the recess; forming a first conductive film as a gate electrode on the first sacrificial film, the side spacers and an exposed part of the substrate; etching back the first conductive film so as to expose the substrate at the bottom of the recess; forming a first insulation film on the first conductive film; forming a second conductive film as an emitter electrode on the first insulation film; and exposing an end portion of the second conductive film.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: November 30, 1999
    Assignee: Yamaha Corporation
    Inventor: Atsuo Hattori
  • Patent number: 5981304
    Abstract: Self-alignment process usable in microelectronics to obtain alignment of at least one group of holes, one of said holes (or large diameter hole) being formed in an upper level and the other hole (or small diameter hole) being formed in a lower level of a stacked structure.
    Type: Grant
    Filed: December 17, 1997
    Date of Patent: November 9, 1999
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Aime Perrin, Brigitte Montmayeul
  • Patent number: 5975976
    Abstract: Structured surface, having a support layer and, connected electrically to it, peak-shaped elements, each peak-shaped element exhibiting a cylindrical or conical shaped stem region adjacent to the support layer and at least two, preferably 2 to 4 peaks at the free end of the stem region. The structured surface is suitable in particular as electron emission source for ultra-flat image screens, for electron lithography or for scanning or transmission microscopy.
    Type: Grant
    Filed: April 28, 1998
    Date of Patent: November 2, 1999
    Assignee: Alusuisse Technology & Management Ltd.
    Inventors: Kurt Sekinger, Harald Fuchs, Jean-Francois Paulet, Roman Fuchs
  • Patent number: 5971825
    Abstract: A method of manufacturing a field emission element includes the steps of: forming an overhang portion on a substrate, the overhang portion having a cross section with confronting two parts; depositing a first sacrificial film on the overhang portion with the two parts, the first sacrificial film having a cross section with two parts; depositing a reaction control film on the first sacrificial film with the two parts, the first sacrificial film controlling chemical reaction of the first sacrificial film and having a cross section with two parts; chemically react the first sacrificial film so as to make the two parts of the first sacrificial film contact each other; depositing a field emission cathode film on the contacted area of the first sacrificial film; and exposing a tip of the field emission cathode film.
    Type: Grant
    Filed: April 3, 1997
    Date of Patent: October 26, 1999
    Assignee: Yamaha Corporation
    Inventor: Atsuo Hattori
  • Patent number: 5967873
    Abstract: Method and apparatus are presented for the generation, regeneration, and transplantation of field enhancing whiskers to provide for an improved cathode in flat panel displays in particular, and in other applications. Such applications comprise devices in which there is an emissive cathode structure for producing electrons. There are dear advantages for the instant invention in the case of a flat panel display which requires a relatively large cathode area, because the present invention avoids excessive power loss due to radiation and conduction loss by permitting operation of the cathode at a significantly lower temperature than if it operated solely as a thermionic emitter. The combination of moderately elevated temperature and enhanced electric field allows the advantages of thermo-field assisted emission.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: October 19, 1999
    Inventor: Mario Rabinowitz
  • Patent number: 5964629
    Abstract: To form a silicon tip having an undercut, a photoresist pattern having a vertical profile or a positive profile is formed on a silicon substrate and an under-cuted isotropic etching process is then performed using the photoresist pattern as a mask. First and second insulation films are formed on the silicon tip and the silicon substrate except for the silicon tip. The first insulation film is then separated from the second insulation film.
    Type: Grant
    Filed: November 21, 1996
    Date of Patent: October 12, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jong Moon Park, Jin Keon Ku, Ki Hong Kim, Yeong Cheol Hyeon, Min Park
  • Patent number: 5966588
    Abstract: An improved field emission display device fabrication method which adopts both a silicon wafer direct bonding method and a mold method so as to fabricate an improved field emission display device, which includes the steps of a first step which forms a tip array by a molding method; and a second step which bonds the tip array to a second semiconductor substrate.
    Type: Grant
    Filed: April 4, 1996
    Date of Patent: October 12, 1999
    Assignee: Korea Institute of Science and Technology
    Inventors: Byeong Kwon Ju, Myung Hwan Oh, Yun Hi Lee, Nam Yang Lee
  • Patent number: 5965218
    Abstract: A method for manufacturing probe tips suitable for use in an atomic force microscope (AFM) or scanning tunneling microscope (STM) begins by depositing a layer of a first material over a substrate and then patterning the layer of the first material to define apertures wherever probe tips are to be formed. Next, a layer of a second material is deposited using an unbiased high density plasma chemical vapor deposition (HDPCVD) process to form sharp probe tips in the apertures in the layer of the first material. The HDPCVD process also forms a sacrificial layer of the second material on top of the portions of the first material not removed by the patterning step. The sacrificial layer at least partially overhangs the apertures in the first material, forming a shadow mask during the deposition process which gives rise to a sharp probe profile.
    Type: Grant
    Filed: March 18, 1997
    Date of Patent: October 12, 1999
    Assignee: VLSI Technology, Inc.
    Inventors: Subhas Bothra, Ling Q. Qian
  • Patent number: 5953580
    Abstract: A method of manufacturing a vacuum device utilizing a sputtering process is disclosed. According to the present invention, the vacuum device includes a silicon substrate. An emission electrode having a sharp ended tip is formed by etching the silicon substrate. An insulating layer is formed on the silicon substrate so as to make the entire structure of the emission electrode to be exposed, with the emission electrode being surrounded by the insulating layer. A gate electrode is then formed adjacent to the sharp ended tip of the emission electrode. According to the present invention, it has advantages that the emission electrode is manufactured by forming the silicon pillar using the isotropic etching and anisotropic etching and the gate electrode can be easily formed adjacent to the emission electrode by using the sputtering method after the gate insulating layer is formed.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: September 14, 1999
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung Weon Kang, Jin Ho Lee, Kyoung Ik Cho, Hyung Joun Yoo
  • Patent number: 5948228
    Abstract: A method of fabricating a channel structure for a PALC display panel comprises providing a channel member having channels formed in its upper surface and two electrodes in each channel, masking one electrode in each channel while leaving the other electrode unmasked, depositing material on the unmasked electrode in each channel, and removing the mask from masked electrode in each channel.
    Type: Grant
    Filed: September 9, 1997
    Date of Patent: September 7, 1999
    Assignee: Tektronix, Inc.
    Inventors: Robert D. Hinchliffe, Mark W. Roberson, Dorothy L. Blazo, Donald E. Kephart
  • Patent number: 5948465
    Abstract: A process for making a field emitter cathode is disclosed, which comprises the steps of depositing a solution of a metal compound in a solvent and an electron emitting powder onto the surface of a substrate and heating the substrate containing the solution and the electron emitting powder deposited thereon for a time and temperature sufficient for the metal compound to be completely reduced to a metal.
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: September 7, 1999
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Graciela Beatriz Blanchet-Fincher, William Leo Holstein, Shekhar Subramoney, Norman Herron
  • Patent number: 5944573
    Abstract: A process for depositing diamond crystals onto a field emission cathode. The process involves providing a cathode having a substrate, a gate layer and a plurality of emitters electrically insulated from the gate layer. An electric bias is applied to the gate layer and a ground potential is applied to the emitters. A heat source is positioned adjacent the cathode, and the cathode is exposed to a field of ions for a sufficient period to at least partially clean the emitters. A carbon containing gas is added to the atmosphere adjacent to the cathode such that carbon ions are dissociated from the gas and deposited on the emitters to form a "soot". The temperature of the cathode is then adjusted to a level which allows formation of diamond film.
    Type: Grant
    Filed: December 10, 1997
    Date of Patent: August 31, 1999
    Assignee: BAV Technologies, Ltd.
    Inventors: Gerald T. Mearini, Robert E. Kusner
  • Patent number: 5944975
    Abstract: A method of fabricating an emitter plate 12 for use in a field emission device comprising the steps of providing an insulating substrate 18 and forming a first conductive layer 13 on the insulating substrate 18. This is followed by the steps of forming an insulating layer 20 on the first conductive layer 13 and forming a second conductive layer 22 on the insulating layer 20. Then, a plurality of apertures 34 are formed through the second conductive layer 22 and through the insulating layer 20. A lift-off layer 36 is then formed on the second conductive layer 22. The lift-off layer 36 is formed by a plating process wherein the plating bath has a pH between 2.25 and 4.5, and current densities of 1 to 2O mA/cm.sup.2. The method may further comprise depositing conductive material through the plurality of apertures 34 to form a microtip 14 in each of the plurality of apertures 34. The excess deposited conductive material 14' and the lift-off layer 36 are then removed from the second conductive layer 22.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: August 31, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Arthur M. Wilson, Chi-Cheong Shen, Saroja Ramamurthi
  • Patent number: 5945778
    Abstract: An electron emitter formed with a layer of diamond-like carbon having a diamond bond structure with an electrically active defect at an emission site. The electrically active defect acts like a very thin electron emitter with a very low work function and improved current characteristics, including in improved saturation current.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: August 31, 1999
    Assignee: Motorola, Inc.
    Inventor: James E. Jaskie
  • Patent number: 5941748
    Abstract: A lateral field emission display in which a cathode and anode are laterally arrayed, and a fabricating method thereof, since the micro tip is formed to be sharp through the reactive ion etching method, efficiency of electron emission is better than a conventional wedge-type tip. Also, since focusing of an electron beam is accurately controlled, a relatively low-voltage driving is possible. Further, since the first gate is further provided above the cathode and the anode is formed to be higher than the second gate, a trace control of an electron-beam emitted from the micro tip is easy and focusing efficiency of the emitted electron beam to the anode is also improved.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: August 24, 1999
    Assignee: Samsung Display Devices Co., Ltd.
    Inventor: Jong-min Kim
  • Patent number: 5938493
    Abstract: A method of fabricating electron emission structures 30 having enhanced emission characteristics. The method comprising the steps of providing a substrate 10 having electron emission structures 5 thereon and having a gate layer 6 over the electron emission structures 5. Then modifying the electron emission structures with a focused beam to create modified electron emission structures 30 with enhanced emission efficiency.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: August 17, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Kenneth G. Vickers
  • Patent number: 5936354
    Abstract: A field emission display (100) includes a cathode plate (104) having a plurality of electron emitters (112) and ballast resistors (118), an anode plate (120) having an anode (124), and a temperature compensation circuit (130) having an input (142), an output (134), and a current output (138). Input (142) is connected to unregulated voltage (132), output (134) is connected to gate (116), and current output (138) is connected to temperature sensing element (148). Preferably, temperature sensing element (148) is mounted on cathode plate (104) and matches the temperature vs. resistance characteristics of ballast resistors (118). Temperature compensation circuit (130) outputs current (220) to temperature sensing element (148) and receives ballast voltage (230) from temperature sensing element (148) as a function of temperature of cathode plate (104).
    Type: Grant
    Filed: November 2, 1998
    Date of Patent: August 10, 1999
    Assignee: Motorola, Inc.
    Inventors: Robert T. Smith, Ken K. Foo
  • Patent number: 5928048
    Abstract: A method of manufacturing a field emission element including the steps of: forming an opening in a partial region of a first film formed on an underlying substrate and thereafter forming a first sacrificial film; etching back the first sacrificial film to expose the surface of the first film and leave a side spacer on the side wall of the opening, the side spacer being made of the first sacrificial film, and continuing to etch back the first sacrificial film to form a recess in the underlying substrate; depositing a second sacrificial film on the recess, the side spacer and the first film to a thickness larger than the radius of curvature of a rounded corner at the bottom of the recess, to form a cusp on the surface of the second sacrificial film, the cusp having a sharp apex at a deepest point where side walls of the second sacrificial film as viewed in cross section contact at the first time; and forming a field emission cathode electrode having a sharp apex by depositing a conductive film on the second sac
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: July 27, 1999
    Assignee: Yamaha Corporation
    Inventor: Atsuo Hattori
  • Patent number: 5924903
    Abstract: A method is for use in fabricating a cold cathode comprising a sharp emitter (3) having a sharp tip that is formed on a silicon substrate 1b. The method comprises a first step of forming an intermediate emitter on the silicon substrate. The intermediate emitter has first and second emitter regions (33,34). The second emitter region is positioned under the first emitter region and has a width (diameter) larger than that of the first emitter region. The method further comprises a second step of processing the intermediate emitter into the sharp emitter by oxidation.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: July 20, 1999
    Assignee: NEC Corporation
    Inventor: Hisashi Takemura
  • Patent number: 5923948
    Abstract: An improved method for sharpening emitter sites for cold cathode field emission displays (FEDs) includes the steps of: forming a projection on a baseplate; growing an oxide layer on the projection using a low temperature oxidation process; and then stripping the oxide layer. Preferred low temperature oxidation processes include: wet bath anodic oxidation, plasma assisted oxidation and high pressure oxidation. These low temperature oxidation processes grow an oxide film using a consumptive process in which oxygen reacts with a material of the projection. This permits emitter sites to be fabricated with less distortion and grain boundary formation than emitter sites formed with thermal oxidation. As an example, emitter sites can be formed of amorphous silicon. In addition, low temperature materials such as glass can be used in fabricating baseplates without the introduction of high temperature softening and stress.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: July 13, 1999
    Assignee: Micron Technology, Inc.
    Inventor: David A Cathey, Jr.
  • Patent number: 5921838
    Abstract: A method for protecting extraction electrodes (140) during processing of Spindt-tip field emitters (150, 155) includes the steps of: (i) depositing a parting layer (170) on the extraction electrodes (140) and in an interspace region (145) defined by the extraction electrodes (140), (ii) sharpening the Spindt-tip field emitters (150), (iii) depositing a layer (180) of emission-enhancing material on the sharpened field emitters (155) and on the parting layer (170), and (iv) removing the parting layer (170), thereby lifting off the emission-enhancing material from the extraction electrodes (140) and from the interspace region (145), but not from the sharpened field emitters (155).
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: July 13, 1999
    Assignee: Motorola, Inc.
    Inventors: Sung P. Pack, Patricia A. Norton, Robert F. Woodburn, Jr.
  • Patent number: 5920151
    Abstract: An electron-emitting device contains an electron focusing system (37 or 37A) formed with a base focusing structure (38 or 38A), a focus coating (39 or 39A), and an access conductor (106 or 116). The focus coating overlies the base focusing structure and extends into a focus opening (40). The access conductor is electrically coupled to the lower surface of the focus coating. A potential for controlling the focusing of electrons that travel through the focus opening is provided to the focus coating via the access conductor. The focus coating is typically formed by an angled deposition technique.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: July 6, 1999
    Assignee: Candescent Technologies Corporation
    Inventors: Roger W. Barton, Stephanie J. Oberg, N. Johan Knall, Christopher J. Spindt, Duane A. Haven
  • Patent number: 5919070
    Abstract: A vacuum state microelectronic device comprising at least a cathode, an anode, and a grid, disposed in a cavity, and formed by the wafer bonding of two planar substrates. The technology permits multiple vacuum state microelectronic devices (vacuum tubes) to be arrayed on a single substrate in an integrated manner.
    Type: Grant
    Filed: August 16, 1996
    Date of Patent: July 6, 1999
    Assignee: Philips Electronics North America Corporation
    Inventors: Babar A. Khan, David A. Cammack, Ronald Pinker
  • Patent number: 5916005
    Abstract: A high curvature diamond field emitter tip fabrication method includes forming on a substrate a diamond film composed of square (100) phase-oriented facets and (111) phase-oriented facets distributed thereabout and columnar diamond particles having defect density differences between the diamond formed beneath the (100) and (111) diamond growth facets, and etching the diamond film using a oxygen-containing gas plasma. Further, the method includes forming on a substrate a diamond film composed of square (100) facets and (111) facets distributed thereabout and columnar diamond particles having defect density differences between the diamond formed beneath the (100) and (111) diamond growth facets, forming a supporting film on the diamond film, removing the substrate therefrom, and etching the diamond film using an oxygen-containing gas plasma after any one of the previously described steps.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: June 29, 1999
    Assignee: Korea Institute of Science and Technology
    Inventors: Young-Joon Baik, Kwang Yong Eun
  • Patent number: 5917284
    Abstract: A conductive refractory compound coating for electrodes is sputter resistant, very resistant to oxidation, and easy to apply by way of electrophoresis or screen printing. This structure is further enhanced by the presence of surface particles of electrically nonconductive ceramic material. When the cathode electrode is energized, electrically nonconductive material is penetrated by the electric field, which attracts secondary electrons out of the cathode electrode, thereby increasing the cathode's efficiency as an emitter of secondary electrons. More specifically, cathode electrodes are used in a plasma addressing structure. The coating is formed by approximately 5 nm particles, each comprised of a fused matrix of conductive and nonconductive particles co-deposited with frit particles by either electrophoresis or "silk" screening. The coating is subsequently baked to fuse the frit and bond the electrophoretically deposited particles to the electrodes.
    Type: Grant
    Filed: July 31, 1997
    Date of Patent: June 29, 1999
    Assignee: Tektronix, Inc.
    Inventors: John S. Moore, William W. Stein, Donald E. Kephart
  • Patent number: 5911615
    Abstract: A method for use in manufacture of field emitter devices is provided specifically for forming electron emitter tips in a doped semiconductor substrate. The method comprises the following steps: forming a depression around an emitter area in the substrate; doping the substrate in the depression; and expanding the dopant in the depression into the emitter area.
    Type: Grant
    Filed: January 7, 1997
    Date of Patent: June 15, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Kevin Tjaden, John K. Lee
  • Patent number: 5902165
    Abstract: An electron emitter plate (110) for an FED image display has an extraction (gate) electrode (22) spaced by an insulating spacer (125) from a cathode electrode including a conductive mesh (18). Arrays of microtips (14) are located in mesh spacings (16), within apertures (26) formed in extraction electrode (22) and subcavities (141) formed through apertures (26) in insulating spacer (125). Subcavities (141a) are open to row-adjacent and column-adjacent subcavities (141b, 141c) to form larger main cavities (144). Posts (143) of insulating spacer (125) separate diagonally-adjacent cavities (141d). Subcavities (141) are formed by over-etching a layer of insulating spacer material (25) through apertures (26) before or after forming microtips (14) through the same apertures (26). Over-etching reduces the dielectric constant factor of gate-to-cathode capacitance in the finished structure.
    Type: Grant
    Filed: July 10, 1996
    Date of Patent: May 11, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Jules D. Levine, Kenneth G. Vickers
  • Patent number: 5898258
    Abstract: A field emission type cold cathode apparatus comprises a mother material layer made of an n-type silicon layer, a conical emitter having an arcuate side surface, an insulating layer formed in a surface region of the mother material layer in a manner to define the arcuate side surface of the emitter and having a concave portion formed to expose the tip portion of the conical emitter, the depth of the concave portion being determined such that the lower portion of the emitter covering a region more than half the height of the emitter is buried in the insulating layer, and a gate electrode formed over the insulating film in a manner to surround the emitter and having an open portion exposing the tip portion of the emitter, the diameter of the open portion being smaller than the diameter in the base portion of the emitter.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: April 27, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Sakai, Tomio Ono, Li Zhang