Abstract: A local oscillator provides an in-phase local oscillating signal and quadrature-phase signal to first and second mixers outputting an input signal with a mixed in-phase local oscillating signal and quadrature-phase local oscillating signal, respectively. The oscillator comprises a local oscillator having first and second delay cells and outputting said in-phase local oscillating signal and said quadrature-phase local oscillating signal; and a correction circuit for controlling phase matching characteristics, said correction circuit setting bias current flowing in said first and second delay cells of said local oscillator as being to be different. In another embodiment, the phase matching characteristic is controlled by setting the bias voltage applied to the first and second delay cells as being to be different, by setting the width of the active device included in the first and second delay cells dells as being to be different, or by setting impedance of passive device to be different.

Abstract: An analog open-loop voltage controlled oscillator (VCO) calibration circuit and method for selecting the frequency of the VCO for a phase locked loop (PLL). A frequency divider module produces a 50% duty cycle divided local oscillation and a 50% duty cycle divided reference signal, wherein the divided signals are substantially equal. A period-to-voltage conversion module converts the divided local oscillation signal and the divided reference signal to voltages proportional to the divided signals. A comparator module produces a frequency adjustment signal based on a comparison of the proportional voltages and couples the frequency adjustment signal to a logic module which produces a frequency compensation signal based on the frequency adjustment signal. The frequency compensation signal functions to adjust the configuration of switched capacitors in a capacitor bank, coupled to the VCO tuned circuit, until the divided local oscillation signal is substantially equal to the divided reference signal.

Abstract: It is possible to achieve the miniaturization and the power saving of a hardware circuit as a multi-band radio signal transmitter/receiver, which can carry out a communication through a signal of a first communication method of transmitting and receiving a signal modulated by using information with regard only to a phase, for example, GSM/DCS, and a signal of a second communication method of transmitting and receiving a signal modulated by using an information of a phase and an amplitude, for example, UMTS (W-CDMA). A signal of PLL for a different reception channel is used as a local oscillation signal for a direct conversion reception, by using an image removing mixer or a reproduction dividing circuit, in each of GSM/DCS and UMTS modes, by switching a frequency of PLL in a transmitting IF signal in GSM/DCS/UMTS for each method, in order to generate a receiving signal used in GSM/DCS/UMTS.

Abstract: A radio communication unit employs passive devices and a loop filter to receive a coded frequency modulated wakeup or synchronization signal that enables the receiving radio unit and initiates communications. The loop filter simultaneously tracks phase and frequency and provides smoothing to enable synchronization with weak signals (e.g., signals that typically do not enable a standard phase locked loop (PLL) to lock). In particular, when the communication unit is in a standby mode, the passive circuits of the present invention are receiving energy from a unit antenna and initially function as a phase locked loop (PLL) to lock onto an incoming signal. The wakeup or synchronization signal includes a series of tones at different frequencies, where the specific sequence is prearranged between the transmitting and receiving units. When each tone in the sequence has been detected by the receiving unit, the unit is enabled for communications.

Abstract: In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.

Abstract: In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.

Abstract: A variable frequency oscillator comprising: an oscillatory circuit for generating a periodic output dependent on the capacitance between a first node and a second node of the circuit, and having a capacitative element connected between the first node and the second node; the capacitative element comprising: a variable capacitance unit, the capacitance of which is variable for varying the frequency of the output and a plurality of finite capacitances each being selectively connectable in parallel with the variable capacitance unit between the first node and the second node to trim the frequency of the output.

Abstract: An integrated demodulator tuning circuit (10, 60) receives differential currents at input terminals (12, 46) and provides an AFC signal at an output terminal (48). The AFC current characteristic has a dead band (72) in the output current generated when the integrated demodulator tuning circuit (10, 60) operates under the condition where the difference between the currents supplied at the input terminals (12 and 46) is at or below a set threshold value. The set threshold value is determined by the relative sizes of the transistors (14, 16 and 20, 36, 38 and 40) that form the current mirrors connected to the input terminals (12, 46).

Abstract: A frequency offset correction value estimation section (21) receives a signal including a predetermined fixed pattern from a transmission side, thereafter, selects a combination of fixed patterns used in a process of estimating a frequency offset is selected depending on the state of a channel, and an estimation result of the frequency offset calculated by the combination of the fixed patterns is output as a correction value of a determined frequency offset. A frequency offset correction section (22) receives the received signal obtained after the correction is performed for correcting a frequency offset of the received signal on the basis of the correction value, and an equalizer (23) demodulates the received signal by using a predetermined algorithm.

Abstract: The invention concerns a mixer, in particular for an dual conversion receiver. The mixer includes a first variable transconductance stage (A) controlled by a high frequency carrier signal, this first stage including first (37) and second (38) terminals delivering a first signal; and a second stage (B) connected to said first terminal of the first stage including, in parallel, first (T32) and second (T33) switching means respectively controlled by first (in2) and second (in2b) phase opposition control signals at a first intermediate frequency (IF1), these first and second switching means being powered by a substantially equal current supplied by polarisation means (34). The mixer according to the invention is characterised in that it further includes means (T36) for modulating said first signal delivered by said first stage by means of a third control signal (in3) at a second intermediate frequency (IF2).

Abstract: A zero or near zero IF frequency changer for use in a digital tuner comprises multipliers which receive the RF input signal from an input. The multipliers receive quadrature local oscillator signals from a first oscillator of an arrangement which comprises first and second phase-locked loops. The first phase-locked loop comprises a programmable divider, a comparator and a control loop so that the first oscillator is phase-locked to a second oscillator. A second phase-locked loop comprises the second oscillator and a synthesizer containing a reference oscillator to which the second oscillator is phase-locked. The output frequency of the second oscillator is in a frequency band which is outside the RF input frequency band of the frequency changer.

Abstract: A voltage controlled oscillation device includes a voltage controlled oscillator, fixed-frequency oscillator, frequency mixer, and frequency selector. The voltage controlled oscillator changes the output signal frequency in the microwave band in accordance with the input voltage of a frequency control signal. The fixed-frequency oscillator has a fixed oscillation frequency higher than that of the voltage controlled oscillator. The frequency mixer mixes the output signal from the fixed-frequency oscillator and the output signal from the voltage controlled oscillator and outputs the sum frequency and difference frequency between the two signals. The frequency selector selects and outputs one of the sum frequency and difference frequency contained in the output signal from the frequency mixer.

Abstract: For use in an orthogonal frequency division multiplexing (OFDM) transceiver, a multimode local oscillator circuit and a method of operating the same. In one embodiment, the circuit includes: (1) a single sideband mixer having an output, first and second inputs and a local oscillator input and (2) a signal generator, coupled to the single sideband mixer, for alternatively providing to the first and second inputs: (2a) constant values to cause the single sideband mixer to generate a first receiver local oscillator signal for operating the OFDM transceiver as a zero intermediate frequency receiver and (2b) a first orthogonal baseband signal to cause the single sideband mixer to generate a second receiver local oscillator signal for operating the OFDM transceiver as a low intermediate frequency receiver.

Abstract: A frequency modulation system is disclosed which includes a voltage-controlled oscillator (VCO) 43 and a phase detector 47 configured to receive an output signal from the VCO. The phase detector is arranged to output an error signal representing the phase difference between the signal from the VCO and a reference signal. The system also includes control means 62 arranged to monitor the error signal to derive an indication of the frequency deviation of the VCO, and, in accordance with this derivation, to maintain the frequency deviation of the VCO substantially constant.

Abstract: The present invention provides for a system for operating a communication device (20) for reception of scheduled intermittent information messages (22) with a dual mode timer (70) that extends battery life. A controller (50) schedules the timer (70) to power down all idle components of the device (20) between message receptions in a power saving sleep mode to conserve battery power. During active mode when the device is fully active in reception of messages, the timer (70) uses a reference oscillator (90) with a relatively high frequency to support digital processing by the receiver (26). During sleep mode when only the timer is powered on, a much lower frequency sleep oscillator (96) is used to maintain the lowest possible level of power consumption within the timer itself. The timer (70) has provision for automatic temperature calibration to compensate for timing inaccuracies inherent to the low-power low-frequency crystal oscillator (96) used for the sleep mode.

Abstract: To ensure frequency stability of a radio frequency in a radio communication apparatus for generating the radio frequency synchronizing with a transmission path frequency of digital data transmitted from a wire digital transmission path and so on. Concerning influence of a difference of a transmission path frequency that obstructs stability of a radio carrier frequency, the difference of a transmission path frequency 12b is compared with a high-stability radio reference clock 22a, the difference frequency 17a is detected by a counter 71, and frequency offset of a radio-station-transmission signal of a local oscillator 61 is made on the basis of the differential frequency. By the operation, the influence of the difference of the transmission path frequency that obstructs the stability of the radio carrier frequency 63a can be compensated.

Abstract: An analog demodulator used in a low IF receiver to down-convert a pair of quadratureIF signals and to perform image-rejection operations. The analog demodulator includes at least one first calibration apparatus and/or at least one second calibration apparatus so that the analog demodulator can reduce DC offset that would cause LO leakage in the low IF receiver by using the first calibration apparatus and/or the second calibration apparatus. The analog demodulator further includes a filtering device connected to a LO generator for removing the 3rd and 5th order harmonic components.

Abstract: The present invention provides for a cellular radio communications device arranged for use with first and second communication systems having different timebases, and including means for determining the offset between the timebase at a serving cell of the first system and the timebase of a neighbouring cell of the second system, the said means for determining including timing means being arranged to be controlled by frame-boundary signals of the first and second communication systems.

Abstract: An intermediate frequency signal SIF is demodulated and the noise component contained in a null portion (no-signal portion) is detected as the noise component contained in a signal of the sub-carrier frequencies. The frequency f0 of a reference frequency signal LO of a local oscillator 24 is feedback-controlled in accordance with the noise component thus detected. Further, the frequency f0 of the reference frequency signal LO is feedback-controlled in accordance with an error rate detected by an error correction section 23. Thus, the sub-carriers within the intermediate frequency signal SIF subjected to the frequency conversion by a mixer 16 based on the reference frequency signal LO thus feedback-controlled is separated from the noise component on the frequency axis. The intermediate frequency signal SIF is subjected to the Fourier transformation by a digital mixer/FFT calculation section 21, so that the noise component can be suppressed.

Abstract: Disclosed is an amplifier apparatus that corrects mismatching of the filter transmission characteristic due to a change in the temperature of the amplifier apparatus itself and thereby stably amplifies the high-frequency signal. The amplifier apparatus converts a signal to be processed into one having an intermediate frequency band to thereby execute amplification processing.

Abstract: A receiver system (10) includes a first stage of modulation (46, 51) which modulates a radio-frequency input signal (17), and a second stage of modulation (56, 61, 66, 71) which modulates outputs from the first stage. Combining circuits (76, 77) combine selected outputs of the second stage to produce two outputs (18, 19) from the receiver system. The first stage receives modulating signals (22, 23) from a first oscillator (21), and the second stage receives modulating signals (27, 28, 32, 33) from second and third oscillators (26, 31). The second and third oscillators each operate at a substantially lower frequency than the first oscillator. The phase difference between the modulating signals produced by each of the second and third oscillators is adjusted so that there is minimum image power in each of the system outputs (18, 19), even if the modulating signals from the first oscillator are not in phase quadrature.

Abstract: The present invention relates to a demodulation structure and method for downconverting and demodulating a digitally modulated signal So, with a local oscillator means (1; 5; 8) for providing a local oscillator signal Slo a mixer means (2) for mixing said local oscillator signal Slo and said digitally modulated signal S0 in order to obtain a mixed signal, a lowpass filter means (3) for lowpass filtering the mixed signal from the mixer means (2) and an analog-to-digital converting means (4) for converting the filtered signal from the lowpass filter means (3) into a downconverted and demodulated digital signal Sl, whereby the local oscillator signal is set in respect to the modulated digital signal so that the downconverted and demodulated digital signal output from the analog-to-digital converting means comprises to serially arranged information parts. The present demodulation structure provides a very simple structure with improved amplitude and phase imbalances.

Abstract: An electronic circuit includes a frequency conversion device (4), an oscillator (6), a band-pass filter (8), and a controller (14). The oscillator (6) is connected to the frequency conversion device (4), and the frequency conversion device (4) is connected to the band-pass filter (8). The frequency conversion device (4) is arranged to receive a first signal (S1) at a frequency (ft), and to transform the first signal (S1) into an intermediate frequency signal (S2) at an intermediate frequency (fi) by applying a selection frequency (floc) from the oscillator (6). The band-pass filter (8) is arranged to receive the intermediate signal (S2) and to perform a band-pass filtering at a centre frequency (fbpf) and with a bandwidth (fw), the centre frequency (fbpf) being equal to the intermediate frequency (fi) at a predetermined working temperature of the band-pass filter (8).

Abstract: A method is provided for selecting the frequencies of local oscillators and intermediate frequency converters of a receiver that selects the frequency for a first intermediate frequency converter, selects a frequency for a first local oscillator above the frequency of the first intermediate frequency converter to provide an overlapping harmonic first gap, and selects a frequency for a second local oscillator to provide a harmonic gap overlapping said first gap.

Abstract: There is described an FM receiver (29) including; an antenna (2) able to receive a high frequency signal from a transmitter; a high frequency stage (3); an oscillator (5); a mixer unit (30) able to provide a signal (S6) at an intermediate frequency (fIF); an FM demodulation stage (8); and an automatic frequency control stage (36) able to control the oscillator, so as to keep said intermediate frequency (fIF) of said signal (S6) constant. This receiver further includes a locked loop (32) arranged to enslave said intermediate frequency (fIF) from a pilot frequency (fp) present in the demodulated signal. One advantage of such a locked loop is that the intermediate frequency is enslaved so that the aliasing phenomenon does not prevent demodulation of the signals containing the RDS data.

Abstract: A system and method for a multi-band direct conversion wireless communication receiver is presented. The system incorporates a low noise amplifier (LNA) configured to amplify received RF signals, a local oscillator (LO) configured to output a frequency, and I and Q channel mixers. Each mixer has a first input operatively coupled to the LNA, a second input operatively coupled to the LO output, and an output. The system further includes an adjustment mechanism configured to adjust drive level of the LO depending on a level of jammers detected by the receiver. Thus, the receiver may operate in multiple wireless communication bands and modes and meet the associated specifications.

Abstract: A radio transmission apparatus for performing radio transmission by use of a plurality of carrier frequencies, including signal processing systems for respective channels. Each signal processing system includes a transmission signal generator that modulates transmission data with a predetermined carrier frequency signal to generate a transmission signal, an amplifier that amplifies the transmission signal, and a variable band-pass filter connected to the output of the amplifier. The outputs of the signal processing systems are combined with a radio transmission signal. At least the center frequency of a pass band of the variable band-pass filter can be changed, with the pass band determined based on the carrier frequency signal of the channel. The apparatus also includes a fault detector configured to detect a fault of each variable band-pass filter.

Abstract: The method determines a deviation between a modulation frequency, combined with a first baseband signal to form a transmitted signal and a frequency used by the receiver to form a second baseband signal from a received signal, in order to adjust the frequency used by the receiver. Knowing a time segment of the first signal and the time position of a corresponding segment of the second signal, whereby the segments comprise N samples at a sample frequency Fe, a frequency transform Y(f), of size N, of the product of the complex conjugate of said segment of the first signal by the corresponding segment of the second signal is calculated, and the frequency deviation &Dgr;f which makes the frequency transform Y(f) as close as possible to C.

Abstract: A phase-locked loop circuit includes an array of selectable capacitors formed within the phase-locked loop circuit to enable the phase-locked loop circuit to provide a degree of coarse frequency control by adding or removing capacitors and a degree of fine frequency control by sinking or sourcing current from a charge pump into a loop filter. A finite state machine is provided within a voltage controlled oscillator calibration circuit that communicates with an external baseband processor to initiate a calibration process, and further to determine how many capacitors of an array of capacitors if formed within the phase-locked loop circuit should be coupled to provide the coarse frequency control.

Abstract: An FSK receiving apparatus has, as means for performing offset correction upon a demodulated base band signal, a second low pass filter 9 for integrating the demodulated base band signal; a window comparator for detecting a DC offset component in an output voltage from the second low pass filter 9; an up/down counter 11 for incrementing or decrementing a count value on the basis of the output of the window comparator 10; a clock generating portion 13 for generating a timing signal for counting operation in the up/down counter 11; a reference voltage generating portion 12 for generating a reference voltage for a comparator 7 on the basis of the output of the up/down counter 11; and a charging circuit 22 for supplying a reference voltage in the last frame to the second low pass filter 9 so as to charge the second low pass filter 9 with the last-frame reference voltage and set an initial value of the second low pass filter 9.

Abstract: The present invention eliminates the need for an anti-aliasing filter in a receiver that employs an analog-to-digital converter. By maintaining a predetermined relationship between a local oscillator frequency and the sampling frequency of the analog-to-digital converter, aliasing that would normally occur in the desired pass band is avoided. More specifically, the frequency of the periodic signal provided to the mixer is an integer multiple of half the sampling rate of the analog-to-digital converter. In a preferred, non-limiting example embodiment, the sampling rate of the analog-to-digital converter FADC and the frequency of the local oscillator FLO are related by the following: FLO=n * FADC/2, where n is any positive integer.

Abstract: A method and system for receiving a signal in a received frequency and shifting the received frequency to become a desired frequency is provided. The system includes a controllable oscillator for generating a first internal frequency, a frequency estimating unit connected to the controllable oscillator, a first frequency shift unit, connected to the controllable oscillator and to the frequency estimating unit, for shifting the received frequency according to the first internal frequency, thereby obtaining an initially shifted frequency and a second frequency shift unit connected to the first frequency shift unit and the frequency estimating unit for shifting the initially shifted frequency. The frequency estimating unit determines a total frequency shift value from the desired frequency, the received frequency and the first internal frequency and it also determines a first frequency shift value and a second frequency shift value from the total frequency shift value.

Abstract: Data counters and perform a counting operation which is synchronized with the respective timing of receiving multiplex data from a VICS data broadcasting station and a D-GPS data broadcasting station. While receiving the multiplex data from the VICS data broadcasting station, based on an output C2 of the data counter and a BIC detection output BP, block synchronization is detected. When the broadcasting station is switched from the VICS data broadcasting station to the D-GPS data broadcasting station, an output C2 of the data counter is selected in response to a control signal CONT and block synchronization is detected based on an output C2 and an output BP. Further, an output C1 is always inputted to the block counter. Thus, even while receiving the multiplex data from the D-GPS data broadcasting station, frame synchronization of the multiplex data of the VICS data broadcasting station is detected without causing miscounting.

Abstract: The present invention provides for a system for operating a communication device (20) for reception of scheduled intermittent information messages (22) with a dual mode timer (70) that extends battery life. A controller (50) schedules the timer (70) to power down all idle components of the device (20) between message receptions in a power saving sleep mode to conserve battery power. During active mode when the device is fully active in reception of messages, the timer (70) uses a reference oscillator (90) with a relatively high frequency to support digital processing by the receiver (26). During sleep mode when only the timer is powered on, a much lower frequency sleep oscillator (96) is used to maintain the lowest possible level of power consumption within the timer itself. The timer (70) has provision for automatic temperature calibration to compensate for timing inaccuracies inherent to the low-power low-frequency crystal oscillator (96) used for the sleep mode.

Abstract: An integrated receiver mixer system is disclosed wherein the plurality of wireless receivers is remotely controlled, and retained in synchronism, via reference and control signals outputted by the system mixer. Further, pairs of receivers are connected to each other, and to the mixer, in a manner which minimizes the requisite cabling therebetween.

Abstract: An analog circuit for receiving satellite signals through an antenna. The circuit includes frequency transposition circuits and an analog/digital converter. Each frequency transposition circuit includes at least two frequency dividers of which due first is programmable so as to provide division ratios 140 and 143. The other divider provides one of the division ratios of 10 or 11. A third divider provides ratios of 3, 5, 7 or 8. These division ratios enable a single analog integrated circuit topography to allow a large number of possible applications including civil or military receivers operating on the GPS constellation or on the GLONASS constellation.

Abstract: A plurality of transmitting and receiving stations are provided at randomly distributed locations within a telecommunication network, and switching circuitry is provided within the stations themselves for routing of calls between stations in the network utilizing other stations in the network for relaying of such calls where necessary. To this end each station incorporates a call routing control unit acting to select a further station to which a call from a source to a destination is to be transmitted for the purpose of relaying the call. The call routing control unit transmits an interrogation signal to be received by other stations in the network within range of the transmitting station, and the call routing control unit of each of the other stations transmits an acknowledgment signal when the station is available for relaying a call in response to the interrogation signal received from the station.

Abstract: A method of demodulating an FM carrier wave and an FM demodulation circuit are described which use a phase locked loop. The phase locked loop is tuned to a selected carrier wave frequency including the step of selecting a setting of the variable gain circuit in the phase locked loop to select desired loop gain.

Abstract: The invention provides an automatic frequency control (AFC) method and circuit for use with a receiver by which deterioration of the reception characteristic of the receiver due to frequency error of the reference oscillator (e.g. a VCO) of a quasi-synchronous detection circuit arising from initial deviation, aging, or temperature characteristics is suppressed. During operation of the receiver, only when frame synchronization is established, the set value that the frequency control circuit determines for the VCO is periodically stored into a non-volatile memory together with current ambient temperature information of the VCO.

Abstract: A double superheterodyne type microwave detector is constructed from a reception antenna; a first local oscillator; a second local oscillator; reception means for detecting microwaves having prescribed frequencies based on signals obtained by carrying out a first mixing in which the output of the first local oscillator is mixed with the microwaves picked up by the antenna, and a second mixing in which the signals obtained from the first mixing are mixed with the output of the second local oscillator; judgement means for judging whether or not an actual microwave signal which forms a detection target has been detected by the reception means; alarm means for outputting an alarm when the judgement means judges an actual microwave signal to have been received by the reception means; and first control means for suspending the first mixing when the reception means detects a microwave signal having a prescribed frequency; wherein the judgement of whether or not the prescribed frequency microwave signal detected by t

Abstract: A frequency stabilizer circuit in the form of a charge-pump phase-lock loop utilizing a MEMS capacitance device, preferably a tunable MEMS capacitor or a MEMS capacitor bank, which more rapid and with a greater precision determine the phase and frequency of a carrier signal so that it can be extracted, providing an information signal of interest. Such MEMS devices have the added advantage of providing linear capacitance, low insertion losses, higher isolation and high reliability, they run on low power and permit the entire circuit to be fabricated on a common substrate. The use of the MEMS capacitance device reduces unwanted harmonics generated by the circuit's charge pump allowing the filtering requirements to be relaxed or perhaps eliminated.

Abstract: A digital radio transmission and reception system capable of preventing shift of carrier by fading through receiving a modulated signal radio-transmitted, and then directly demodulating the signal.

Abstract: A multimode radio communication terminal includes a tunable source of transmit and/or receive local oscillator signals for transmitting and/or receiving channels of different frequency bands in at least two radio communication systems. The terminal includes, downstream of the tunable source, a switchable frequency changer implementing a fixed frequency change and selectively insertable so that, the source responding directly to the requirements of one radio communication system, insertion of the frequency changer renders it capable of responding to the requirements of another radio communication system using different frequency bands. This is achieved by virtue of a particular change to the frequency produced by the tunable source, effected by the frequency changer.

Abstract: A method and apparatus for reducing power consumption in a communication device. In a standby mode, a relatively high power clock with a high degree of accuracy is powered down and a lower power, low frequency clock is used to maintain system synchronization. Synchronization means are provided to improve the accuracy of the low frequency clock during the standby mode.

Abstract: A wideband phase-lock loop frequency synthesizer (200) used in a radio transceiver capable of being reconfigured to operate in either a transmit, receive, or battery save mode. The wideband phase-lock loop frequency synthesizer (200) includes, a divide-by-two divider (205), quadrature detector (204), offset VCO (209) and offset mixer (207) for generating a quadrature phase modulated signal. Moreover, a programmable filter (211) is used for removing predetermined harmonic components of the offset mixed signal enabling the synthesizer to operate over a wide frequency range.

Abstract: A synchronizing apparatus for a differential OFDM receiver that simultaneously adjust the radio frequency and sample clock frequency using a voltage controlled crystal oscillator to generate a common reference frequency. Timing errors are found by constellation rotation. Subcarrier signals are weighted by using complex multiplication to find the phase differentials and then the timing errors. The reference oscillator is adjusted using the timing errors. Slow frequency drift may be compensated using an integral of the timing error. Frequency offset is found using the time required for the timing offset to drift from one value to another.

Abstract: Signal processing apparatus (410) includes a phase-locked oscillator (200, 236, 310, 330, 390), having a closed loop with both forward (204) and feedback (206) paths, that is a part of a larger closed loop (438). The larger loop (438) is phase locked to the phase-locked oscillator (200, 236, 310, 330, 390) by a signal derived from the larger closed loop (438) that modulates the feedback path (206), and by an output frequency of the phase-locked oscillator (200, 236, 310, 330, 390) that is delivered to the larger loop (438). Modulating the feedback path (206) either adds pulses to the feedback path (206) or removes pulses, thereby causing irregularities in the flow of pulses. A low-pass filter (210) in the feedback path (206) obviates these irregularities, thereby also obviating incidental frequency modulation (IFM) in the output of the phase-locked oscillator (200, 236, 310, 330, 390).

Abstract: A very low intermediate frequency (IF) transceiver is described for use in a wireless LAN, cellular telephone, cordless telephone, and other radio transceiver applications. The transceiver preferably directly down-converts the RF signal to lower frequency such as a very low IF signal, which can be handled by transceiver components advantageously integrated with the communication control system such as an MAC or serial communications controller. Preferably, the very low IF signal is above peak modulation deviation and below the channel interval for the communication system. The very low IF signal may be up converted so that the RF signal can be more reliably demodulated. Alternatively, the RF signal can be additionally converted to a second IF frequency before the very low IF frequency to reduce the effects of noise in the transceiver. Alternatively, an image rejection mixer circuit can be employed to provide some rejection selectivity for the adjacent channels on one side of the local oscillator.

Abstract: A biphase stable FPLL includes a lock switch, operated in response to a frequency lock condition, that forces a predetermined voltage on the input of the third multiplier to guarantee that the loop locks up in a phase that produces a desired polarity of demodulated signal. A frequency lock indicator operates the lock switch to force the predetermined voltage on the third multiplier irrespective of the actual lock up phase of the loop. If the lock up phase is wrong, the voltage reversal causes the VCO to slip 180.degree. in phase and the loop locks up in its other bistable state.

Abstract: A transceiver (10) in a first embodiment includes a zero intermediate frequency (ZIF) receiver (11), which achieves high throughput operation by reducing receiver latency time due to receiver response within a receiver pass band to carrier spectral components of a modulated carrier frequency. During a receive mode, a receiver local oscillator (LO) frequency is offset from the carrier frequency within the receiver pass band, preferably as determined by worst case errors in the carrier frequency and the LO frequency. During a transmit mode, the receiver LO frequency is modulated in such a way as to suppress the LO center frequency component in the modulated spectrum.