Semiconductor Thin Film Device Or Thin Film Electric Solid-state Device Or System (i.e., Active Or Passive) Patents (Class 505/191)
  • Patent number: 5912503
    Abstract: A method of fabricating a low-inductance, in-line resistor includes the steps of: depositing a superconductive layer 12 on a base layer 14; patterning an interconnect region 16 on the superconductive layer 12; and converting the interconnect region 16 of the superconductive layer 12 to a resistor material region 18. The resistor region 18 and the superconductive layer 12 are substantially in the same plane. The method can further include the steps of depositing a conductive layer 22 on the resistor region 18 and on the photo-resist layer 20, and lifting off the photo-resist layer 20 to leave the conductive layer 22 on the resistor region 18. As such, the conductive layer 22 provides a low sheet resistivity for the resistor region 18.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: June 15, 1999
    Assignee: TRW Inc.
    Inventors: Hugo W. Chan, Arnold H. Silver
  • Patent number: 5910662
    Abstract: A semiconductor substrate comprising a single crystal substrate base such a silicon and a superconducting thin film layer deposited on said substrate base and composed of compound oxide such as Ln.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-.delta.. (Ln is lanthanide).
    Type: Grant
    Filed: December 14, 1993
    Date of Patent: June 8, 1999
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideo Itozaki, Keizo Harada, Naoji Fujimori, Shuji Yazu, Tetsuji Jodai
  • Patent number: 5852703
    Abstract: The present invention is to provide a production method of a ferroelectric thin film element comprising an epitaxial ferroelectric thin film having stable composition control, an optical smoothness of the surface, and a high crystallization. In the production method, carrying out a first solid phase epitaxial growth process where a first organometallic compound is applied on the single-crystalline substrate and heated to form a ferroelectric buffer layer on a single-crystalline substrate, having a composition different from the substrate with a film thickness of 1 nm to 40 nm; carrying out at least once a second solid phase epitaxial growth process where a second organometallic compound is applied on the ferroelectric buffer layer formed in the above process and heated to form a ferroelectric single layer thin film with a film thickness of 10 nm or more, and being thicker than the ferroelectric buffer layer.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: December 22, 1998
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Keiichi Nashimoto
  • Patent number: 5846846
    Abstract: Disclosed is a method for making a superconducting field-effect device with a grain boundary channel, the method comprising the steps of depositing a first superconducting thin film on a substrate; patterning the first superconducting thin film to form a patterned superconducting thin film having an opening; depositing a template layer thereon; selectively etching back the template layer to form a patterned template layer; growing a second superconducting thin film to form a grain boundary therebetween; depositing an insulating layer on the second superconducting thin film to protect the second superconducting thin film from degrading in property in the air; selectively etching back the insulating layer to form a patterned insulating layer; forming a gate insulating layer on the patterned insulating layer; and coating metal electrodes thereon, source/drain being formed respectively on the etched portions, and a gate electrode being formed on the deposited portion of the gate insulating layer directly above th
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: December 8, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jeong-Dae Suh, Gun-Yong Sung
  • Patent number: 5828078
    Abstract: The present invention presents an electrostatic discharge and power surge protected circuit board (10) and method for providing an electrostatic discharge and power surge protected circuit board. The protected circuit board (10) includes temperature sensitive conducting material (14) and semiconductor circuit components (12). The temperature sensitive conducting material (14) has a critical current density, provides a high impedance when the critical current density is exceeded, and preferably comprises a high temperature superconductor. Preferably, the temperature sensitive conducting material (14) and the semiconductor circuit components (12) are coupled in series. In a method aspect of the present invention, an electrostatic discharge protected circuit board (10) is provided by providing a current carrying mechanism (16) on the circuit board (10), and coupling the current carrying mechanism (16) to temperature sensitive conducting material (14).
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: October 27, 1998
    Assignee: Hughes Electronics
    Inventor: Nicholas A. Doudoumopoulos
  • Patent number: 5793055
    Abstract: A step junction is provided for superconductor/semiconductor heterostructure hybrid devices like tunneling transistors, in a body of p-InAs with a vertical side connecting the low plateau and high plateau on which superconductors, preferably of niobium, are applied.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: August 11, 1998
    Assignee: Forschungszentrum Julich GmbH
    Inventor: Alexander Kastalsky
  • Patent number: 5747873
    Abstract: A system for incorporating superconductor circuits and semiconductor circuits in multilayered structures. A carrier material is chosen that is a good thermal match with the preferred superconductor substrates. The preferred superconductor substrate materials are lanthanum aluminate, magnesium oxide and neodymium gallate. The substrate carrier material should provide adequate thermal match through the range of operating temperatures which are preferably from room temperature to 77K. The preferred carrier material is a low temperature cofired ceramic (LTCC) which allows for multilayered structures to be developed which incorporate the superconductor circuitry and the semiconductor elements. The LTCC is composed of crystalline quartz particles in a borosilicate glass matrix. The percentage of quartz may be adjusted to adjust the thermal expansion characteristics of the LTCC.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: May 5, 1998
    Assignee: Northrop Grumman Corporation
    Inventors: Salvador H. Talisa, Michael A. Janocko, Deborah P. Partlow, Andrew J. Piloto
  • Patent number: 5747418
    Abstract: An apparatus and method for producing electricity from heat. The present invention is a thermoelectric generator that uses materials with substantially no electrical resistance, often called superconductors, to efficiently convert heat into electrical energy without resistive losses. Preferably, an array of superconducting elements is encased within a second material with a high thermal conductivity. The second material is preferably a semiconductor. Alternatively, the superconducting material can be doped on a base semiconducting material, or the superconducting material and the semiconducting material can exist as alternating, interleaved layers of waferlike materials. A temperature gradient imposed across the boundary of the two materials establishes an electrical potential related to the magnitude of the temperature gradient. The superconducting material carries the resulting electrical current at zero resistivity, thereby eliminating resistive losses.
    Type: Grant
    Filed: October 17, 1996
    Date of Patent: May 5, 1998
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: John D. Metzger, Mohamed S. El-Genk
  • Patent number: 5728599
    Abstract: Process for manufacturing a high interconnection density, fine-line, superconductive printed leadframes using thick-film screen-printing techniques, or other printing techniques. Generally, a superconductive leadframe pattern is printed on a backing substrate. Once the pattern is cured, the backing substrate, or portions thereof can be removed. The backing substrate can be a "fish paper" substrate treated with a release agent, or other substrate material which can be dissolved away, etched away, or otherwise removed. Portions of the backing substrate can be used to provide mechanical integrity for the leadframe. The leadframe fingers can be printed using a superconductive paste or a superconductive precursor paste which is subsequently treated to exhibit superconductivity.
    Type: Grant
    Filed: August 7, 1995
    Date of Patent: March 17, 1998
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Mark Schneider, Chok J. Chia
  • Patent number: 5665980
    Abstract: A method of fabricating a superconducting quantum interference device (DC-SQUID) constructed from short weak links with untrafine wires. The method comprises the following steps: successive forming a niobium nitride film and a silicon nitride film on a substrate; oblique etching of the niobium nitride film and said silicon nitride film with respect to the substrate by a reactive ion etching process using a mixture of oxygen and CF.sub.4 gases to form an olique edge; and successive forming a barrier thin film and a counterelectrode of niobium on the said edge. The short weak links wire fabricated by field evaporation technique. The counterelectrode material were field-evaporated and formed the conductive paths in the pinholes in the insulating thin film.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: September 9, 1997
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yoshio Onuma, Katsuyoshi Hamasaki
  • Patent number: 5644143
    Abstract: Various techniques for forming superconductive lines are described whereby superconductive lines can be formed by stamping, etching, polishing, or by rendering selected areas of a superconductive film (layer) non-superconductive. The superconductive material can be "perfected" (or optimized) after it is formed into lines (traces). In one embodiment, trenches are etched in a substrate, the trenches are filled with superconductive material, and any excess superconductive material overfilling the trenches is removed, such as by polishing. In another embodiment, superconductive lines are formed by rendering selected areas of a superconductive layer (i.e., areas other than the desired superconductive lines) non-superconductive by "damaging" the superconductive material by laser beam heating, or by ion implantation. Superconductive lines formed according to the invention can be used to protect semiconductor devices (e.g.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: July 1, 1997
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Mark Schneider, Nicholas F. Pasch, Abraham Yee, William C. Schneider
  • Patent number: 5545611
    Abstract: An oxide superconductor thin film is formed on a substrate by emitting molecular beams of constituent elements of the oxide superconductor to the substrate under high vacuum, wherein at first a molecular beam of one of the constituent elements of the oxide superconductor, of which an oxide thin film can be deposited so as to have a smooth surface, is emitted so as to form the oxide thin film of one or two unit cells. And then, all the molecular beams of constituent elements of the oxide superconductor are emitted to the oxide thin film so as to form the oxide superconductor thin film.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: August 13, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takao Nakamura
  • Patent number: 5534715
    Abstract: A Josephson junction is disclosed which includes a substrate of a single crystal having a substantially flat surface, a wiring pattern of an oxide superconductor formed on the flat surface of the substrate, and an altered region formed having a width of 300 nm or less and formed in the wiring pattern to intersect the wiring pattern, the crystal orientations of the wiring pattern on both sides of the altered region being equal to each other.
    Type: Grant
    Filed: November 8, 1993
    Date of Patent: July 9, 1996
    Assignees: International Superconductivity Technology Center, NEC Corporation
    Inventors: Christian Neumann, Katsumi Suzuki, Youichi Enomoto, Shoji Tanaka
  • Patent number: 5525582
    Abstract: A Josephson junction device comprising a single crystalline substrate including a principal surface, a layer of the same material as the substrate formed on the principal surface of the substrate so as to form a step on the principal surface, and an oxide superconductor thin film formed on the principal surface of the substrate. The oxide superconductor thin film includes a first and a second superconducting portions respectively positioned above and below the step, which are constituted of single crystals of the oxide superconductor, a junction portion between the first and the second superconducting portions, which is constituted of a single crystal of the oxide superconductor of which crystal orientation is different from those of the first and second superconducting portions, and grain boundaries between the first superconducting portion and the junction portion and between the second superconducting portion and the junction portion, which constitute one weak link of the Josephson junction.
    Type: Grant
    Filed: October 20, 1994
    Date of Patent: June 11, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Saburo Tanaka, Takashi Matsuura, Hideo Itozaki
  • Patent number: 5514484
    Abstract: An orientative ferroelectric thin film has such a structure that an epitaxial or orientative buffer layer having a double layer structure constituted by two layers is formed on a semiconductor single crystal (100) substrate, and an epitaxial or orientative perovskite ABO.sub.3 type ferroelectric thin film is further formed on the buffer layer. The epitaxial or orientative buffer layer has a structure in which a perovskite ABO.sub.3 type thin film is formed on an MgO thin film. Also, an orientative ferroelectric thin film has such a structure that an opitaxial MgO buffer layer is formed on a single crystal Si (100) substrate, and an epitaxial or orientative perovskite ABO.sub.3 type ferroelectric thin film is formed on the buffer layer.
    Type: Grant
    Filed: October 19, 1993
    Date of Patent: May 7, 1996
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Keiichi Nashimoto
  • Patent number: 5510324
    Abstract: The invention relates to a method of manufacturing a superconducting device, which comprises the steps of forming on a principal surface of a substrate a non-superconducting oxide layer having a similar crystal structure to that of a c-axis oriented oxide superconductor thin film and a flat-top projection at its center portion, forming a c-axis oriented oxide superconductor thin film having an extremely thin thickness on the non-superconducting oxide layer so as to form a superconducting channel on the projecting portion of the non-superconducting oxide layer, forming an insulating layer on the c-axis oriented oxide superconductor thin film so as to form a gate insulating layer on the superconducting channel, and forming an a-axis oriented oxide superconductor thin film so as to form a superconducting source region and a superconducting drain region of which upper surfaces have the same level as that of the superconducting channel.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: April 23, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama, Hiroshi Inada
  • Patent number: 5504058
    Abstract: In a method of manufacturing a superconducting device which has a first thin film of oxide superconductor material formed on a substrate and a second thin film formed on the first thin film of oxide superconductor material, after the second thin film is deposited on the first thin film of oxide superconductor material, a multi-layer structure formed of the first and second thin films is patterned so that a side surface of the first thin film is exposed. In this condition, the whole of the substrate is heated in an O.sub.2 atmosphere or in an O.sub.3 atmosphere so that oxygen is entrapped into the first thin film of oxide superconductor material. Thereafter, the patterned multi-layer structure is preferably covered with a protection coating.
    Type: Grant
    Filed: April 20, 1994
    Date of Patent: April 2, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Sou Tanaka, Mitsuchika Saitoh, Michitomo Iiyama
  • Patent number: 5498881
    Abstract: A superconducting device has a substrate and a superconducting film formed on the substrate. A surface of the substrate has a first surface portion of which a curvature is constant or changes continuously, a second surface portion of which a curvature is constant or changes continuously, and a third surface portion at which the first and second surface portions meet and at which the curvatures of the first and second surface portions become discontinuous. The superconducting film formed on the surface of said substrate has a grain boundary serving as a junction only in a portion corresponding to the third surface portion of the substrate.
    Type: Grant
    Filed: September 20, 1994
    Date of Patent: March 12, 1996
    Assignees: International Superconductivity Technology Ctr., Sharp Kabushiki Kaisha
    Inventors: Manabu Fujimoto, Keiichi Yamaguchi, Youichi Enomoto, Tsutomu Mitsuzuka, Katsumi Suzuki
  • Patent number: 5494891
    Abstract: A superconducting device comprises a substrate, a non-superconducting layer formed in a principal surface of said substrate, an extremely thin superconducting channel formed of an oxide superconductor thin film on the non-superconducting layer. A superconducting source region and a superconducting drain region of a relatively thick thickness are formed of the oxide superconductor at the both sides of the superconducting channel separated from each other but electrically connected through the superconducting channel, so that a superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: February 27, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: 5468723
    Abstract: A superconducting device has a structure of superconductor--normal--conductor (semiconductor)--superconductor. The superconducting regions and the normal-conductor region can be made of the same elements but having different relative proportions of the elements. The device can be fabricated by introducing at least one element into an unmasked region of the superconductor to form a normal conductor region or into unmasked regions of the normal conductor to form superconductor regions.
    Type: Grant
    Filed: May 4, 1994
    Date of Patent: November 21, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Toshikazu Nishino, Haruhiro Hasegawa, Ushio Kawabe
  • Patent number: 5447906
    Abstract: Superconducting transition metal oxide films are provided which exhibit very high onsets of superconductivity and superconductivity at temperatures in excess of 40.degree. K. These films are produced by vapor deposition processes using pure metal sources for the metals in the superconducting compositions, where the metals include multi-valent nonmagnetic transition metals, rare earth elements and/or rare earth-like elements and alkaline earth elements. The substrate is exposed to oxygen during vapor deposition, and, after formation of the film, there is at least one annealing step in an oxygen ambient and slow cooling over several hours to room temperature. The substrates chosen are not critical as long as they are not adversely reactive with the superconducting oxide film. Transition metals include Cu, Ni, Ti and V, while the rare earth-like elements include Y, Sc and La. The alkaline earth elements include Ca, Ba and Sr.
    Type: Grant
    Filed: June 23, 1994
    Date of Patent: September 5, 1995
    Assignee: International Business Machines Corporation
    Inventors: Praveen Chaudhari, Richard J. Gambino, Roger H. Koch, James A. Lacey, Robert B. Laibowitz, Joseph M. Viggiano
  • Patent number: 5442195
    Abstract: A superconducting device may include a superconducting weak link equipped with plural superconducting devices that are used as input-output terminals formed on the same plane and at least one current source for applying current to at least one of these superconducting electrodes. A superconducting device suitable for high integration can be realized as it enables structuring of a superconducting weak link 1 equipped with plural superconducting electrodes 101, 102, 103 and 104 that can be used as input-output terminals and changing symmetry of superconducting electrode arrangement through the form of a normal conductor 201 which is forming a superconducting weak link. In addition, when this superconducting device is used as a quasi-particle injection type device, a superconducting device with plural superconducting electrodes that can be used for a gate electrode, drain electrode or control electrode can be realized. Further, a superconducting device equipped with new functions (e.g.
    Type: Grant
    Filed: October 18, 1993
    Date of Patent: August 15, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Saitoh, Toshikazu Nishino, Mutsuko Hatano
  • Patent number: 5434127
    Abstract: For manufacturing a superconducting device, a first c-axis orientated oxide superconductor thin film having a very thin thickness is formed on a principal surface of a substrate, and a stacked structure of a gate insulator and a gate electrode is formed on a portion of the first oxide superconductor thin film. An a-axis orientated oxide superconductor thin film is grown, using the gate electrode as a mask, so that second and third superconducting regions having a relatively thick thickness are formed at both sides of the gate electrode, electrically isolated from the gate electrode. The superconducting device thus formed can functions as a super-FET.
    Type: Grant
    Filed: July 25, 1994
    Date of Patent: July 18, 1995
    Assignee: Sumitomo Electric Industries, ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5420101
    Abstract: The invention relates to a structured superconductive track and a process for making it from epitaxial high temperature superconductor (HTSC) layers using lift off technique, in which a HTSC track deposited on an elevated substrate region is surrounded by an insulating layer of doped HTSC lying on a lower substrate region, and the substrate region with the superconductive track formed thereon is elevated such that the superconductive track is isolated from the insulating layer.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: May 30, 1995
    Assignee: Forschungszentrum Julich GmbH
    Inventors: Carlo Copetti, Jurgen Schubert, Willi Zander, Christoph Buchal
  • Patent number: 5408108
    Abstract: A superconducting device comprises a substrate having a principal surface and a non-superconducting oxide layer having a similar crystal structure to that of the oxide superconductor, which has a projection at its center portion. A superconducting source region and a superconducting drain region formed of an .alpha.-axis oriented oxide superconductor thin film are positioned at the both sides of the projection of the non-superconducting oxide layer separated from each other and an extremely thin superconducting channel formed of a c-axis oriented oxide superconductor thin film is positioned on the projection of the non-superconducting oxide layer. The superconducting channel electrically connects the superconducting source region to the superconducting drain region, so that superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region.
    Type: Grant
    Filed: December 14, 1992
    Date of Patent: April 18, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama, Hiroshi Inada
  • Patent number: 5399546
    Abstract: A superconducting device comprises a substrate, a non-superconducting layer formed in a principal surface of said substrate, an extremely thin superconducting channel formed of an oxide superconductor thin film on the non-superconducting layer. A superconducting source region and a superconducting drain region of a relatively thick thickness are formed of the oxide superconductor at the both sides of the superconducting channel separated from each other but electrically connected through the superconducting channel, so that a superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region.
    Type: Grant
    Filed: November 30, 1992
    Date of Patent: March 21, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: 5382565
    Abstract: This field-effect transistor comprises a conductive substrate (2) serving as the gate electrode, an insulating barrier layer (3), and a superconducting channel layer (1) on top of the barrier layer (3). The superconductor layer (1) carries a pair of mutually spaced electrodes (4, 5) forming source and drain, respectively. The substrate is provided with an appropriate gate contact (6).The substrate (2) consists of a material belonging to the same crystallographic family as the barrier layer (3). In a preferred embodiment, the substrate (2) is niobium-doped strontium titanate, the barrier layer (3) is undoped strontium titanate, and the superconductor (1) is a thin film of a material having a lattice constant at least approximately similar to the one of the materials of the substrate (2) and barrier (3) layers. A preferred material of this type is YBa.sub.2 Cu.sub.3 O.sub.7-.delta., where 0.ltoreq..delta..ltoreq.0.5.
    Type: Grant
    Filed: October 20, 1993
    Date of Patent: January 17, 1995
    Assignee: International Business Machines Corporation
    Inventors: Johannes G. Bednorz, Jochen D. Mannhart, Carl A. Mueller
  • Patent number: 5380704
    Abstract: Disclosed herein is a superconducting field effect transistor (FET) which has at least an active region formed from a film of oxide normal conductor, a plurality of electrodes formed from a film of oxide superconductor, and a means to control the current which flows between the electrodes through the active region. Having a much greater electrode distance than the conventional superconducting device, it can be produced easily by lithography without resorting to special techniques.
    Type: Grant
    Filed: August 30, 1993
    Date of Patent: January 10, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinobu Tarutani, Tokuumi Fukazawa, Uki Kabasawa, Kazumasa Takagi, Akira Tsukamoto, Masahiko Hiratani, Toshikazu Nishino
  • Patent number: 5374610
    Abstract: An insulating composition consisting of Bi, Sr, RE, Cu, O or of Tl, Ba, RE, Cu, O (wherein; RE is an element selected from a group consisting of Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and Y) aligns properly with a crystal face of an oxide superconductor because its crystal structure is the same as or similar to that of the oxide superconductor. An insulating composition in which a part of Bi is replaced by Pb is further near the oxide superconductor its construction, and the modulation structure in this insulating composition is mitigated or disappears.
    Type: Grant
    Filed: May 8, 1991
    Date of Patent: December 20, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noburu Fukushima, Shunji Nomura, Hisashi Yoshino, Ken Ando, Hiromi Niu, Tomohisa Yamashita
  • Patent number: 5358925
    Abstract: An HTSC material epitaxially deposited on a YSZ buffer layer on a surface of a monocrystalline silicon substrate has a zero resistance transition temperature of at least 85.degree. K., a transition width (10-90%) of no more than 1.0.degree. K., a resistivity at 300.degree. K. of no more than 300 micro-ohms-centimeter and a resistivity ratio (at 300.degree. K./100.degree. K.) of 3.0.+-. 0.2. The surface of the silicon substrate is cleaned using a spin-etch process to produce an atomically clean surface terminated with an atomic layer of an element such as hydrogen with does not react with silicon. The substrate can be moved to a deposition chamber without contamination. The hydrogen is evaporated in the chamber, and then YSZ is epitaxially deposited preferably by laser ablation. Thereafter, the HTSC material, such as YBCO, is epitaxially deposited preferably by laser ablation. The structure is then cooled in an atmosphere of oxygen.
    Type: Grant
    Filed: August 10, 1992
    Date of Patent: October 25, 1994
    Assignee: Board of Trustees of the Leland Stanford Junior University
    Inventors: George A. Neville Connell, David B. Fenner, James B. Boyce, David K. Fork
  • Patent number: 5354732
    Abstract: An electrode in an electronic device using a functional thin film facilitates epitaxial growth during the functional material film-forming process and prevents the generation of cracks due to thermal stress. An oxide superconductor is using as an electrode material, thereby forming the crystal structure identical with the crystal structure of a functional thin film, and rendering their lattice constant and coefficient of thermal expansion close to the lattice constant and coefficient of thermal expansion functional thin film. According to the electrode material, high electric conductivity, low thermal conductivity and large thermal absorption coefficient characteristics can also be obtained.
    Type: Grant
    Filed: December 28, 1992
    Date of Patent: October 11, 1994
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Hitoshi Tabata, Osamu Murata, Junzo Fujioka, Shunichi Minakata, Tomoji Kawai, Shichio Kawai
  • Patent number: 5347143
    Abstract: A superconducting tunnel element, having a plurality of super conductors separated by barriers, the superconductors each comprising two physically separate but electrically connected superconducting layers and one insulated control layer. As a result, summation of the detection capacity or of the transmitting intensity becomes possible. Also, the simultaneous detection or transmission is permitted on arbitrary different frequencies or a summation of the signal intensity is possible in the case of SQUID-systems.
    Type: Grant
    Filed: August 9, 1993
    Date of Patent: September 13, 1994
    Assignee: Dornier Luftfahrt GmbH
    Inventor: Hehrwart Schroder
  • Patent number: 5334580
    Abstract: A superconducting device has a structure of superconductor - normal-conductor (semiconductor) - superconductor. The superconductors constituting the superconducting device are made of a superconducting oxide material of K.sub.2 NiF.sub.4 type crystal-line structure or perovskite type crystalline structure which contains at least one element selected from the group consisting of Ba, Sr, Ca, Mg and Ra; at least one element selected from the group consisting of La, Y, Ce, Sc, Sm, Eu, Er, Gd, Ho, Yb, Nd, Pr, Lu and Tb; Cu; and O.
    Type: Grant
    Filed: January 14, 1993
    Date of Patent: August 2, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Toshikazu Nishino, Haruhiro Hasegawa, Ushio Kawabe
  • Patent number: 5332722
    Abstract: A novel nonvolatile memory element or cell comprising a memory means consisting of at least one superconducting ring (21, 22) and a detector means consisting of a MOSFET. The superconducting ring and the MOSFET are arranged in such a manner that a magnetic flux created by the superconducting ring (21, 22) passes through a channel zone of the MOSFET. Information is held in the superconducting ring in a form of permanent current and is detected electrically as variation in the conductivity of the channel zone of the MOSFET.
    Type: Grant
    Filed: March 8, 1993
    Date of Patent: July 26, 1994
    Assignee: Sumitomo Electric Industries, LTD
    Inventor: Mitsuka Fujihira
  • Patent number: 5326745
    Abstract: Superconducting device include a type having a structure of a superconductor--a normal-conductor (or a semiconductor)--a superconductor, and a type having a superconducting weak-link portion between superconductors.The superconductors constituting the superconducting device are made of an oxide of either of perovskite type and K.sub.2 NiF.sub.4 type crystalline structures, containing at least one element selected from the group consisting of Ba, Sr, Ca, Mg, and Ra; at least one element selected from the group consisting of La, Y, Ce, Sc, Sm, Eu, Er, Gd, Ho, Yb, Nd, Pr, Lu, and Tb; Cu; and O. In addition, the c-axis of the crystal of the superconductor is substantially perpendicular to the direction of current flowing through this superconductor.
    Type: Grant
    Filed: March 17, 1992
    Date of Patent: July 5, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Toshikazu Nishino, Ushio Kawabe, Yoshinobu Tarutani, Shinya Kominami, Toshiyuki Aida, Tokuumi Fukazawa, Mutsuko Hatano
  • Patent number: 5323023
    Abstract: An article of manufacture having an epitaxial (111) magnesium oxide (MgO) layer, suitable for use as a buffer layer, on a (111) surface of a tetrahedral semiconductor substrate, and method for its manufacture is described. The article may further include an epitaxial oxide overlayer on the (111) MgO layer. The overlayer may be a conducting, superconducting, and/or ferroelectric oxide layer. The method of producing the epitaxial (111) magnesium oxide (MgO) layer on the (111) surface of a tetrahedral semiconductor substrate proceeds at low temperature. The method may further include steps for forming the epitaxial oxide layer on the (111) MgO layer. The methods include the steps of preparing the (111) surface of a tetrahedral semiconductor substrate for deposition and the low temperature depositing of an MgO layer on the prepared surface. Further steps may include the depositing of the oxide layer over the MgO layer.
    Type: Grant
    Filed: December 2, 1992
    Date of Patent: June 21, 1994
    Assignee: Xerox Corporation
    Inventor: David K. Fork
  • Patent number: 5306705
    Abstract: A non-linear superconducting junction device comprising a layer of high transient temperature superconducting material which is superconducting at an operating temperature, a layer of metal in contact with the layer of high temperature superconducting material and which remains non-superconducting at the operating temperature, and a metal material which is superconducting at the operating temperature and which forms distributed Sharvin point contacts with the metal layer.
    Type: Grant
    Filed: May 6, 1993
    Date of Patent: April 26, 1994
    Assignee: Board of Trustees of the Leland Stanford Junior University
    Inventors: Matthew J. Holcomb, William A. Little