Semiconductor Thin Film Device Or Thin Film Electric Solid-state Device Or System (i.e., Active Or Passive) Patents (Class 505/191)
  • Patent number: 9722086
    Abstract: In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: August 1, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Hidetomo Kobayashi
  • Patent number: 9461233
    Abstract: A high-temperature superconducting film includes a SrTiO3 substrate, a single crystalline FeSe layer, and a protective layer with a layered crystal structure. The single crystalline FeSe layer is sandwiched between the SrTiO3 substrate and the protective layer via a layer-by-layer mode. An onset temperature of superconducting transition of the high-temperature superconducting film is greater than or equal to 54 K, and a critical current density of the high-temperature superconducting film is about 106 A/cm2 at 12 K.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 4, 2016
    Assignees: Tsinghua University, Institute of Physics, Chinese Academy of Sciences
    Inventors: Qi-Kun Xue, Xu-Cun Ma, Li-Li Wang, Xi Chen, Jin-Feng Jia, Ke He, Shuai-Hua Ji, Wen-Hao Zhang, Qing-Yan Wang, Zhi Li
  • Patent number: 9425375
    Abstract: A method for making a high-temperature superconducting film includes loading a SrTiO3 substrate in an ultra-high vacuum system. A single crystalline FeSe layer is grown on a surface of the SrTiO3 substrate by molecular beam epitaxy. A protective layer with a layered crystal structure is grown by molecular beam epitaxy and covering the single crystalline FeSe layer.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: August 23, 2016
    Assignees: Tsinghua University, Institute of Physics, Chinese Academy of Sciences
    Inventors: Qi-Kun Xue, Xu-Cun Ma, Li-Li Wang, Xi Chen, Jin-Feng Jia, Ke He, Shuai-Hua Ji, Wen-Hao Zhang, Qing-Yan Wang, Zhi Li
  • Patent number: 9014771
    Abstract: A layered superconductor device includes multiple layers of a single crystal superconducting material having intermittent layers of superconducting material dispersed in a pattern with a second material such that each layer of the multiple layers a single crystal superconducting material are interconnected via superconducting material, allowing for a continuous current path, and a thickness of the superconducting material never exceeds a first predetermined thickness.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: April 21, 2015
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Thomas O. Jones, III
  • Patent number: 8989829
    Abstract: A layered superconductor device includes multiple layers of a single crystal superconducting material having intermittent layers of superconducting material dispersed in a pattern with a second material such that each layer of the multiple layers a single crystal superconducting material are interconnected via superconducting material, allowing for a continuous current path, and a thickness of the superconducting material never exceeds a first predetermined thickness.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: March 24, 2015
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Thomas O. Jones, III
  • Publication number: 20150045228
    Abstract: A radio frequency-assisted fast superconducting switch is described. A superconductor is closely coupled to a radio frequency (RF) coil. To turn the switch “off,” i.e., to induce a transition to the normal, resistive state in the superconductor, a voltage burst is applied to the RF coil. This voltage burst is sufficient to induce a current in the coupled superconductor. The combination of the induced current with any other direct current flowing through the superconductor is sufficient to exceed the critical current of the superconductor at the operating temperature, inducing a transition to the normal, resistive state. A by-pass MOSFET may be configured in parallel with the superconductor to act as a current shunt, allowing the voltage across the superconductor to drop below a certain value, at which time the superconductor undergoes a transition to the superconducting state and the switch is reset.
    Type: Application
    Filed: April 9, 2013
    Publication date: February 12, 2015
    Applicant: Brookhaven Science Associates, LLC
    Inventors: Vyacheslav Solovyov, Qiang Li
  • Patent number: 8822979
    Abstract: Disclosed is an arrangement including a support and a super-conductive film which is arranged thereon. The film has a plurality of holes in order to form a perforated grating. The holes are optionally round holes having increasing sizes, triangular holes, or holes which are arranged in a meandering manner in the film, and which produce improved properties in relation to signal conversion by a vortex diode and/or in a filter. A DC signal is directly removed therein without additional electronics.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: September 2, 2014
    Assignee: Forschungszentrum Juelich GmbH
    Inventor: Roger Woerdenweber
  • Patent number: 8795854
    Abstract: Novel articles and methods to fabricate the same resulting in flexible, oriented, semiconductor-based, electronic devices on {110}<100> textured substrates are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: August 5, 2014
    Inventor: Amit Goyal
  • Patent number: 8787999
    Abstract: A fault current limiter system including a fault current limiter and a variable shunt current splitting device. The current splitting device includes first and second conductive windings, wherein the first conductive winding is connected in parallel with the fault current limiter and is configured to carry current in a first direction. The second conductive winding is electrically connected in series with the fault current limiter and is configured to carry current in a second direction opposite to the first direction so that the reactance of the first winding is negated by the reactance of the second winding during steady state operation of the fault current limiter system. Thus, a first portion of a steady state current is conveyed through the fault current limiter and a second portion of the current is conveyed through the current splitting device. The steady state current load on the fault current limiter is thereby reduced.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: July 22, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Kasegn D. Tekletsakik
  • Patent number: 8649834
    Abstract: A layered superconductor device includes multiple layers of a single crystal superconducting material having intermittent layers of superconducting material dispersed in a pattern with a second material such that each layer of the multiple layers a single crystal superconducting material are interconnected via superconducting material, allowing for a continuous current path, and a thickness of the superconducting material never exceeds a first predetermined thickness.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: February 11, 2014
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Thomas O. Jones
  • Patent number: 8571615
    Abstract: A superconducting metallic glass transition-edge sensor (MGTES) and a method for fabricating the MGTES are provided. A single-layer superconducting amorphous metal alloy is deposited on a substrate. The single-layer superconducting amorphous metal alloy is an absorber for the MGTES and is electrically connected to a circuit configured for readout and biasing to sense electromagnetic radiation.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: October 29, 2013
    Assignee: California Institute of Technology
    Inventor: Charles C. Hays
  • Publication number: 20130196856
    Abstract: In some embodiments of the invention, superconducting structures are described. In certain embodiments the superconducting structures described are thin films of iron-based superconductors on textured substrates; in some aspects a method for producing thin films of iron-based superconductors on textured substrates is disclosed. In some embodiments applications of thin films of iron-based superconductors on textured substrates are described. Also contemplated is the formation of a film of iron-based superconductor having a thickness and an in-plane lattice constant formed on a textured substrate having a thickness and an in-plane lattice constant similar to the in-plane lattice constant of the iron-based superconductor.
    Type: Application
    Filed: August 2, 2011
    Publication date: August 1, 2013
    Applicant: BROOKHAVENSCIENCE ASSOICATES, LLC
    Inventors: Qiang Li, Weidong Si
  • Patent number: 8252724
    Abstract: A fault current limiter, with a superconducting device (1; 21; 31; 41; 51; 61; 71; 72) comprising a sequence of superconducting elements (2a-2f), each with—a substrate (3a-3d), —a superconducting film (5a-5d), and —an intermediate layer (4a-4c) provided between the substrate and the superconducting film, wherein the superconducting films (5a-5d) of adjacent superconducting elements (2a-2f) of the sequence are electrically connected, in particular in series, is characterized in that the substrates (3a-3d) of the superconducting elements (2a-2d) are electrically conducting substrates (3a-3d), wherein the electrically conducting substrate (3a-3d) of each superconducting element (2a-2f) of the sequence is electrically insulated from each electrically conducting substrate (3a-3d) of those adjacent superconducting elements (2a-2f) within the sequence whose superconducting films (5a-5d) are electrically connected in series with the superconducting film (5a-5d) of said superconducting element (2a-2f), and that the in
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: August 28, 2012
    Assignees: Areva T & D SAS, Bruker HTS GmbH
    Inventors: Francis James Mumford, Alexander Usoskin
  • Patent number: 8252725
    Abstract: A fault current limiter, with a superconducting device (1; 21; 31; 41; 51; 61; 71; 72) comprising a sequence of superconducting elements (2a-2f), each with an electrically conducting substrate (3a-3d), a superconducting film (5a-5d), and an electrically insulating intermediate layer (4a-4c) provided between the substrate and the superconducting film, wherein the superconducting films (5a-5d) of adjacent superconducting elements (2a-2f) of the sequence are electrically connected, in particular in series, wherein the electrically conducting substrate (3a-3d) of each superconducting element (2a-2f) of the sequence is electrically insulated from each electrically conducting substrate (3a-3d) of those adjacent superconducting elements (2a-2f) within the sequence whose superconducting films (5a-5d) are electrically connected in series with the superconducting film (5a-5d) of said superconducting element (2a-2f).
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: August 28, 2012
    Assignees: Areva T & D SAS, Bruker HTS GmbH
    Inventors: Francis James Mumford, Alexander Usoskin
  • Patent number: 8247354
    Abstract: A fault current limiter and a method for the production thereof has a superconducting device (1; 21; 31; 41; 51; 61; 71; 72) comprising a sequence of superconducting elements (2a-2f), each with an electrically conducting substrate (3a-3d), a superconducting film (5a-5d) and an electrically insulating intermediate layer (4a-4c) provided between the substrate and the superconducting film. The superconducting films (5a-5d) of adjacent superconducting elements (2a-2f) of the sequence are electrically connected, in particular in series, wherein the electrically conducting substrate (3a-3d) of each superconducting element (2a-2f) of the sequence is electrically insulated from each electrically conducting substrate (3a-3d) of those adjacent superconducting elements (2a-2f) within the sequence whose superconducting films (5a-5d) are electrically connected in series with the superconducting film (5a-5d) of said superconducting element (2a-2f).
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: August 21, 2012
    Assignees: Areva T & D SAS, Bruker HTS GmbH
    Inventors: Francis James Mumford, Alexander Usoskin
  • Patent number: 8211833
    Abstract: The invention pertains to creating new extremely low resistance (“ELR”) materials, which may include high temperature superconducting (“HTS”) materials. In some implementations of the invention, an ELR material may be modified by depositing a layer of modifying material unto the ELR material to form a modified ELR material. The modified ELR material has improved operational characteristics over the ELR material alone. Such operational characteristics may include operating at increased temperatures or carrying additional electrical charge or other operational characteristics. In some implementations of the invention, the ELR material is a cuprate-perovskite, such as, but not limited to YBCO. In some implementations of the invention, the modifying material is a conductive material that bonds easily to oxygen, such as, but not limited to, chromium.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: July 3, 2012
    Assignee: Ambature, LLC
    Inventors: Douglas J. Gilbert, Timothy S. Cale
  • Patent number: 8178221
    Abstract: Novel articles and methods to fabricate the same resulting in flexible, {100}<100> or 45°-rotated {100}<100> oriented, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: May 15, 2012
    Inventor: Amit Goyal
  • Publication number: 20120077680
    Abstract: Systems, articles, and methods are provided related to nanowire-based detectors, which can be used for light detection in, for example, single-photon detectors. In one aspect, a variety of detectors are provided, for example one including an electrically superconductive nanowire or nanowires constructed and arranged to interact with photons to produce a detectable signal. In another aspect, fabrication methods are provided, including techniques to precisely reproduce patterns in subsequently formed layers of material using a relatively small number of fabrication steps. By precisely reproducing patterns in multiple material layers, one can form electrically insulating materials and electrically conductive materials in shapes such that incoming photons are redirected toward a nearby electrically superconductive materials (e.g., electrically superconductive nanowire(s)). For example, one or more resonance structures (e.g.
    Type: Application
    Filed: May 27, 2011
    Publication date: March 29, 2012
    Applicant: Massachusetts Institute of Technology
    Inventors: Karl K. Berggren, Xiaolong Hu, Daniele Masciarelli
  • Publication number: 20120028806
    Abstract: Disclosed herein is a topologically protected ?/8-gate which becomes universal when combined with the gates available through quasi-particle braiding and planar quasi-particle interferometry. A twisted interferometer, and a planar ?/8-gate in CTS, implemented with the help of the twisted interferometer, are disclosed. Embodiments are described in the context of state X (CTS) supported by an ISH, although the concept of a twisted-interferometer is more general and has relevance to all anionic, i.e. quasiparticle systems.
    Type: Application
    Filed: May 19, 2011
    Publication date: February 2, 2012
    Applicant: Microsoft Corporation
    Inventors: Parsa Bonderson, Michael Freedman, Chetan Nayak, Kevin Walker, Lukasz Fidkowski
  • Patent number: 8088713
    Abstract: To prepare a superconducting fault-current limiting element having a high sharing electric field at low cost, a superconducting fault-current limiting element includes an insulator substrate; a superconductive thin film formed on the insulator substrate; and an alloy layer formed on the superconducting thin film, said alloy layer having a room-temperature resistivity higher by twice or more than the room-temperature resistivity of a pure metal, in which, when the superconducting thin film goes into a normal conductive state by an overcurrent, the overcurrent flowing through the superconducting thin film is transferred only to the alloy layer.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: January 3, 2012
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Hirofumi Yamasaki, Mitsuho Furuse
  • Patent number: 8043716
    Abstract: Disclosed herein is a gradient thin film, formed on a substrate by simultaneously depositing different materials on the substrate using a plurality of thin film deposition apparatuses provided in a vacuum chamber, wherein the gradient thin film is formed such that the composition thereof is continuously changed depending on the thickness thereof by deposition control plates provided in the path through which the different materials move to the substrate. The gradient thin film is advantageous in that the thin film is formed by simultaneously depositing different materials using various deposition apparatuses, so that the composition thereof is continuously changed depending on the thickness thereof, with the result that the physical properties of a thin film are easily controlled and the number of deposition processes is decreased, and thus processing time and manufacturing costs are decreased, thereby improving economic efficiency.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: October 25, 2011
    Assignee: Korea Electrotechnology Research Institute
    Inventors: Ho Sup Kim, Sang Soo Oh, Tae Hyung Kim, Dong Woo Ha, Kyu Jung Song, Hong Soo Ha, Rock Kil Ko, Nam Jin Lee
  • Publication number: 20110251071
    Abstract: The application relates to electricity, electro-physics and thermo conductivity of materials, to the phenomena of zero electric resistance, i.e. to hyperconductivity (superconductivity) and zero thermal resistance, i.e. to superthermoconductivity of materials at near-room and higher temperatures. The matter: on the surface of in the volume of non-degenerate or poorly degenerate semiconductor material or layer of such material on semi-insulating or dielectric substrate the electrodes are located forming rectifying contacts to the material. The distance between the electrodes (D) is chosen much smaller comparing to the depth of penetration into the material of the electric field caused by their contact difference of potentials (L), (D<<L) Minimum distance between the electrodes DMIN=20 nanometers, maximum distance between the electrodes DMAX=30 micrometers.
    Type: Application
    Filed: May 26, 2009
    Publication date: October 13, 2011
    Inventor: Vyacheslav Andreevich Vdovenkov
  • Patent number: 8003571
    Abstract: A composite structure is provided including a base substrate, an IBAD oriented material upon the base substrate, and a cubic metal oxide material selected from the group consisting of rare earth zirconates and rare earth hafnates upon the IBAD oriented material. Additionally, an article is provided including a base substrate, an IBAD oriented material upon the base substrate, a cubic metal oxide material selected from the group consisting of rare earth zirconates and rare earth hafnates upon the IBAD oriented material, and a thick film upon the cubic metal oxide material. Finally, a superconducting article is provided including a base substrate, an IBAD oriented material upon the base substrate, a cubic metal oxide material selected from the group consisting of rare earth zirconates and rare earth hafnates upon the IBAD oriented material, and an yttrium barium copper oxide material upon the cubic metal oxide material.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: August 23, 2011
    Assignee: Los Alamos National Security, LLC
    Inventors: Liliana Stan, Quanxi Jia, Stephen R. Foltyn
  • Patent number: 7979101
    Abstract: It is possible to improve the negative resistance characteristic that can be expected when an SNS (superconductor-normal conductor-superconductor) structure is used as a structure unit for series connection. On the top of a first superconducting electrode, a second superconducting electrode is superimposed so as to sandwich an insulation film between the first and second superconducting electrodes, with parts of cross sections of the second superconducting electrode and insulation film placed on the top. A normal superconducting line electrically connects the first and second superconducting electrodes passing along the cross section of the insulation film, thereby constituting a structure unit having a single weak link. A plurality of such structure units connected in series are prepared. At the both ends of the series the first or second superconducting electrode is an element connected to a leading line.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: July 12, 2011
    Assignee: National Institute of Information and Communications Technology, Incorporated Administrative Agency
    Inventors: Toshiaki Matsui, Hiroshi Ohta, Akira Kawakami
  • Patent number: 7858558
    Abstract: A superconducting thin film material that can realize attainment of an excellent property such as a high JC and a high IC and reduction of costs at the same time includes an orientated metal substrate and an oxide superconductor film formed on the orientated metal substrate. The oxide superconductor film includes a physical vapor deposition HoBCO layer formed by a physical vapor deposition method, and a metal organic deposition HoBCO layer formed on the physical vapor deposition HoBCO layer by a metal organic deposition method.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: December 28, 2010
    Assignees: Sumitomo Electric Industries, Ltd., International Superconductivity Technology Center, the Juridical Foundation
    Inventors: Shuji Hahakura, Kazuya Ohmatsu, Munetsugu Ueyama, Katsuya Hasegawa
  • Patent number: 7732376
    Abstract: The present invention relates to a method of preparing an oxide superconducting film, the method includes reacting a metal acetate containing metal M selected from the group consisting of lanthanum, neodymium and samarium with fluorocarboxylic acid having not less than three carbon atoms, reacting barium acetate with fluorocarboxylic acid having two carbon atoms, reacting copper acetate with fluorocarboxylic acid having not less than two carbon atoms, respectively, followed by refining reaction products, dissolving the reaction products in methanol such that a molar ratio of the metal M, barium and copper is 1:2:3 to prepare a coating solution, and coating a substrate with the coating solution to form a gel film, followed by calcining and firing the gel film to prepare an oxide superconducting film.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: June 8, 2010
    Assignees: Kabushiki Kaisha Toshiba, International Superconductivity Technology Center
    Inventors: Takeshi Araki, Koichi Nakao, Izumi Hirabayashi
  • Patent number: 7560291
    Abstract: A layered article of manufacture and a method of manufacturing same is disclosed. A substrate has a biaxially textured MgO crystalline layer having the c-axes thereof inclined with respect to the plane of the substrate deposited thereon. A layer of one or more of YSZ or Y2O3 and then a layer of CeO2 is deposited on the MgO. A crystalline superconductor layer with the c-axes thereof normal to the plane of the substrate is deposited on the CeO2 layer. Deposition of the MgO layer on the substrate is by the inclined substrate deposition method developed at Argonne National Laboratory. Preferably, the MgO has the c-axes thereof inclined with respect to the normal to the substrate in the range of from about 10° to about 40° and YBCO superconductors are used.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: July 14, 2009
    Assignee: UChicago Argonne, LLC
    Inventors: Uthamalingam Balachandran, Beihai Ma, Dean Miller
  • Patent number: 7547661
    Abstract: An superconductive article and method of forming such an article is disclosed, the article including a substrate and a layer of a rare earth barium cuprate film upon the substrate, the rare earth barium cuprate film including two or more rare earth metals capable of yielding a superconductive composition where ion size variance between the two or more rare earth metals is characterized as greater than zero and less than about 10×10?4, and the rare earth barium cuprate film including two or more rare earth metals is further characterized as having an enhanced critical current density in comparison to a standard YBa2Cu3Oy composition under identical testing conditions.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: June 16, 2009
    Assignee: Los Alamos National Security, LLC
    Inventors: Judith L. Driscoll, Stephen R. Foltyn
  • Publication number: 20090027140
    Abstract: Disclosed is an arrangement including a support and a super-conductive film which is arranged thereon. The film has a plurality of holes in order to form a perforated grating. The holes are optionally round holes having increasing sizes, triangular holes, or holes which are arranged in a meandering manner in the film, and which produce improved properties in relation to signal conversion by a vortex diode and/or in a filter. A DC signal is directly removed therein without additional electronics.
    Type: Application
    Filed: June 28, 2006
    Publication date: January 29, 2009
    Inventor: Roger Woerdenweber
  • Patent number: 7247603
    Abstract: A Superconducting Quantum Interference Device (SQUID) is disclosed comprising a pair of resistively shunted Josephson junctions connected in parallel within a superconducting loop and biased by an external direct current (dc) source. The SQUID comprises a semiconductor substrate and at least one superconducting layer. The metal layer(s) are separated by or covered with a semiconductor material layer having the properties of a conductor at room temperature and the properties of an insulator at operating temperatures (generally less than 100 Kelvins). The properties of the semiconductor material layer greatly reduces the risk of electrostatic discharge that can damage the device during normal handling of the device at room temperature, while still providing the insulating properties desired to allow normal functioning of the device at its operating temperature. A method of manufacturing the SQUID device is also disclosed.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: July 24, 2007
    Assignee: Star Cryoelectronics
    Inventors: Robin Harold Cantor, John Addison Hall
  • Patent number: 7012275
    Abstract: A layered article of manufacture and a method of manufacturing same is disclosed. A substrate has a biaxially textured MgO crystalline layer having the c-axes thereof inclined with respect to the plane of the substrate deposited thereon. A layer of one or more of YSZ or Y2O3 and then a layer of CeO2 is deposited on the MgO. A crystalline superconductor layer with the c-axes thereof normal to the plane of the substrate is deposited on the CeO2 layer. Deposition of the MgO layer on the substrate is by the inclined substrate deposition method developed at Argonne National Laboratory. Preferably, the MgO has the c-axes thereof inclined with respect to the normal to the substrate in the range of from about 10° to about 40° and YBCO superconductors are used.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: March 14, 2006
    Assignee: The University of Chicago
    Inventors: Uthamalingam Balachandran, Beihai Ma, Dean Miller
  • Patent number: 6911665
    Abstract: A superconducting integrated circuit includes a substrate, a multilayer structure formed on the substrate and composed of a lower superconducting electrode, a tunnel barrier and an upper superconducting electrode sequentially joined together upward in the order mentioned, and an insulating layer perforated to form via holes to get electrical contacts with the lower and upper electrodes. The insulating layer is formed of a high-resolution, photosensitive, solvent-soluble, organic insulating material. The superconducting integrated circuit is produced by a method that includes the steps of depositing the multiplayer on the substrate, applying the insulating material to the front surface of the substrate inclusive of the multiplayer, forming the via holes in the insulating material by the lithographic technique at the prospective positions to get electrical contacts with the upper and lower electrodes, and laying wirings for connecting the upper and lower electrodes through the via holes.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: June 28, 2005
    Assignees: National Institute of Advanced Industrial Science and Technology, PI R&D Co., Ltd.
    Inventors: Masahiro Aoyagi, Hiroshi Nakagawa, Kazuhiko Tokoro, Katsuya Kikuchi, Hiroshi Itatani, Sigemasa Segawa
  • Patent number: 6787798
    Abstract: A method includes providing a superconducting material having pinning sites that can pin magnetic vortices within the superconducting material. The method also includes pinning one or more magnetic vortices at one or more of the pinning sites. An information storage apparatus includes a superconducting material, doped particles within the superconducting material that can pin dipole magnetic vortices, a magnetic tip that generates pinned magnetic vortices and a magnetic detector that detects pinned magnetic vortices.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: September 7, 2004
    Assignee: The Texas A&M University System
    Inventors: Malcolm J. Andrews, Joseph H. Ross, Jr., John C. Slattery, Mustafa Yavuz, Ali Beskok, Karl T. Hartwig, Jr.
  • Patent number: 6719924
    Abstract: There is provided a superconducting device including a substrate, a first superconductor layer supported by the substrate and containing Ln, AE, M and O, and a second superconductor layer containing a material represented by a formula of (Yb1−yLn′y)AE′2M′3Oz, the first and second superconductor layers forming a junction, and atomic planes each including M and O in the first superconductor layer and atomic planes each including M′ and O in the second superconductor layer being discontinuous to each other in a position of the junction, wherein each of Ln and Ln′ represents at least one metal of Y and lanthanoids, each of AE and AE′ represents at least one of alkaline earth metals, each of M and M′ represents a metal which contains 80 atomic % or more of Cu, y represents a value between 0 and 0.9, and z represents a value between 6.0 and 8.0.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: April 13, 2004
    Assignees: Kabushiki Kaisha Toshiba, International Superconductivity Technology Center
    Inventors: Toshihiko Nagano, Jiro Yoshida
  • Patent number: 6635368
    Abstract: A film-based HTS device comprises a substrate and a superconducting film. A peripheral portion of the film is a-axis-aligned material which is so situated on the substrate as to describe a-b planar barriers which are perpendicular to the substrate and which in parallel fashion border upon the entire periphery of the film. The a-b planar barriers serve to block vortices which nucleate at the film's periphery, thereby attenuating the overall vortex activity associated with the film, thereby attenuating the ELF and white noise which are normally prevalent in superconductor devices. Effectiveness in terms of arresting vortex motion may be increased by providing an interior film portion which is also a-axis-aligned material. It may be preferable to provide an interior film portion which is c-axis-aligned material, since this is easier to make and the a-axis-aligned peripheral portion of the film will be sufficiently effective in terms of “pinning” the vortices.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: October 21, 2003
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Yehoshua Dan Agassi
  • Patent number: 6345189
    Abstract: A flux-pinning system comprised of a high temperature superconductor film on a carrier wherein the film is provided with a multiplicity of holes of a radius of 50 to 2000 nm serves as the basis for an electronic component which can be utilized in high frequency and radial frequency circuits and in conjunction with SQUIDs. The holes can be arranged with variable density over the film or in the form of a uniform hexagonal or square grid and the high temperature superconductor is preferably a YBa2Cu3O7 composition. The film has a configuration of a high frequency component and may be strip shaped or loop shaped.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: February 5, 2002
    Assignee: Forschungszentrum Julich GmbH
    Inventor: Roger Wördenweber
  • Patent number: 6345190
    Abstract: A flux-pinning system comprised of a high temperature superconductor film on a carrier wherein the film is provided with a multiplicity of holes of a radius of 50 to 2000 nm serves as the basis for an electronic component which can be utilized in high frequency and radial frequency circuits and in conjunction with SQUIDs. The holes can be arranged with variable density over the film or in the form of a uniform hexagonal or square grid and the high temperature superconductor is preferably a YBa2Cu3O7 composition. The film has a configuration of a high frequency component and may be strip shaped or loop shaped.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: February 5, 2002
    Assignee: Forschungszentrum Julich GmbH
    Inventor: Roger Wördenweber
  • Publication number: 20020006876
    Abstract: The present invention relates to a revolution member supporting apparatus for holding and rotating a disc-shaped object (object to be rotated) such as a semiconductor wafer. A revolution member supporting apparatus, comprising: a rotatable member which rotates about an axis of rotation; and a plurality of holding members which are disposed along a circle having a center corresponding to the axis of rotation of the rotatable member, and which revolve around the axis of rotation when the rotatable member rotates; wherein the holding members are allowed to swing about their own central axes.
    Type: Application
    Filed: April 27, 2001
    Publication date: January 17, 2002
    Inventors: Akihisa Hongo, Ichiro Katakabe, Shinya Morisawa
  • Patent number: 6320369
    Abstract: A superconducting current measuring circuit is provided with a detection loop through which a current flows by the influence of a magnetic field generated by a measurement target current. The detection loop contains a superconductor. The superconducting current measuring circuit is also provided with a superconducting sampler circuit for measuring the current flowing through the detection loop.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: November 20, 2001
    Assignee: NEC Corporation
    Inventors: Mutsuo Hidaka, Shuichi Tahara
  • Patent number: 6274412
    Abstract: A process sequence is disclosed for fabricating arrays of Thin Film Transistors by printing metallic conductors for the gate and data lines and possibly the Indium Tin Oxide Pixel electrode as well. The process eliminates conventional step-and-repeat photolithographic patterning, and provides high conductivity metallization for large arrays. These arrays may be used in displays, detectors and scanners.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: August 14, 2001
    Assignee: Parelec, Inc.
    Inventors: Paul H. Kydd, Sigurd Wagner, Helena Gleskova
  • Patent number: 6270908
    Abstract: A laminate article comprises a substrate and a biaxially textured (RExA(1−x))2O2−(x/2) buffer layer over the substrate, wherein 0<x≦0.70 and RE is selected from the group consisting of La, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. A is selected from the group consisting of Zr+4, Ce+4, Sn+4, and Hf+4. The (RExA(1−x))2O2−(x/2) buffer layer can be deposited using sol-gel or metal-organic decomposition. The laminate article can include a layer of YBCO over the (RExA(1−x))2O2−(x/2) buffer layer. A layer of CeO2 between the YBCO layer and the (RExA(1−x))2O2−(x/2) buffer layer can also be include. Further included can be a layer of YSZ between the CeO2 layer and the (RExA(1−x))2O2−(x/2) buffer layer. The substrate can be a biaxially textured metal, such as nickel. A method of forming the laminate article is also disclosed.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: August 7, 2001
    Assignee: UT-Battelle, LLC
    Inventors: Robert K. Williams, Mariappan Paranthaman, Thomas G. Chirayil, Dominic F. Lee, Amit Goyal, Roeland Feenstra
  • Patent number: 6258459
    Abstract: The first object of the invention is to provide means that enables a perovskite oxide thin film having (100) orientation, (001) orientation or (111) orientation to be easily obtained, and the second object of the invention is to provide a multilayer thin film comprising a unidirectionally oriented metal thin film of good crystallinity. The multilayer thin film according to the first embodiment of the invention comprises a buffer layer and a perovskite oxide thin film present thereon. The interface between the buffer layer and the perovskite oxide thin film is made up of a {111} facet plane. Substantially parallel to the facet plane there is present a {110} face of a cubic, rhombohedral, tetragonal or orthorhombic crystal of the perovskite oxide thin film, a {101} face of the tetragonal or orthorhombic crystal or a {011} face of the orthorhombic crystal.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: July 10, 2001
    Assignee: TDK Corporation
    Inventors: Takao Noguchi, Yoshihiko Yano
  • Patent number: 6175749
    Abstract: A flux-pinning system comprised of a high temperataure superconductor film on a carrier wherein the film is provided with a multiplicity of holes of a radius of 50 to 2000 nm serves as the basis for an electronic component which can be utilized in high frequency and radial frequency circuits and in conjuction with SQUIDs. The holes can be arranged with variable density over the film or in the form of a uniform hexagonal or square grid and the high temperature superconductor is preferably a YBa2Cu3P7 composition.
    Type: Grant
    Filed: June 22, 1998
    Date of Patent: January 16, 2001
    Assignee: Forschungszentrum Julich GmbH
    Inventor: Roger W{overscore (o)}rdenweber
  • Patent number: 6096434
    Abstract: A film structure includes a conductive oxide thin film formed on a substrate having a silicon (100) face at its surface. The conductive oxide thin film is an epitaxial film composed mainly of strontium ruthenate. At least 80% of the surface of the conductive oxide thin film has a Rz of up to 10 nm. On the conductive oxide thin film having excellent surface flatness and crystallinity, a ferroelectric thin film, typically of lead zirconate titanate, having surface flatness and spontaneous polarization can be formed.
    Type: Grant
    Filed: March 19, 1998
    Date of Patent: August 1, 2000
    Assignee: TDK Corporation
    Inventors: Yoshihiko Yano, Takao Noguchi
  • Patent number: 6088604
    Abstract: A superconductor-normal conductor junction device comprises first and second regions (1, 3) of normal material forming first and second junctions with a superconducting material (2), the Fermi level of the first region of normal material being so arranged relative to a given energy level in the superconducting material that charge carriers in the first normal material undergo Andreev reflection at the first junction, resulting in pairs of the charge carriers entering said given energy level in the superconducting material, and the Fermi level of the second region of normal material being so arranged relative to said given level in the superconducting material that said charge carriers conduct from the superconducting material through the second region.
    Type: Grant
    Filed: January 19, 1995
    Date of Patent: July 11, 2000
    Assignee: Hitachi, Ltd.
    Inventors: David Arfon Williams, Adrian Michael Marsh, Haroon Ahmed, Bruce William Alphenaar
  • Patent number: 6069369
    Abstract: Superconducting device include a type having a structure of a superconductor--a normal-conductor (or a semiconductor)--a superconductor, and a type having a superconducting weak-link portion between superconductors.The superconductors constituting the superconducting device are made of an oxide of either of perovskite type and K.sub.2 NiF.sub.4 type crystalline structures, containing at least one element selected from the group consisting of Ba, Sr, Ca, Mg, and Ra; at least one element selected from the group consisting of La, Y, Ce, Sc, Sm, Eu, Er, Gd, Ho, Yb, Nd, Pr, Lu, and Tb; Cu; and O. In addition, the c-axis of the crystal of the superconductor is substantially perpendicular to the direction of current flowing through this superconductor.
    Type: Grant
    Filed: October 24, 1997
    Date of Patent: May 30, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Toshikazu Nishino, Ushio Kawabe, Yoshinobu Tarutani, Shinya Kominami, Toshiyuki Aida, Tokuumi Fukazawa, Mutsuko Hatano
  • Patent number: 6051846
    Abstract: A method for the fabrication of active semiconductor and high-temperature superconducting device of the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.
    Type: Grant
    Filed: April 1, 1993
    Date of Patent: April 18, 2000
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Michael J. Burns, Paul R. de la Houssaye, Graham A. Garcia, Stephen D. Russell, Stanley R. Clayton, Andrew T. Barfknecht
  • Patent number: 6023072
    Abstract: A Josephson junction having a laminar structure which includes a substrate, a first superconductive layer deposited on the substrate, a non-superconductive layer deposited on the first superconductive layer, and a second superconductive layer deposited on the non-superconductive layer. The laminar structure has three segments, including: a first planar segment, a second planar segment, and a ramp segment connecting the two planar segments at an ascent angle thereto. The layers are of substantially uniform thickness in the three segments, with the substrate being thinner in the second planar segment than in the first planar segment and having a constantly-decreasing thickness in the ramp segment. The superconductive layers and the non-superconductive layer are deposited in-situ and are epitaxial with a c-axis in a direction substantially normal to the first and second planar segments.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: February 8, 2000
    Assignee: TRW Inc.
    Inventor: Arnold H. Silver
  • Patent number: 5916697
    Abstract: A material formed as a film comprised of monomolecular layers (2,3,4,5) stacked on a substrate (1), wherein said film includes at least one first set (R) of layers which form an electric charge reservoir, and a second set (S) of layers which form a conductive cell and which contain a number of conductive copper oxide layers (4), separated from each other by intermediate layers (5), the reservoir and the conductive cell being adjacent in the layer stack. There are at least four conductive copper oxide layers, and the intermediate layers have the chemical formula Ca.sub.1-x M.sub.x and are free of strontium, wherein x is a real number between 0 and 0.2, M is a component with an ionic radius close to that of the Ca.sup.2+ ion, and the intermediate layers may be complete or not.
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: June 29, 1999
    Assignees: Michael Lagues, Jacques Lewiner, Ufinnova
    Inventor: Michel Lagues
  • Patent number: 5912503
    Abstract: A method of fabricating a low-inductance, in-line resistor includes the steps of: depositing a superconductive layer 12 on a base layer 14; patterning an interconnect region 16 on the superconductive layer 12; and converting the interconnect region 16 of the superconductive layer 12 to a resistor material region 18. The resistor region 18 and the superconductive layer 12 are substantially in the same plane. The method can further include the steps of depositing a conductive layer 22 on the resistor region 18 and on the photo-resist layer 20, and lifting off the photo-resist layer 20 to leave the conductive layer 22 on the resistor region 18. As such, the conductive layer 22 provides a low sheet resistivity for the resistor region 18.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: June 15, 1999
    Assignee: TRW Inc.
    Inventors: Hugo W. Chan, Arnold H. Silver