Superconducting Transistor (e.g., Josephson Transistor, Etc.) Patents (Class 505/193)
  • Publication number: 20130123111
    Abstract: A device and a method of thermal management. In one embodiment, the device includes an integrated circuit, including: (1) a conductive region configured to be connected to a voltage source, (2) a transistor having a semiconductor channel with a controllable conductivity and (3) first and second conducting leads connecting to respective first and second ends of said channel, wherein a charge in the conductive region is configured to substantially raise an electrical potential energy of conduction charge carriers in the semiconductor channel and portions of said leads are located where an electric field produced by said charge is substantially weaker than near the semiconductor channel.
    Type: Application
    Filed: January 10, 2013
    Publication date: May 16, 2013
    Applicant: ALCATEL-LUCENT USA INC.
    Inventor: ALCATEL-LUCENT USA INC.
  • Patent number: 8274098
    Abstract: Provided are a field effect transistor, a logic circuit including the same and methods of manufacturing the same. The field effect transistor may include an ambipolar layer that includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the source region, the drain region, and the channel region may be formed in a monolithic structure, a gate electrode on the channel region, and an insulating layer separating the gate electrode from the ambipolar layer, wherein the source region and the drain region have a width greater than that of the channel region in a second direction that crosses a first direction in which the source region and the drain region are connected to each other.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: September 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-jong Chung, Ran-ju Jung, Sun-ae Seo, Dong-chul Kim, Chang-won Lee
  • Publication number: 20110287941
    Abstract: Disclosed herein is a topologically protected ?/8-gate which becomes universal when combined with the gates available through quasi-particle braiding and planar quasi-particle interferometry. A twisted interferometer, and a planar ?/8-gate in CTS, implemented with the help of the twisted interferometer, are disclosed. Embodiments are described in the context of state X (CTS) supported by an ISH, although the concept of a twisted-interferometer is more general and has relevance to all anionic, i.e. quasiparticle systems.
    Type: Application
    Filed: March 31, 2011
    Publication date: November 24, 2011
    Applicant: MICROSOFT CORPORATION
    Inventors: Parsa Bonderson, Michael Freedman, Chetan Nayak, Kevin Walker, Lukasz Fidkowski
  • Patent number: 7715892
    Abstract: A compact, solid-state THz source based on the driven Josephson vortex lattice in a highly anisotropic superconductor such as Bi2Sr2CaCu2O8 that allows cw emission at tunable frequency. A second order metallic Bragg grating is used to achieve impedance matching and to induce surface emission of THz-radiation from a Bi2Sr2CaCu2O8 sample. Steering of the emitted THz beam is accomplished by tuning the Josephson vortex spacing around the grating period using a superimposed magnetic control field.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: May 11, 2010
    Assignee: Uchicago Argonne, LLC
    Inventors: Ulrich Welp, Alexei E. Koshelev, Kenneth E. Gray, Wai-Kwong Kwok, Vitalii Vlasko-Vlasov
  • Patent number: 7610071
    Abstract: A compact, solid-state THz source based on the driven Josephson vortex lattice in a highly anisotropic superconductor such as Bi2Sr2CaCu2O8 that allows cw emission at tunable frequency. A second order metallic Bragg grating is used to achieve impedance matching and to induce surface emission of THz-radiation from a Bi2Sr2CaCu2O8 sample. Steering of the emitted THz beam is accomplished by tuning the Josephson vortex spacing around the grating period using a superimposed magnetic control field.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: October 27, 2009
    Assignee: UChicago Argonne, LLC
    Inventors: Ulrich Welp, Alexei E. Koshelev, Kenneth E. Gray, Wai-Kwong Kwok, Vitalii Vlasko-Vlasov
  • Publication number: 20080312088
    Abstract: Provided are a field effect transistor, a logic circuit including the same and methods of manufacturing the same. The field effect transistor may include an ambipolar layer that includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the source region, the drain region, and the channel region may be formed in a monolithic structure, a gate electrode on the channel region, and an insulating layer separating the gate electrode from the ambipolar layer, wherein the source region and the drain region have a width greater than that of the channel region in a second direction that crosses a first direction in which the source region and the drain region are connected to each other.
    Type: Application
    Filed: December 27, 2007
    Publication date: December 18, 2008
    Inventors: Hyun-jong Chung, Ran-ju Jung, Sun-ae Seo, Dong-chul Kim, Chang-won Lee
  • Patent number: 7451292
    Abstract: Quantum gaps exist between an origin and a destination that heretofore have prevented reliably utilizing the advantages of quantum computing. To predict the outcome of instructions with precision, the input data, preferably a qubit, is collapsed to a point value within the quantum gap based on a software instruction. After collapse the input data is restructured at the destination, wherein dynamics of restructuring are governed by a plurality of gap factors as follows: computational self-awareness; computational decision logic; computational processing logic; computational and network protocol and logic exchange; computational and network components, logic and processes; provides the basis for excitability of the Gap junction and its ability to transmit electronic and optical impulses, integrates them properly, and depends on feedback loop logic; computational and network component and system interoperability; and embodiment substrate and network computational physical topology.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: November 11, 2008
    Inventor: Thomas J Routt
  • Publication number: 20080108505
    Abstract: A strip-shaped superconductor has a conductor structure containing at least one metallic substrate strip, a layer made of oxidic high Tc superconducting material of the AB2Cu3OX type; an oxidic buffer layer, which is arranged therebetween and which has adapted crystalline dimensions, and; a normal-conductive top layer that is applied to the superconductive layer. The buffer layer should be formed so that a transition resistance of no greater than 10?3 ?cm2 is formed at least in partial areas between the superconductive layer and the substrate strip. For example, suitable materials are of the La—Mn—O or Sr—Ru—O or La—Ni—O or In—Sn—O type.
    Type: Application
    Filed: September 27, 2005
    Publication date: May 8, 2008
    Inventors: Hans-Peter Kramer, Wolfgang Schmidt
  • Patent number: 7332738
    Abstract: A method for reading out the state of a mesoscopic phase device. In the method the mesoscopic phase device is coherently coupled to a mesoscopic charge device using a phase shift device and the quantum state of the mesoscopic charge device is measured. A method for reading out the quantum state of a qubit in a heterogeneous quantum register. The heterogeneous quantum register includes a first plurality of phase qubits and a second plurality of charge qubits. In the method a first phase qubit or a first charge qubit in the heterogeneous quantum register is selected. The first phase qubit or the first charge qubit is coherently connected to a mesoscopic charge device for a duration tc. The quantum state of the mesoscopic charge device is read out after the duration tc has elapsed.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: February 19, 2008
    Assignee: D-Wave Systems Inc.
    Inventors: Alexandre Blais, Jeremy P. Hilton
  • Patent number: 7012275
    Abstract: A layered article of manufacture and a method of manufacturing same is disclosed. A substrate has a biaxially textured MgO crystalline layer having the c-axes thereof inclined with respect to the plane of the substrate deposited thereon. A layer of one or more of YSZ or Y2O3 and then a layer of CeO2 is deposited on the MgO. A crystalline superconductor layer with the c-axes thereof normal to the plane of the substrate is deposited on the CeO2 layer. Deposition of the MgO layer on the substrate is by the inclined substrate deposition method developed at Argonne National Laboratory. Preferably, the MgO has the c-axes thereof inclined with respect to the normal to the substrate in the range of from about 10° to about 40° and YBCO superconductors are used.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: March 14, 2006
    Assignee: The University of Chicago
    Inventors: Uthamalingam Balachandran, Beihai Ma, Dean Miller
  • Patent number: 6984846
    Abstract: A qubit (quantum bit) circuit includes a superconducting main loop that is electrically-completed by a serially-interconnected superconducting subloop. The subloop includes two Josephson junctions. A first coil provides a first flux that couples with the main loop but not with the subloop. A second coil provides a second flux that couples with the subloop but not with the main loop.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Dennis M. Newns, David P. DiVincenzo, Roger H. Koch, Glenn J. Martyna, Jim Rozen, Chang Chyi Tsuei
  • Patent number: 6784451
    Abstract: In one embodiment, a two-junction phase qubit includes a superconducting loop and two Josephson junctions separated by a mesoscopic island on one side and a bulk loop on another side. The material forming the superconducting loop is a superconducting material with an order parameter that violates time reversal symmetry. In one embodiment, a two-junction phase qubit includes a loop of superconducting material, the loop having a bulk portion and a mesoscopic island portion. The loop further includes a relatively small gap located in the bulk portion. The loop further includes a first Josephson junction and a second Josephson junction separating the bulk portion from the mesoscopic island portion. The superconducting material on at least one side of the first and second Josephson junctions has an order parameter having a non-zero angular momentum in its pairing symmetry. In one embodiment, a qubit includes a superconducting loop having a bulk loop portion and a mesoscopic island portion.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: August 31, 2004
    Assignee: D-Wave Systems Inc.
    Inventors: Mohammad H. S. Amin, Alexandre Zagoskin, Geordie Rose, Jeremy P. Hilton
  • Patent number: 6774463
    Abstract: In a Field Effect Transistor (FET) with a semiconductor channel the use of a high Tc oxide superconductor material in the gate electrode provides both control of parasitic resistance and capacitance and a proper work function when operated at a temperature below the Tc. The 1-2-3 compound oxide superconductors with the general formula Y1Ba2Cu3O7-y where y is approximately 0.1 have the ability in use in FET's to provide convenient work functions, low resistance and capacitance, and to withstand temperatures encountered in processing as the FET is being manufactured.
    Type: Grant
    Filed: February 24, 1992
    Date of Patent: August 10, 2004
    Assignee: International Business Machines Corporation
    Inventors: Praveen Chaudhari, Richard Joseph Gambino, Eti Ganin, Roger Hilsen Koch, Lia Krusin-Elbaum, Robert Benjamin Laibowitz, George Anthony Sai-Halasz, Yuan-Chen Sun, Matthew Robert Wordeman
  • Publication number: 20040077503
    Abstract: A circuit comprising a superconducting qubit and a resonant control system that is characterized by a resonant frequency. The resonant frequency of the control system is a function of a bias current. The circuit further includes a superconducting mechanism having a capacitance or inductance. The superconducting mechanism coherently couples the superconducting qubit to the resonant control system. A method for entangling a quantum state of a first qubit with the quantum state of a second qubit. In the method, a resonant control system, which is capacitively coupled to the first and second qubit, is tuned to a first frequency that corresponds to the energy differential between the lowest two potential energy levels of the first qubit. The resonant control system is then adjusted to a second frequency corresponding to energy differential between the lowest two potential energy levels of the second qubit.
    Type: Application
    Filed: April 17, 2003
    Publication date: April 22, 2004
    Inventors: Alexandre Blais, Jeremy P. Hilton, Alexandre M. Zagoskin
  • Patent number: 6719924
    Abstract: There is provided a superconducting device including a substrate, a first superconductor layer supported by the substrate and containing Ln, AE, M and O, and a second superconductor layer containing a material represented by a formula of (Yb1−yLn′y)AE′2M′3Oz, the first and second superconductor layers forming a junction, and atomic planes each including M and O in the first superconductor layer and atomic planes each including M′ and O in the second superconductor layer being discontinuous to each other in a position of the junction, wherein each of Ln and Ln′ represents at least one metal of Y and lanthanoids, each of AE and AE′ represents at least one of alkaline earth metals, each of M and M′ represents a metal which contains 80 atomic % or more of Cu, y represents a value between 0 and 0.9, and z represents a value between 6.0 and 8.0.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: April 13, 2004
    Assignees: Kabushiki Kaisha Toshiba, International Superconductivity Technology Center
    Inventors: Toshihiko Nagano, Jiro Yoshida
  • Patent number: 6670630
    Abstract: A superconducting structure that includes a mesoscopic phase device and a mesoscopic charge device. The superconducting structure further includes a mechanism for coupling the mesoscopic phase device and the mesoscopic charge device so that the quantum state of the mesoscopic phase device and the quantum state of the mesoscopic charge device interact. In another aspect, the superconducting structure includes a mechanism for reading out the quantum state of the mesoscopic charge device.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: December 30, 2003
    Assignee: D-Wave Systems, Inc.
    Inventors: Alexandre Blais, Jeremy P. Hilton
  • Patent number: 6649929
    Abstract: A method and structure for a d-wave qubit structure includes a qubit disk formed at a multi-crystal junction (or qubit ring) and a superconducting screening structure surrounding the qubit. The structure may also include a superconducting sensing loop, where the superconducting sensing loop comprises an s-wave superconducting ring. The structure may also include a superconducting field effect transistor.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: November 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Dennis M. Newns, Chang C. Tsuei
  • Patent number: 6605822
    Abstract: A method for performing a quantum computing entanglement operation between a phase qubit and a charge qubit. A coherent connection between the phase qubit and the charge qubit is provided. The coherent connection allows the quantum state of the phase qubit and the quantum state of the charge qubit to interact with each other. The coherent connection is modulated for a duration te. The phase qubit is connected to the charge qubit during at least a portion of the duration te in order to controllably entangle the quantum state of the phase qubit and the quantum state of the charge qubit.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: August 12, 2003
    Assignee: D-Wave Systems, Inc.
    Inventors: Alexandre Blais, Jeremy P. Hilton
  • Patent number: 6495854
    Abstract: A method and structure for a d-wave qubit structure includes a qubit disk formed at a multi-crystal junction (or qubit ring) and a superconducting screening structure surrounding the qubit. The structure may also include a superconducting sensing loop, where the superconducting sensing loop comprises an s-wave superconducting ring. The structure may also include a superconducting field effect transistor.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: December 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Dennis M. Newns, Chang C. Tsuei
  • Patent number: 6486756
    Abstract: A superconductor signal amplifier which receives an extremely small high-frequency signal having a frequency of tens of GHz generated in a superconductive circuit, amplifies the voltage of the high-frequency signal without a decrease in frequency, and outputs the thus amplified high-frequency signal from the superconductive circuit. At an output part of a single flux quantum circuit using a flux quantum as a binary information carrier, there are provided a superconductive junction line for flux quantum transmission and a splitter for simultaneously producing two flux quanta from a flux quantum. According to the number of plural series-connected SQUIDs, a plurality of flux quantum signals are generated and input to the plural series-connected SQUIDs so that the SQUIDs are simultaneously switched to a voltage state. In each SQUID pair comprising two SQUIDs, a part of an inductor is shared by the two SQUIDs for reduction in inductance, thereby increasing an output voltage of the series-connected SQUIDs.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: November 26, 2002
    Assignees: Hitachi, Ltd., International Superconductivity Technology Center
    Inventors: Yoshinobu Tarutani, Kazuo Saitoh, Kazumasa Takagi, Yoshihisa Soutome, Tokuumi Fukazawa, Akira Tsukamoto
  • Patent number: 6111268
    Abstract: The invention relates to an inverted JOFET with an at least bicrystalline electrically conductive substrate-layer bearing an insulating element and a superconductive element with a Josephson-junction. The substrate-layer is connected to a control-element. The invention further relates to a method for making such a JOFET. The grain boundary in the substrate-layer thereby maps into the Josephson-junction in the superconductive element.
    Type: Grant
    Filed: July 17, 1998
    Date of Patent: August 29, 2000
    Assignee: International Business Machines Corporartion
    Inventors: Jochen Mannhart, Bernd Mayer
  • Patent number: 6020596
    Abstract: A FET type superconducting device comprises a substrate having a principal surface, a thin superconducting channel formed of an oxide superconductor layer over the principal surface of the substrate, a superconducting source region and a superconducting drain region formed of an oxide superconductor layer over the principal surface of the substrate at the both ends of the superconducting channel which connects the superconducting source region and the superconducting drain region, so that superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region and a gate electrode on a gate insulator disposed on the superconducting channel for controlling the superconducting current flowing through the superconducting channel by a signal voltage applied to the gate electrode, wherein the superconducting device is isolated by a isolation layer directly formed on the principal surface of the substrate, the superconducting layer of the su
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: February 1, 2000
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takao Nakamura
  • Patent number: 5861361
    Abstract: A FET type superconducting device comprises a thin superconducting channel, a superconducting source region and a superconducting drain region formed of an oxide superconductor over a principal surface of the substrate, and a gate electrode on a gate insulator disposed on the superconducting channel for controlling the superconducting current flowing through the superconducting channel by a signal voltage applied to the gate electrode. The superconducting channel is formed of(Pr.sub.w Y.sub.1-w)Ba.sub.2 Cu.sub.3 O.sub.7-z (0<w<1, 0<z<1) oxide superconductororY.sub.1 Ba.sub.2 Cu.sub.3-v CO.sub.V O.sub.7-u (0<v<3, 0<u<1) oxide superconductor.These oxide superconductors have smaller carrier densities than the conventional oxide superconductor so that the superconducting channel has a larger thickness than the one funned of the conventional oxide superconductor.
    Type: Grant
    Filed: April 17, 1996
    Date of Patent: January 19, 1999
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: 5846846
    Abstract: Disclosed is a method for making a superconducting field-effect device with a grain boundary channel, the method comprising the steps of depositing a first superconducting thin film on a substrate; patterning the first superconducting thin film to form a patterned superconducting thin film having an opening; depositing a template layer thereon; selectively etching back the template layer to form a patterned template layer; growing a second superconducting thin film to form a grain boundary therebetween; depositing an insulating layer on the second superconducting thin film to protect the second superconducting thin film from degrading in property in the air; selectively etching back the insulating layer to form a patterned insulating layer; forming a gate insulating layer on the patterned insulating layer; and coating metal electrodes thereon, source/drain being formed respectively on the etched portions, and a gate electrode being formed on the deposited portion of the gate insulating layer directly above th
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: December 8, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jeong-Dae Suh, Gun-Yong Sung
  • Patent number: 5828079
    Abstract: A field-effect type superconducting device includes a channel layer. The channel layer includes Bi-based oxide compound containing Cu. A source electrode contacts the channel layer. A drain electrode contacts the channel layer. A gate insulating film made of insulating material extends on on the channel layer. A gate electrode extends on the gate insulating film.
    Type: Grant
    Filed: June 24, 1993
    Date of Patent: October 27, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Mizuno, Hideaki Adachi, Yo Ichikawa, Kentaro Setsune
  • Patent number: 5804835
    Abstract: This is an invention of a superconductive device that is equipped with a first superconductive electrode, a second superconductive electrode and a junction that is made of a superconductive material that connects these superconductive electrodes, wherein there are 2-terminal or 3-terminal superconductive devices that use a junction that is in a superconductive state that is weaker than the first and the second superconductive electrodes or in a normal conductive state that is near the superconductive state. The differences between the critical current, the critical temperature, the pair potential and the carrier densities of the first and the second superconductive electrodes and the junction are used as a means of putting the junction in the states mentioned above. Based on the methods mentioned above, a superconductive device which has few pattern rule restrictions and which is easy to fabricate can be offered.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: September 8, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Taketomi Kamikawa, Eiji Natori, Setsuya Iwashita, Tatsuya Shimoda
  • Patent number: 5793055
    Abstract: A step junction is provided for superconductor/semiconductor heterostructure hybrid devices like tunneling transistors, in a body of p-InAs with a vertical side connecting the low plateau and high plateau on which superconductors, preferably of niobium, are applied.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: August 11, 1998
    Assignee: Forschungszentrum Julich GmbH
    Inventor: Alexander Kastalsky
  • Patent number: 5789346
    Abstract: Method for manufacturing a superconducting device including forming on a surface of a substrate a non-superconducting oxide layer, a first oxide superconductor thin film, etching the first oxide superconductor thin film so as to form a concave portion, implanting ions to the first oxide superconductor thin film at the bottom of the concave portion so as to form an insulating region such that the first oxide superconductor thin film is divided into two superconducting regions by the insulating region, and forming a second oxide superconductor thin film on the insulating region and the two superconducting regions, which is continuous to the two superconducting regions.
    Type: Grant
    Filed: May 20, 1996
    Date of Patent: August 4, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5770470
    Abstract: The invention relates to a high temperature superconducting electric field effect device which creates a dual grain boundary on a superconducting thin film and employs it as a channel. The device comprises a substrate, a bottom layer formed on a predetermined region of the bottom layer, a dual grain boundary channel region formed on the bottom layer, a high temperature source and a drain formed at both end portions of the channel region on the substrate, a high temperature superconducting thin film channel layer formed a predetermined region on the source, the drain and the substrate, dual grain boundaries formed on the high temperature superconducting thin film channel layer, and a gate insulating layer formed on the dual grain boundary channel region.
    Type: Grant
    Filed: August 8, 1996
    Date of Patent: June 23, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Gun-Yong Sung, Jeong-Dae Suh
  • Patent number: 5717222
    Abstract: A superconducting device includes a substrate, a projecting insulating region formed in a principal surface of the substrate, and a first thin film portion of an oxide superconductor formed on the projecting insulating region. Second and third thin film portions of an oxide superconductor are positioned at opposite sides of the projecting insulating region to be continuous to the first thin film portion, respectively, so that a superconducting current can flow through the first thin film portion between the second thin film portion and the third thin film portion. The second thin film portion and the third thin film portion has a thickness larger than that of the first thin film portion. The projecting insulating region is formed of an oxide which is composed of the same constituent elements of the oxide superconductor but which has the oxygen content smaller than that of said oxide superconductor.
    Type: Grant
    Filed: May 23, 1996
    Date of Patent: February 10, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5714767
    Abstract: For manufacturing a superconducting device, a compound layer which is composed of the same constituent elements of an oxide superconductor is formed on a surface of the substrate, and a gate electrode is formed on a portion of the compound layer. Portions of the compound layer at both sides of die gate electrode are etched using die gate electrode as a mask, so that a shallow step is formed on an upper surface of the compound layer and side surfaces of the step exposed. After that electric power is applied to the gate electrode to heat the gate electrode so as to carry out a heat-treatment on the portion of die compound layer under the gate electrode locally, so that a gate insulator formed directly under the the gate electrode and a superconducting channel which is constituted an extremely thin superconducting region composed of the oxide superconductor and formed under die gate insulator are produced in a self alignment to die gate electrode.
    Type: Grant
    Filed: November 1, 1995
    Date of Patent: February 3, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5654259
    Abstract: The substance has a composition of a general chemical formula ofBi.sub.2 -(Sr.sub.2 Ca.sub.1).sub.1-x (La.sub.2 Y.sub.1).sub.x -Cu.sub.y -O.sub.z,where 0.4.ltoreq.x.ltoreq.1, y=2 and z=9-10.5, wherein the substance is an insulator or a semiconductor in the dark, and has a photoconductivity Q(.lambda.,T) in conjugate with superconductivity of a superconductor of an adjacent component of the Bi-SrCa-LaY-Cu-O system at and below a critical temperature (T) of less than 105.degree.-115.degree. K. and below 65.degree.-85.degree. K. at photoexcitation in an optical wavelength range (.lambda.) of 420-670 nm. The present invention relates to a method for producing the same and a superconductive optoelectronic device by using the same. The present invention also relates to an organized integration of the element or device into an apparatus to further develop a new field of "Superconductive Optoelectronics.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 5, 1997
    Assignee: The University of Tokyo
    Inventor: Taizo Masumi
  • Patent number: 5637555
    Abstract: A method for manufacturing a three-terminal superconducting device is disclosed. A superconducting channel constituted in an oxide superconductor thin film is deposited on a deposition surface of a substrate. A gate electrode for the device is formed through a gate insulator layer on the superconducting channel of the device. The steps of forming the gate electrode include forming a thin film that stands upright with respect to the insulator layer for the gate.
    Type: Grant
    Filed: August 23, 1995
    Date of Patent: June 10, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5629267
    Abstract: A superconducting element is disclosed which comprises a lower superconducting layer, an upper superconducting layer, and an intermediate layer interposed between the lower and upper superconducting layers. The lower and upper superconducting layers are both form of a superconducting cuprate. The intermediate layer is formed of a layered cuprate containing in the crystal structure thereof multiple fluorite blocks represented by the formula:[B]AE.sub.2 (RE1.sub.1-y RE2.sub.y).sub.m+1 Cu.sub.2 O.sub.z(wherein [B] stands for a block layer, AE for an alkaline earth element, RE1 for at least one element selected from the group consisting of lanthanide elements and actinoid elements which form ions of valency of larger than 3, RE2 for at least one element selected from the group consisting of lanthanide elements which form ions of valency of 3 and yttrium, m for a number satisfying the expression m.gtoreq.2, y for a number satisfying the expression 0.ltoreq.y<1, and z for the oxygen content).
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: May 13, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sumio Ikegawa, Tadao Miura
  • Patent number: 5621223
    Abstract: A superconducting device includes first and second oxide superconducting regions of a relatively thick thickness, formed directly on a principal surface of a substrate to be separate from each other, and a third oxide superconducting region of an extremely thin thickness which is formed directly on the principal surface of the substrate so as to bridge the first and second oxide superconducting regions. A barrier layer and a diffusion source layer are formed on the third oxide superconducting region, and an isolation region is formed to cover an upper portion or both side surfaces of the diffusion source layer. The first, second and third oxide superconducting regions and the isolation region are formed of the same oxide superconductor material, and the isolation region is diffused with a material of the diffusion source layer, so that the isolation region does not show superconductivity.
    Type: Grant
    Filed: August 16, 1995
    Date of Patent: April 15, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5596206
    Abstract: A new type of superconducting device is disclosed. The device embodies a superconducting ceramic film as an active part. A control electrode is provided on the superconducting film in which a passing current is controlled by applying a voltage on an intermediate portion of the film.
    Type: Grant
    Filed: April 4, 1995
    Date of Patent: January 21, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 5594257
    Abstract: A superconducting device comprises a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of an oxide superconductor formed on the principal surface, which can compensates the lattice mismatch between the substrate and the oxide superconductor, a superconducting source region and a superconducting drain region formed of c-axis oriented oxide superconductor thin films on the non-superconducting oxide layer, and an insulating region formed of a doped oxide superconductor on the non-superconducting oxide layer separating the superconducting source region and the superconducting drain region between them. On the insulating region an extremely thin superconducting channel formed of a c-axis oriented oxide superconductor thin film is arranged.
    Type: Grant
    Filed: June 24, 1993
    Date of Patent: January 14, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: 5552374
    Abstract: A superconducting device comprises a thin superconducting channel formed of an oxide superconductor, a superconducting source region and a superconducting drain region formed of an oxide superconductor at the both ends of the superconducting channel which connects the superconducting source region and the superconducting drain region, so that superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region. The superconducting device further includes a gate electrode through a gate insulator on the superconducting channel for controlling the superconducting current flowing through the superconducting channel. The length of the gate electrode ranges from one third of the length of the superconducting channel to one and a half length of the superconducting channel.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: September 3, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: So Tanaka, Michitomo IIyama
  • Patent number: 5547923
    Abstract: For manufacturing a superconducting device, a first oxide superconductor thin film having a very thin thickness is formed on a principal surface of a substrate, and a stacked structure of a gate insulator and a gate electrode is formed on a portion of the first oxide superconductor thin film. A second oxide superconductor thin film is grown on an exposed surface of the first oxide superconductor thin film, using the gate electrode as a mask, so that first and second superconducting regions having a relatively thick thickness are formed at opposite sides of the gate electrode, electrically isolated from the gate electrode. A source electrode and a drain electrode is formed on the first and second oxide superconducting regions. The superconducting device thus formed can functions as a super-FET.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 20, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5545612
    Abstract: A superconductor element includes a first layer of an oxide superconductor, a second layer of an insulator, semiconductor, or metal, and an interlayer interposed between the first and second layers and formed of AgO.sub.x (where in 0<.times.< 1/2) .
    Type: Grant
    Filed: May 1, 1995
    Date of Patent: August 13, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Mizushima, Jiro Yoshida, Koh-ichi Kubo
  • Patent number: 5539215
    Abstract: A superconducting device comprising a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of the oxide superconductor, a first and a second superconducting regions formed of c-axis oriented oxide superconductor thin films on the non-superconducting oxide layer separated from each other and gently inclining to each other, a third superconducting region formed of an extremely thin c-axis oriented oxide superconductor thin film between the first and the second superconducting regions, which is continuous to the first and the second superconducting regions.
    Type: Grant
    Filed: December 29, 1994
    Date of Patent: July 23, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5528052
    Abstract: Proposed is a method for operating a field-effect device comprised of a superconducting current channel having source and drain electrodes connected thereto, said superconducting current channel being separated from a gate electrode by an insulating layer, where the resistance of said current channel is controlled by varying the critical current of the superconducting material through the application of an electrical field across the superconducting current channel, which in turn changes the density of the mobile charge carriers in the superconducting material. Taught is also an inverted MISFET device for performing that method, the device being characterized in that on an electrically conductive substrate an insulating layer is provided which in turn carries a layer consisting of a superconducting material, and that a gate electrode is attached to said substrate, and source and drain electrodes are electrically connected to said superconductor layer.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: June 18, 1996
    Assignee: International Business Machines Corporation
    Inventors: Johannes G. Bednorz, Jochen D. Mannhart, Carl A. Mueller, Darrell G. Schlom
  • Patent number: 5514877
    Abstract: A superconducting device or a super-FET has a pair of superconducting electrode regions (20b,20c) consisting of a thin film (20)oxide superconductor being deposited on a substrate (5) and a weak link region (20a), the superconducting electrode regions (20b, 20c) being positioned at opposite sides of the weak link region (20a) these superconducting electrode regions (20b, 20c) and the weak link region (20a) being formed on a common plane surface of the substrate (5). The weak link region (20a) is produced by local diffusion of constituent element(s) of the substrate (5) into the thin film (20) of the oxide superconductor in such a manner that a substantial wall thickness of the thin film (20) of the oxide superconductor is reduced at the weak link region (20a) so as to leave a weak link or superconducting channel (10) in the thin film (20) of oxide superconductor over a non-superconducting region (50) which is produced by the diffusion.
    Type: Grant
    Filed: January 21, 1994
    Date of Patent: May 7, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5510324
    Abstract: The invention relates to a method of manufacturing a superconducting device, which comprises the steps of forming on a principal surface of a substrate a non-superconducting oxide layer having a similar crystal structure to that of a c-axis oriented oxide superconductor thin film and a flat-top projection at its center portion, forming a c-axis oriented oxide superconductor thin film having an extremely thin thickness on the non-superconducting oxide layer so as to form a superconducting channel on the projecting portion of the non-superconducting oxide layer, forming an insulating layer on the c-axis oriented oxide superconductor thin film so as to form a gate insulating layer on the superconducting channel, and forming an a-axis oriented oxide superconductor thin film so as to form a superconducting source region and a superconducting drain region of which upper surfaces have the same level as that of the superconducting channel.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: April 23, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama, Hiroshi Inada
  • Patent number: 5506197
    Abstract: A superconducting device comprising a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of the oxide superconductor, a first and a second superconducting regions formed of c-axis oriented oxide superconductor thin films on the non-superconducting oxide layer separated from each other and gently inclining to each other, a third superconducting region formed of an extremely thin c-axis oriented oxide superconductor thin film between the first and the second superconducting regions, which is continuous to the first and the second superconducting regions.
    Type: Grant
    Filed: September 16, 1994
    Date of Patent: April 9, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5494891
    Abstract: A superconducting device comprises a substrate, a non-superconducting layer formed in a principal surface of said substrate, an extremely thin superconducting channel formed of an oxide superconductor thin film on the non-superconducting layer. A superconducting source region and a superconducting drain region of a relatively thick thickness are formed of the oxide superconductor at the both sides of the superconducting channel separated from each other but electrically connected through the superconducting channel, so that a superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: February 27, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: 5480861
    Abstract: A layered structure formed on a substrate comprising an oxide superconductor thin film deposited on the substrate, a noble metal monolayer deposited on the oxide superconductor thin film and an insulator thin film deposited on the noble metal monolayer. The noble metal monolayer prevents interdiffusion between the oxide superconductor thin film and the insulator thin film so that they have excellent properties.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: January 2, 1996
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: So Tanaka, Michitomo Iiyama
  • Patent number: 5471069
    Abstract: A superconducting device includes a superconducting channel constituted in an oxide superconductor the film deposited on a deposition surface of a substrate. A source electrode and a drain electrode are formed on the oxide superconductor thin film at opposite ends of the superconducting channel, so that a superconducting current can flow through be superconducting channel between the superconductor source electrode and the superconductor drain electrode. A gate electrode is formed through a gate insulator layer on the superconducting channel so as to control the superconducting current flowing through the superconducting channel. The gate electrode is in the form of a thin film and stands upright with respect to the gate insulator layer.
    Type: Grant
    Filed: May 13, 1994
    Date of Patent: November 28, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5466664
    Abstract: A method of manufacturing a superconducting device involves forming a thin film on the surface of a substrate, forming a superconducting gate electrode on a portion of the thin film, etching the portions of the thin film using the gate electrode as a mask thereby providing a superconducting channel under the gate, forming a step portion on the superconducting channel and under the gate, converting the oxide portion of the step portion into a gate insulation portion by heating the substrate in a vacuum, forming a second oxide superconducting film on the exposed surface of the channel so that superconducting source and drain electrodes are formed on each side of the gate such that the drain and source have a thickness greater than that of the channel and are electrically isolated from the gate electrode.
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: November 14, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi Inada, Takao Nakamura, Michitomo Iiyama
  • Patent number: 5462916
    Abstract: The disclosed superconductive optoelectronic device with the basic substance Bi.sub.2 O.sub.3 or Bi.sub.2 O.sub.3 ;M.sup.2+ (M=Ca,Sr,Cu) of superconductive-conjugate photoconductivity has a substrate, a photoconductive gate region formed on the substrate, and a source region and a drain region formed on the substrate at opposite sides of the gate region so as to face toward each other across the gate region. The source region and the drain region are made of a Bi-based superconductive material. The gate region is made of such the basic material Bi.sub.2 O.sub.3 or Bi.sub.2 O.sub.3 ;M.sup.2+ (M=Ca,Sr,Cu) of superconductive-conjugate photoconductivity, which reveals photoconductivity at a temperature below the transition temperature of the above relevant Bi-based superconductive material. Also disclosed are superconductive optoelectronic devices formed of an organized integration of the above superconductive optoelectronic devices to develop effectively a new field of "Superconductive Optoelectronics".
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: October 31, 1995
    Assignee: The University of Tokyo
    Inventor: Taizo Masumi