Josephson Junction Type: (class 365/162) Patents (Class 505/832)
  • Patent number: 8971977
    Abstract: A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: March 3, 2015
    Assignee: Hypres, Inc.
    Inventors: Oleg A. Mukhanov, Alan M. Kadin, Ivan P. Nevirkovets, Igor V. Vernik
  • Patent number: 8738105
    Abstract: A superconducting integrated circuit may include a magnetic flux transformer having an inner inductive coupling element and an outer inductive coupling element that surrounds the inner inductive coupling element along at least a portion of a length thereof. The magnetic flux transformer may have a coaxial-like geometry such that a mutual inductance between the first inductive coupling element and the second inductive coupling element is sub-linearly proportional to a distance that separates the first inner inductive coupling element from the first outer inductive coupling element. At least one of the first inductive coupling element and the second inductive coupling element may be coupled to a superconducting programmable device, such as a superconducting qubit.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: May 27, 2014
    Assignee: D-Wave Systems Inc.
    Inventors: Andrew J. Berkley, Mark W. Johnson, Paul I. Bunyk
  • Patent number: 8003410
    Abstract: A method of operating a quantum system comprising computational elements, including an insulated ring of superconductive material, and semi-closed rings used as an interface between the computational elements and the external world, is disclosed. In one aspect, the method comprises providing an electrical signal, e.g. a current, in an input ring magnetically coupled to a computational element, which generates a magnetic field in the computational element and sensing the change in the current and/or voltage of an output element magnetically coupled to the computational element. The electrical input signal can be an AC signal or a DC signal. The computational element is electromagnetically coupled with other adjacent computational elements and/or with the interface elements. The corresponding magnetic flux between the computational elements and/or the interface elements acts as an information carrier. Ferromagnetic cores are used to improve the magnetic coupling between adjacent elements.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: August 23, 2011
    Assignees: IMEC, Katholieke Universiteit Leuven
    Inventors: Christoph Kerner, Wim Magnus, Dusan Golubovic
  • Patent number: 6787798
    Abstract: A method includes providing a superconducting material having pinning sites that can pin magnetic vortices within the superconducting material. The method also includes pinning one or more magnetic vortices at one or more of the pinning sites. An information storage apparatus includes a superconducting material, doped particles within the superconducting material that can pin dipole magnetic vortices, a magnetic tip that generates pinned magnetic vortices and a magnetic detector that detects pinned magnetic vortices.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: September 7, 2004
    Assignee: The Texas A&M University System
    Inventors: Malcolm J. Andrews, Joseph H. Ross, Jr., John C. Slattery, Mustafa Yavuz, Ali Beskok, Karl T. Hartwig, Jr.
  • Patent number: 6605225
    Abstract: A three-dimensional element is fabricated from a high-temperature superconductor. The method and apparatus can fabricate, for example, a single-electron tunnel device or an intrinsic Josephson device which utilize the layer structure peculiar to the high-temperature superconductor, with machining from the side surface of a monocrystal or thin film. In the focused-ion beam etching, a substrate holder which is rotatable about 360°, is rotated, at the minimum, through an angle of about 90°, and the thin film or monocrystal on the substrate is etched from the side surface thereof so as to fabricate the element. After the thin film or monocrystal is machined from above by means of an focused-ion beam to thereby form a bridge having a junction length, the sample is rotated by about 90° (270°). Subsequently, a multi-layer current path layer is formed through side-surface machining. The junction length is accurately controlled through measurement of the current path length from an image display.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: August 12, 2003
    Assignee: Japan Science and Technology Corporation
    Inventors: Tsutomu Yamashita, Sang-Jae Kim
  • Patent number: 5872731
    Abstract: A multi-state Josephson memory in a superconductor integrated circuit includes a plurality of superconductive quantum interference device (SQUID) memory cells 2 each having a SQUID 4 characterized by a SQUID loop inductance L and a junction critical current I.sub.c, which determine the number of memory states that can be stored in the SQUID 4. A gate current I.sub.g is transmitted to the superconductive inductors 6 and 8 of the SQUID 4 to perform a read operation by crossing a designated number of current threshold boundaries corresponding to the memory state stored in the SQUID, so that the Josephson junction 12 of the SQUID 4 generates a number of pulses corresponding to the memory state. A control current I.sub.con writes data to the SQUID 4 through a control current input 16, and is preferably magnetically coupled to the SQUID 4 through superconductive inductor pairs 18, 6 and 20, 8. In a preferred embodiment, a plurality of SQUID memory cells 70a, 70b, . . .
    Type: Grant
    Filed: October 10, 1997
    Date of Patent: February 16, 1999
    Assignee: TRW Inc.
    Inventors: Hugo W-K. Chan, Arnold H. Silver, Robert D. Sandell
  • Patent number: 5831278
    Abstract: A three-terminal device constructed from a Josephson junction with one or more asymmetric control lines is disclosed. The device is constructed with high temperature superconducting materials. The junction can be a bicrystal, SNS (Superconducting-Normal-Superconducting) or any other type of high temperature superconductor junction. The control line is either a conducting or superconducting material which is electrically isolated from the junction but inductively coupled into the junction. A portion of the control line is approximately directly above the junction and has current which at least partially flows parallel or nonparallel to current flowing across the junction. The control line current alters the magnetic field within the junction which changes the critical current of the junction. The junction is in a superconducting or resistive state depending on whether the bias current of the junction is greater than or less than the control current.
    Type: Grant
    Filed: March 15, 1996
    Date of Patent: November 3, 1998
    Assignee: Conductus, Inc.
    Inventor: Stuart J. Berkowitz
  • Patent number: 5629889
    Abstract: A superconducting fault-tolerant programmable read-only memory (SFT-PROM) cell stores information in the phases of superconducting wires in a Josephson array. The information is addressable and retrievable in a fault-tolerant manner due to the non local nature of the information stored. The coding and decoding process is content-addressable and parallel due to the multitude of interconnections, resulting in picosecond data access time. The SFT-PROM cell comprises superposed WRITE/READ arrays and a reset circuit that ensures multiple non-destructive read-out of data.
    Type: Grant
    Filed: December 14, 1995
    Date of Patent: May 13, 1997
    Assignee: NEC Research Institute, Inc.
    Inventors: Premala Chandra, Lev B. Loffe
  • Patent number: 5610857
    Abstract: A memory element for multiple bit storage uses a plurality of Josephson junction devices coupled in parallel between a ground plane and a superconductive line. A gate current is directly coupled to the superconductive line at a midpoint, and a control current is magnetically coupled to the superconductive line along its length. The current trajectory of the gate and control currents from an initial value to a quiescent point in the threshold curve traces determines the states of the modes. All the modes have a stable operating point at the quiescent point. The control current in the absence of the gate current is used to maintain the memory element at the quiescent point, and the gate current is used to momentarily transition none, one or more of the Josephson junction devices to a voltage state to determine the states of the modes at the quiescent point via appropriate Josephson sensors.
    Type: Grant
    Filed: March 25, 1996
    Date of Patent: March 11, 1997
    Assignee: Tektronix, Inc.
    Inventor: Vallath Nandakumar
  • Patent number: 5582877
    Abstract: A process for fabricating the Josephson junction includes the steps of preparing a substrate, forming a first superconducting layer, forming a second superconducting layer transversely on the first layer with an insulating layer interposed therebetween wherein the insulating layer is an oxide or nitride of the superconducting material, and injecting ion beams into the insulating layer so as to form low oxygen- or nitrogen-concentrated area linking the first and second layers.
    Type: Grant
    Filed: February 24, 1995
    Date of Patent: December 10, 1996
    Assignee: Shimadzu Corporation
    Inventors: Shinji Nagamachi, Masahiro Ueda, Kei Shinada, Mitsuyoshi Yoshii
  • Patent number: 5442195
    Abstract: A superconducting device may include a superconducting weak link equipped with plural superconducting devices that are used as input-output terminals formed on the same plane and at least one current source for applying current to at least one of these superconducting electrodes. A superconducting device suitable for high integration can be realized as it enables structuring of a superconducting weak link 1 equipped with plural superconducting electrodes 101, 102, 103 and 104 that can be used as input-output terminals and changing symmetry of superconducting electrode arrangement through the form of a normal conductor 201 which is forming a superconducting weak link. In addition, when this superconducting device is used as a quasi-particle injection type device, a superconducting device with plural superconducting electrodes that can be used for a gate electrode, drain electrode or control electrode can be realized. Further, a superconducting device equipped with new functions (e.g.
    Type: Grant
    Filed: October 18, 1993
    Date of Patent: August 15, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Saitoh, Toshikazu Nishino, Mutsuko Hatano
  • Patent number: 5438036
    Abstract: A SQUID comprises a substrate, a washer of an oxide superconductor thin film formed on a principal surface of the substrate, a hole shaped a similar figure to the washer at the center of the washer, a slit formed between one side of the washer and the hole, and a Josephson junction which connects portions of the washer at the both sides of the slit across the slit. In the SQUID, the ratio of similarity of the washer to the hole ranges 100 to 2500.
    Type: Grant
    Filed: April 19, 1993
    Date of Patent: August 1, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Matsuura, Hideo Itozaki
  • Patent number: 5401530
    Abstract: A process for producing a Josephson device is disclosed, wherein a Josephson junction is formed over a recess step by oblique deposition and a protective layer of conducting material or semiconducting material is formed on the Josephson junction. The actual thickness of the Josephson junction is controlled to be smaller due to the proximity effect.
    Type: Grant
    Filed: March 3, 1994
    Date of Patent: March 28, 1995
    Assignee: Osaka Gas Company, Ltd.
    Inventors: Itsuro Tamura, Satoshi Fujita, Masao Wada
  • Patent number: 5377141
    Abstract: A new type of superconducting memory is described. The composition of superconducting ceramic material used in the memory has been altered in order to expedite the formation of non-superconducting regions formed of grain boundaries. Non-superconducting regions may also be formed of lattice defects. Magnetic flux is trapped within the non-superconducting regions (grain boundaries or lattice defects). Information can be stored in terms of whether or not magnetic flux is trapped.
    Type: Grant
    Filed: June 21, 1991
    Date of Patent: December 27, 1994
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 5358928
    Abstract: A process for formulating non-hysteretic and hysteretic Josephson junctions using HTS materials which results in junctions having the ability to operate at high temperatures while maintaining high uniformity and quality. The non-hysteretic Josephson junction is formed by step-etching a LaAlO.sub.3 crystal substrate and then depositing a thin film of TlCaBaCuO on the substrate, covering the step, and forming a grain boundary at the step and a subsequent Josephson junction. Once the non-hysteretic junction is formed the next step to form the hysteretic Josephson junction is to add capacitance to the system. In the current embodiment, this is accomplished by adding a thin dielectric layer, LaA1O.sub.3, followed by a cap layer of a normal metal where the cap layer is formed by first depositing a thin layer of titanium (Ti) followed by a layer of gold (Au). The dielectric layer and the normal metal cap are patterned to the desired geometry.
    Type: Grant
    Filed: September 22, 1992
    Date of Patent: October 25, 1994
    Assignee: Sandia Corporation
    Inventors: David S. Ginley, Vincent M. Hietala, Gert K. G. Hohenwarter, Jon S. Martens, Thomas A. Plut, Chris P. Tigges, Gregory A. Vawter, Thomas E. Zipperian
  • Patent number: 5347143
    Abstract: A superconducting tunnel element, having a plurality of super conductors separated by barriers, the superconductors each comprising two physically separate but electrically connected superconducting layers and one insulated control layer. As a result, summation of the detection capacity or of the transmitting intensity becomes possible. Also, the simultaneous detection or transmission is permitted on arbitrary different frequencies or a summation of the signal intensity is possible in the case of SQUID-systems.
    Type: Grant
    Filed: August 9, 1993
    Date of Patent: September 13, 1994
    Assignee: Dornier Luftfahrt GmbH
    Inventor: Hehrwart Schroder
  • Patent number: 5323344
    Abstract: A quantum memory device in which a memory operation is enabled even if the structure of a Josephson device is reduced in size. Each memory cell of the quantum memory device includes a superconducting quantum interference device having two Josephson junctions, a write word line for supplying a current to the superconducting quantum interference device, a write data line and a magnetic field detection line magnetically coupled with the superconducting quantum interference device, a three-terminal switching device for turning a signal of the magnetic field detection line on and off to transfer the signal to a read data line, and a read word line connected to a gate of the three-terminal switching device. The junction area of the Josephson junction is made small to oscillate a magnetic flux so that information is stored in accordance with the phase of oscillation of the magnetic flux.
    Type: Grant
    Filed: January 5, 1993
    Date of Patent: June 21, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Kozo Katayama, Shiroo Kamohara
  • Patent number: 5318950
    Abstract: This device or junction is essentially constituted by a substrate made from an electrically insulating material (2), a vertical wall (4) formed on the substrate and extending in a given direction (x), said wall being made from said insulating material, a superconducting material ribbon (8) in two separate parts (10, 12) located on either side of the wall and bearing on the latter, the ribbon being oriented in a direction perpendicular to the said direction, and two interconnection contacts (14, 16) respectively placed on the two portions of the ribbon.
    Type: Grant
    Filed: January 27, 1993
    Date of Patent: June 7, 1994
    Assignee: France Telecom Etablissement (Autonome de Droit Public)
    Inventor: Jackie Etrillard
  • Patent number: 5313074
    Abstract: In a Josephson device which can be employed as a sensor including superconductor for measuring an extremely weak magnetic field, a Josephson junction consisting of superconducting material is formed, and a covering layer consisting of ordinary conducting metal or semiconductor is formed on the Josephson junction. This enables the Josephson junction to be isolated from the oxidized atmosphere. Further, the covering layer is not to present any deterioration such as cracks even upon being subjected to a thermal hysteresis from very low temperature to ordinary temperature.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: May 17, 1994
    Assignee: Osaka Gas Company Limited
    Inventors: Itsuro Tamura, Satoshi Fujita, Masao Wada
  • Patent number: 5306927
    Abstract: A high current amplifier, three terminal device, comprising a Josephson tunnel junction and a Schottky diode is configured so that the Josephson junction and Schottky diode share a common base electrode which is made very thin. Electrons which cross the Schottky barrier are supplied to the Josephson junction to obtain the amplified output current.
    Type: Grant
    Filed: August 15, 1991
    Date of Patent: April 26, 1994
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Bruce J. Dalrymple, Arnold H. Silver, Randy W. Simon
  • Patent number: 5306521
    Abstract: A method of manufacturing a DC superconducting quantum interference device comprises forming an insulating film over a portion of a resistance film. A lower electrode superconducting film is formed over the resistance film and the insulating film. A barrier layer is formed on a portion of the lower electrode superconducting film. An upper electrode is formed sandwiching the barrier layer between the lower electrode superconducting film and the upper electrode, so as to form a Josephson junction. To reduce the number of manufacturing steps, the lower electrode superconducting film is photolithographically patterned and/or etched to simultaneously form an input coil, a feedback coil and the Josephson junction. In another embodiment, after forming the upper electrode, an insulating film is formed over at least a portion of the lower electrode superconducting film. A superconducting film is formed over the insulating film in contact with the upper electrode.
    Type: Grant
    Filed: February 24, 1992
    Date of Patent: April 26, 1994
    Assignee: Seiko Instruments Inc.
    Inventors: Nobuhiro Shimizu, Kazuo Chinone, Norio Chiba
  • Patent number: 5286336
    Abstract: A Josephson junction and a method for its fabrication in which a laminated junction layer is formed in situ on the side edge of a base electrode contact. The laminated junction layer forms the Josephson junction of the present invention and includes an insulating or barrier layer sandwiched between a superconducting base electrode and a superconducting counter electrode. The Josephson junction is formed on the side edge of the base electrode contact to allow very small junction areas to be fabricated using conventional optical lithographic techniques, such as photolithography. The laminated junction layer is formed in situ, with the three layers of the laminated junction layer being formed successively without removing the device from the controlled atmosphere of the deposition system, to prevent contamination of the junction region.
    Type: Grant
    Filed: November 2, 1992
    Date of Patent: February 15, 1994
    Assignee: TRW Inc.
    Inventors: Hugo W. Chan, Arnold H. Silver, Robert D. Sandell, James M. Murduck
  • Patent number: 5260264
    Abstract: One or more superconducting memory cells capable of storing binary values as the presence or absence of a persisting loop current in their superconducting memory loops are connected in series by a circuit current line. This arrangement is provided with a set gate which switches to the voltage state and outputs circuit current from its output terminal to one end of the circuit current line when write command current is supplied to its control terminal and is further provided with a sense gate whose control terminal is series coupled though a capacitance element with the same one end of the circuit current line and whose ground side terminal is connected with the other end of the circuit control line thereby forming through the sense gate a read-out loop for receiving as differential current persisting loop current selectively discharged from the memory loop. The differential current causes the sense gate to switch itself to the voltage state and output a sense current.
    Type: Grant
    Filed: March 4, 1991
    Date of Patent: November 9, 1993
    Assignees: Agency of Industrial Science & Technology, Ministry of International Trade & Industry
    Inventors: Itaru Kurosawa, Hiroshi Nakagawa, Masahiro Aoyagi
  • Patent number: 5239187
    Abstract: Disclosed is a transistor or diode type Josephson effect device, at least two electrodes of which are made of superconductive material. If the Josephson effect is to be exerted in a semiconductor layer between the access electrodes, the distance between them should be smaller than the length of coherence, namely 10 to 1000 angstroms. According to the disclosure, the control channel between access electrodes is replaced by two channels perpendicular to the semiconductor layer, located between the two access electrodes and a layer of superconductive material placed between the substrate and the semiconductor layer. The disclosure can be applied to transistors, phototransistors and diodes with high switching speed.
    Type: Grant
    Filed: March 2, 1992
    Date of Patent: August 24, 1993
    Assignee: Thomson-CSF
    Inventors: Alain Schuhl, Stephane Tyc, Alain Friederich
  • Patent number: 5231295
    Abstract: A field-effect transistor comprises, on a substrate, a layer of semiconductor material incorporating natural or artificial inclusions of superconducting material. The source, drain and gate electrodes are made on this layer. Applications: field-effect transistors with low gate control voltage. FIG. 3.
    Type: Grant
    Filed: August 16, 1991
    Date of Patent: July 27, 1993
    Assignee: Thomson-CSF
    Inventors: Stephane Tyc, Alain Schuhl
  • Patent number: 5101243
    Abstract: A high T.sub.c oxide superconductive switching device [10] formed on a substantially planar substrate [18] includes a base electrode [12] comprised of a layer or film of anisotropic superconducting material. The layer has a first crystalline axis [c] along which a magnitude of an energy gap of the material is less than an energy gap of the material along other crystalline axes. The superconductive switching device further includes at least one injector electrode [14] forming a planar [16] or an edge tunneling junction with the base electrode for injecting, under the influence of a bias potential eV, quasiparticles into the base electrode. The first crystalline axis is aligned in a predetermined manner with the tunneling junction for optimizing a quasiparticle injection efficiency of the tunneling junction.
    Type: Grant
    Filed: May 21, 1990
    Date of Patent: March 31, 1992
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Chung J. Chi, Alan W. Kleinsasser
  • Patent number: 5053834
    Abstract: A thin film dc SQUID and its driving electronic circuitry configured with very high symmetry. The SQUID loop is formed with four holes at the respective ends of crossed slits. Each of these holes forms a single turn secondary for symmetrically arranged pairs of modulation coils and signal coils. The geometrical placement of the modulation coil transformers with respect to the signal coil transformers results in a device which nominally has no mutual inductance between the two groups of coils when the SQUID is biased for normal operation. The external driving circuit is configured to preserve the highly balanced nature of the chip and forces equal magnitudes of current to flow in all four of the bias leads.
    Type: Grant
    Filed: August 31, 1990
    Date of Patent: October 1, 1991
    Assignee: Quantum Magnetics, Inc.
    Inventor: Michael B. Simmonds
  • Patent number: 5039656
    Abstract: This invention relates to a magnetic memory including a first superconductor wire, a second superconductor wire disposed in such a manner as to cross the first superconductor wire substantially orthogonally, a first magnetic film disposed at the point of intersection between the first and second superconductor wires and a second magnetic film interposed between the first magnetic film and the first or second superconductor films, wherein at least one of the uniaxial magnetic anisotropy within the plane of the films and coercive force of the first and second magnetic films is mutually different. Furthermore, a superconductor film containing a large number of microscopic Josephson junctions is disposed between the first and second magnetic films or on the other side of the superconductor wire connected to the magnetic film, and a lead wire for applying a current is connected to the superconductor film.
    Type: Grant
    Filed: February 28, 1989
    Date of Patent: August 13, 1991
    Inventor: Yasuharu Hidaka
  • Patent number: 5011817
    Abstract: A noble unit cell structure in a magnetic memory is disclosed, in which a ferromagnetic film is sandwiched between first and second wires at a cross-over area, and third and fourth wires are provided so as to sandwich the first wire. The third wire is contacted with the first wire so as to form a ring portion surrounding the ferromagnetic film and the second wire. The fourth wire is isolated from the first wire. At least the first, second and third wires are made of superconductive material. The ferromagnetic film has a uniaxial anisotropy along the second wire and its magnetization direction can be reversed by applying pulse currents to the second and fourth wires in an information writing process. In a reading process, the magnetization direction of the ferromagnetic film can be recognized by detecting either one of a superconductive state or a normal conductive state at the ring portion of the first and third wires.
    Type: Grant
    Filed: January 27, 1989
    Date of Patent: April 30, 1991
    Assignee: NEC Corporation
    Inventors: Yasuharu Hidaka, Takashi Inoue
  • Patent number: 4994434
    Abstract: A process is disclosed of producing on a crystalline silicon substrate a barrier layer triad capable of protecting a rare earth alkaline earth copper oxide conductive coating from direct interaction with the substrate. A silica layer of at least 2000 .ANG. in thickness is deposited on the silicon substrate, and followed by deposition on the silica layer of a Group 4 heavy metal to form a layer having a thickness in the range of from 1500 to 3000 .ANG.. Heating the layers in the absence of a reactive atmosphere to permit oxygen migration from the silica layer forms a barrier layer triad consisting of a silica first triad layer located adjacent the silicon substrate, a heavy Group 4 metal oxide third triad layer remote from the silicon substrate, and a Group 4 heavy metal silicide second triad layer interposed between the first and third triad layers.
    Type: Grant
    Filed: March 21, 1989
    Date of Patent: February 19, 1991
    Assignee: Eastman Kodak Company
    Inventors: Liang-Sun Hung, John A. Agostinelli
  • Patent number: 4926082
    Abstract: Superconducting material improves the operating efficiency and reduces the operating power demand for a disk drive suitable for interchanging data with a magnetic or optic medium. The arm containing the head is moved along a path by a balanced superconductor-to-magnetic-field interface such as for radial positioning relative to a circular medium and is maintained in constant spatial relation with respect to the medium by advantageous application of superconductive layers and magnetic field sources. The superconductor environment also permits efficient bearing support for the medium as well as accommodating superconductor motors for driving the medium, and the use of various circuit elements associated with the drive electronics.
    Type: Grant
    Filed: April 12, 1989
    Date of Patent: May 15, 1990
    Assignee: University of Colorado Foundation, Inc.
    Inventor: Frank S. Barnes
  • Patent number: 4904619
    Abstract: A method of producing a Josephson junction device consisting of thin films of superconducting materials such as niobium and niobium nitride that work at cryogenic temperatures, in which a base electrode layer, tunnel barrier layer and a counterelectrode layer constituting a Josephson junction are formed on a substrate. In order to form a desired electrode pattern on the counterelectrode layer, a resist pattern is used as a mask for dry etching, followed by a plasma ashing process for ablating part of the resist in order to form a terrace-shaped portion at the edges and corners of the counterelectrode pattern by reforming and shrinking the cross-sectional geometry of the resist. Then, a thin insulating film for covering the edged layers is deposited over the entire surface of substrate, followed by the removal of said resist pattern together with said insulating film deposited on said resist pattern in order to form a protecting layer around the counterelectrode pattern.
    Type: Grant
    Filed: February 1, 1988
    Date of Patent: February 27, 1990
    Assignee: Hitachi Ltd.
    Inventors: Hirozi Yamada, Sachiko Kizaki, Hiroyuki Mori, Yoshinobu Tarutani, Mikio Hirano
  • Patent number: 4878094
    Abstract: A self-powered electronic component, particularly, a Josephson junction, is formed of a layer of a superconductor epitaxially grown on a substrate formed of a single crystal of silicon. In accordance with one embodiment of the invention, the expitaxial superconductor layer is separated into two parts by a groove defined by a thin growth region, forming the Josephson junction. On the epitaxial layer at the first side of the junction is deposited a thin layer of an insertion material forming the positive pole of the Josephson junction as well as the cathode of a solid state power generator. On the epitaxial layer and over the thin layer of insertion material is deposited a separator, or fast ion conductor, which assumes the weak link of the Josephson junction as well as separates the ion source from the electronic exchanger and assumes the fast ion transport.
    Type: Grant
    Filed: March 30, 1988
    Date of Patent: October 31, 1989
    Inventor: Minko Balkanski
  • Patent number: H873
    Abstract: A method of making a Josephson Junction is disclosed which includes the steps of depositing a base electrode layer of a refractory superconducting material on a substrate, depositing a first passivation layer on the base electrode, depositing a barrier layer of refractory insulating semiconducting material on the passivation layer, depositing a second passivation layer on the barrier layer, and depositing a counter electrode on the second passivation layer. The layers are deposited at a substrate temperature of from about 50.degree. C. to about 700.degree. C. in an Ultra-High Vacuum sputtering system at a base pressure of less than or equal to 5.times.10.sup.-8 Torr. In the preferred embodiment a base electrode and counter electrode of NbN are separated by a barrier layer of hydrogenated silicon. When exposed to high post processing temperatures this structure maintains a chemically stable interface with the substrate.
    Type: Grant
    Filed: June 30, 1989
    Date of Patent: January 1, 1991
    Assignee: United States of America
    Inventors: Edward Cukauskas, William Carter