Random Access (i.e., Bit Organized Memory Type): (class 365/160) Patents (Class 505/841)
  • Patent number: 5629889
    Abstract: A superconducting fault-tolerant programmable read-only memory (SFT-PROM) cell stores information in the phases of superconducting wires in a Josephson array. The information is addressable and retrievable in a fault-tolerant manner due to the non local nature of the information stored. The coding and decoding process is content-addressable and parallel due to the multitude of interconnections, resulting in picosecond data access time. The SFT-PROM cell comprises superposed WRITE/READ arrays and a reset circuit that ensures multiple non-destructive read-out of data.
    Type: Grant
    Filed: December 14, 1995
    Date of Patent: May 13, 1997
    Assignee: NEC Research Institute, Inc.
    Inventors: Premala Chandra, Lev B. Loffe
  • Patent number: 5388068
    Abstract: Superconducting-semiconducting hybrid memories are disclosed. These superconducting-semiconducting hybrid memories utilize semiconductor circuits to store information, and either superconducting or semiconducting or combinations of superconducting and semiconducting circuits, with at least some superconducting circuitry used, to write and read information. The state of memory cells in the hybrid memories is determined by utilizing superconductor current sensing schemes to detect currents in the bit-line, thereby avoiding any bit-line charging delays and other problems associated with purely semiconductor memories. Additional features of the superconducting-semiconducting hybrid memories include wide margins, dense packing of memory cells, low power dissipation and fast access times. Interface curcuitry for converting superconducting signals to signals compatible with semiconductor circuits and for converting semiconductor signals to signals compatible with superconducting circuits is also disclosed.
    Type: Grant
    Filed: October 14, 1993
    Date of Patent: February 7, 1995
    Assignee: Microelectronics & Computer Technology Corp.
    Inventors: Uttam S. Ghoshal, Harry Kroger
  • Patent number: 5332722
    Abstract: A novel nonvolatile memory element or cell comprising a memory means consisting of at least one superconducting ring (21, 22) and a detector means consisting of a MOSFET. The superconducting ring and the MOSFET are arranged in such a manner that a magnetic flux created by the superconducting ring (21, 22) passes through a channel zone of the MOSFET. Information is held in the superconducting ring in a form of permanent current and is detected electrically as variation in the conductivity of the channel zone of the MOSFET.
    Type: Grant
    Filed: March 8, 1993
    Date of Patent: July 26, 1994
    Assignee: Sumitomo Electric Industries, LTD
    Inventor: Mitsuka Fujihira
  • Patent number: 5323344
    Abstract: A quantum memory device in which a memory operation is enabled even if the structure of a Josephson device is reduced in size. Each memory cell of the quantum memory device includes a superconducting quantum interference device having two Josephson junctions, a write word line for supplying a current to the superconducting quantum interference device, a write data line and a magnetic field detection line magnetically coupled with the superconducting quantum interference device, a three-terminal switching device for turning a signal of the magnetic field detection line on and off to transfer the signal to a read data line, and a read word line connected to a gate of the three-terminal switching device. The junction area of the Josephson junction is made small to oscillate a magnetic flux so that information is stored in accordance with the phase of oscillation of the magnetic flux.
    Type: Grant
    Filed: January 5, 1993
    Date of Patent: June 21, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Kozo Katayama, Shiroo Kamohara
  • Patent number: 5130273
    Abstract: A read only memory device comprises a first electrode, and a second electrode arranged overlapping with the first electrode so as to be geometrically in connection at the intersection. At least one of the first and second electrodes is formed of a ceramics system high temperature superconductor. A prescribed electrode out of said electrodes which is formed of the high temperature superconductor has a high resistance region for insulating the first and second electrodes from each other at the intersection corresponding to a prescribed stored data.In the manufacturing method, the first and second electrodes are formed and, thereafter, a high resistance region is formed by irradiating focused ion beam.
    Type: Grant
    Filed: January 7, 1991
    Date of Patent: July 14, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoji Mashiko, Tadashi Nishioka
  • Patent number: 4990489
    Abstract: A read only memory device includes a first electrode and a second electrode arranged in an overlapping relation with the first electrode so as to be geometrically in connection at an intersection therewith corresponding to a storage location for one type of data. At least one of the first and second electrodes is formed of a ceramics system high temperature superconductor. A prescribed one of the two electrodes which is formed of the high temperature superconductor has a high resistance region for insulating the first and second electrodes from each other at an intersection corresponding to a storage location for another type of stored data. The high resistance region is formed by irradiating an intersection with a focused ion beam.
    Type: Grant
    Filed: July 6, 1988
    Date of Patent: February 5, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoji Mashiko, Tadashi Nishioka