Abstract: A test system including a device under test (DUT) and a tester, where the DUT includes I/O interface logic and a clock circuit. The clock circuit includes a core clock circuit, a pad clock circuit, a test clock circuit, and a select circuit. The core clock circuit generates a core clock signal enabling full speed operation of core circuitry of the IC during test mode. The pad clock circuit generates a preliminary clock signal suitable for normal operation, and the test clock circuit generates a test clock signal suitable for operating the I/O interface logic during the test mode. The select circuit selects, based on the test signal, between the test clock signal and the preliminary clock signal as the pad clock signal. The tester provides the bus clock signal and indicates the test mode to the DUT via the I/O interface logic.

Abstract: A system and method for accurately estimating the fluctuating pressure loads on components, such as steam dryers, within a BWR steam dome using pressure time history measurements made on components of the BWR facility external to the steam dome. The method uses existing sensors to obtain the pressure time histories. An accurate determination of the fluctuating pressure loads within the steam dome may be obtained by modeling and analyzing the steam delivery system external to the steam dome, including all possible acoustic sources, using acoustic circuit methodology and pressure time histories, and then coupling these results, essentially as part of the boundary conditions, to the solutions for Helmholtz equation within the steam dome.

Abstract: A frequency error estimation algorithm is presented for use in radio receivers, for example. The present algorithm utilizes irregular time intervals between pilot symbols to improve the frequency range of the estimate. First, a first phase rotation indicator comprising information on phase rotation of a received signal within a first time interval is estimated. Then, a second phase rotation indicator comprising information on phase rotation of the received signal within a second time interval of a different length than the first time interval is estimated. A frequency error estimate is calculated from the phase difference between the first phase rotation indicator and the second phase rotation indicator, for example by dividing the phase difference by the difference in the lengths of the first and the second time interval.

Abstract: A controller of an optical disk device includes: a first sub-controller, a second sub-controller and a third sub-controller. The first sub-controller includes serially connected a first lead-lag filter and a first low pass filter. The second sub-controller includes a second lead-lag filter and a second low pass filter that are serially connected. The third sub-controller includes serially connected a second lead-lag filter, a third low pass filter and a extra lead-lag filter. A parameter calibrating apparatus and method for the controller is also disclosed.

Abstract: The present invention provides systems and methods for performing frequency margin testing of a computer system, such as a server. A system of the invention can include a controller, e.g., a BMC, internal to the computer system and a digital frequency synthesizer that can communicate with the controller and can apply clock frequency to marginable components of the computer system. In response to commands from the controller, the synthesizer generates one or more test frequencies that are applied to one or more of the marginable components. The response of the system to each of the test frequencies is then monitored.

Abstract: An improved signal processing method and apparatus are presented for use in real-time sub-nanometer scale position measurements with the aid of probing sensors and/or beams scanning periodically undulating surfaces such as a grating and diffraction patterns generated thereby, and the like, enabling greater sub-nanometer precision, higher stage scanner movement speeds, and simultaneous high accuracy and top speed measuring capabilities.

Abstract: A method and a circuit for correcting duty cycle distortion. A delay insertion gate corrects data dependent delay distortion that is generated by CMOS flip-flop circuits. The delay insertion gate includes two field effect transistors and a current mirror. The two transistors each respectively receive an input signal from an upstream circuit. At least one of the transistors is coupled to an output node. The output node temporarily holds a voltage state within the delay insertion gate, correcting any distortion in the duty cycle of the input signals.

Abstract: A calibration module, for use in calibrating a VNA, includes ports connectable to the VNA, calibration standards, and single pole multi throw (SPMT) switches. Each SPMT includes a single pole terminal, multiple throw terminals and a shunt terminal corresponding to each multiple throw terminal. A switching path is between each throw terminal and the single pole terminal, and between each shunt terminal and the single pole terminal. Each switching path includes at least one solid state switching element. The calibration standards are selectively connectable to the ports of the calibration module by selectively controlling the switching elements. Each port of the calibration module is directly connected to a throw terminal of one of the SPMT switches. Also, unique algorithm are provided for calibrating a VNA when using a calibration impedance that is a hybrid of a reflect standard and a transmission standard, which can be achieved using the calibration module.

Abstract: An apparatus for determining the torque imposed on a rotatable shaft. The shaft has at least four paired probes, paired horizontal probes and paired vertical probes. The horizontal probes are positioned 90 degrees apart from the vertical probes. If the shaft moves horizontally, the time of arrival detected by the first horizontal probes will be later than a nominal value and the time of arrival for the second horizontal probes will be earlier than a nominal value with the same amount of error. Combining data from the first and second horizontal probes will then automatically cancel out any error from horizontal motion. Similarly, combining data from vertical probes will eliminate the error due to vertical movement. Because any radial movement is a combination of horizontal and vertical movements, the use of the probes removes errors due to movement in any direction.

Abstract: There is provided a jitter amplifier for amplifying or attenuating a jitter component contained in an input signal, having a jitter demodulating section for demodulating the jitter component from the input signal and an amplifying circuit for amplifying or attenuating the jitter component by controlling phase of the input signal based on the jitter component.

Abstract: There is provided a calibration apparatus for calibrating a jitter measuring circuit for outputting a jitter measuring signal corresponding to a value of jitter contained in an input signal, having a signal inputting section for sequentially inputting the first input signal having first period and the second input signal having second period to the jitter measuring circuit and a gain calculating section for calculating a gain in the jitter measuring circuit based on the jitter measuring signals to be outputted out of the jitter measuring circuit respectively with respect to the first and second input signals.

Abstract: A memory control device and a memory control method are provided to compensate for additional delay subsequent to the change in environmental factors and to permit a smooth writing operation. The memory control device includes a controller that calculates a number of delay cells that are necessary to delay a system clock for one period as delay information, and a compensation unit that generates a compensation control signal by using the delay information calculated by the controller signal. The compensation unit compensates for an additional delay which is subsequent to a change in environmental factors such as voltage or temperature.

Abstract: An RF power delivery diagnostic system is provided herein. The system comprises an RF power source (303), an impedance matching network (305), a plasma reactor (307) in electrical contact with the RF power source by way of the impedance matching network, a first RF sensor (309) adapted to measure at least one attribute of the RF power input to the impedance matching network, and a second RF sensor (311) adapted to measure at least one attribute of the RF power output by the impedance matching network.

Abstract: This invention relates to a method for processing seismic data comprising a collection of seismic traces with different offsets, comprising the steps of: a) breaking up one or several first trace(s) of the collection of seismic traces into a series of trace segments according to a predetermined segmentation interval; b) defining a series of expansion coefficients, each expansion coefficient being associated with a segment of the first trace or traces; c) applying the associated expansion coefficient to each segment of the first trace or traces; d) comparing the first trace or traces thus expanded with a second trace from the collection of seismic. traces to evaluate their similarity; e) repeating steps b), c) and d) with a new series of expansion coefficients, f) determining an optimum series of expansion coefficients that maximizes the similarity between the first expanded trace and the second trace in order to obtain one or several corrected first trace(s).

Abstract: A method and system for calculation of rotation dependent parameters in a system that senses shaft rotation of a toothed speed wheel. The method includes determining the passing edges of multiple gear teeth on a rotating speed wheel; calculating rotational speed of the rotating machine based on the passing edges of multiple gear teeth of the speed wheel; calculating a rotation independent tooth spacing correction factor for each gear tooth on the rotating wheel; and correcting the calculated rotational speed of the rotating machine using the tooth corrections.

Abstract: Phase and magnitude correction is performed in two dimensions to reduce ghosting in single shot and multi-shot EPI scans. First, a phase/magnitude correction in the readout direction is carried out to reduce echo shifts and gradient waveform distortions. Then, a two dimensional phase/magnitude correction is performed to remove the remaining xy phase/magnitude errors.

Abstract: A method for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values are collected in a histogram according to a folding of the samples around a timebase. The timebase is determined by sweeping to detect a minimum jitter for the folded data. The histogram for the correct estimated timebase period is representative of the probability density function of the location of data signal edges and the jitter characteristics are determined by the width and shape of the density function peaks. Frequency drift can be corrected by adjusting the timebase used to fold the data across the sample set.

Abstract: An apparatus and method for calibrating transmission paths in a multicarrier communication system using multiple antennas are provided. In the transmission path calibrating apparatus, a calibration processor generates reference signals to estimate distortions in phase and amplitude in transmission paths, allocates the generated reference signals to subcarriers which are different in each of the transmission paths, and calculates calibration vectors for the transmission paths using the generated reference signals and received reference signals received through the transmission paths. A baseband module IFFT-processes the generated reference signals allocated to the subcarriers and sends the IFFT signals in the transmission paths.

Abstract: Improved calibration of a dual-etalon frequency monitor having x-y outputs is provided. An ellipse is fit to the (x,y) points from a set of calibration data. For each (x,y) point, an angle ? is determined. A linear fit of frequency to ? is provided. Differences between this linear fit and the determined values of ? are accounted for by including a spline fit to this difference in the calibration.

Abstract: An artifact signal correction system may include a mixing component to generate a waveform corresponding to an artifact such as an error tone, whereupon that waveform may be combined with the input waveform to substantially eliminate the artifact. In preferred embodiments, a method and apparatus for reducing spurious tones in systems of mismatched interleaved digitizers due to interleave error is provided. In various embodiments the method may include reversing the frequency content of an input signal, converting the reversed signal into interleave artifact content, delaying the input signal along a parallel path, and then subtracting the interleave content from the delayed input signal.

Abstract: A method a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronously sampled (or alternatively a clock signal is latched). The data signal or a second signal is compared to a settable threshold voltage and sampled. The edge and comparison data are folded according to a swept timebase to find a minimum jitter period. The crossing of the signal diagram edges is determined from a peak of a histogram of the folded edge data. A histogram of ratios of the sample values versus displacement from the position of the crossing location is generated for each threshold voltage. The technique is repeated over a range of settable threshold voltages. Then, the ratio counts are differentiated across the histograms with respect to threshold voltage, from which a signal diagram is populated.

Abstract: A circuit for regulating power is disclosed. The present invention provides circuits and methods for current sensing variations, static droop settings, mismatched phase outputs, and temperature variations in a multiphase power regulator. The circuits may include a calibration controller that senses and regulates both a current sensing circuit and the droop in a power regulator over a range of temperatures thus equalizing phase outputs. The present invention includes the schematic organization and implementation of the circuit, the circuit's calibration, its use, and implementation. This invention advantageously provides circuits and methods to properly power a processor or IC chip according to the unique power specifications of the processor or chip.

Abstract: A system for determining a data converter operating mode includes measurement circuitry operable to measure a master clock frequency of a master clock signal, the master clock frequency measurement biased by a past operating mode selection, and operable to measure a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In an additional embodiment, the measurement circuitry biases the master clock frequency measurement based on a past master clock frequency measurement.

Abstract: A system for estimating clotting properties of blood, comprises a sensor generating an initial data signal associated with a measurement of clotting of the blood during an initial time period prior to a final clotting time of the blood and a processor determining parameters of an equation to curve fit the initial data signal, extrapolating the equation forward in time to a time at which a desired level of clotting is achieved and estimating from the extrapolated equation the final clotting time of the blood.

Abstract: The present invention provides an autonomous calibration of a multivariate based spectroscopic system that is preferably implemented as a multivariate based spectrometer. The spectroscopic system is based on a multivariate optical element that provides a spectral weighting of an incident optical signal. Spectral weighting is performed on the basis of spatial separation of spectral components and subsequent spatial filtering by means of a spatial light modulator. Calibration of the spectroscopic system is based on a dedicated calibration segment of the spatial light modulator, whose position corresponds to a characteristic calibration or reference wavelength of the incident optical signal. Preferably, the calibration or reference wavelength is given by the wavelength of the excitation radiation generated by the optical source that serves to induce scattering processes in a volume of interest.

Abstract: Real-time clock calibration is accomplished by generating a fast clock signal and a slow clock signal from an uncompensated clock signal; selectively, momentarily, replacing the uncompensated clock signal with the fast and slow clock signal to generate a compensated clock signal; generating from the compensated clock signal a calibration strobe and window trigger; responding to the window trigger to detect any uncompensated clock signal frequency error and responding to the calibration strobe to selectively, momentarily, replace the uncompensated clock signal with the fast or slow clock signal to reduce the clock signal frequency error.

Abstract: According to one embodiment, a phase-locked loop (PLL) device includes test circuitry for entering/exiting a test mode upon receiving a particular pulse train at a reference clock input of the PLL. In addition, exemplary methods are provided herein for entering a test mode and detecting loop filter leakage within the PLL. The methods described herein are performed without the use of a dedicated test pin.

Abstract: An asynchronous sampling arrangement utilizes sampling of both a high speed data signal and a trigger (clock) signal. The data signal may be either an optical signal or an electrical signal. The data and trigger signals are sampled in parallel by two separate gates, the gates based on the same strobe frequency. The samples corresponding to the trigger signal are then processed through an algorithm that determines the time-base related to the sampled signal. This established time-base is then used to reconstruct the sampled version of the high data rate input signal waveform.

Abstract: A quality assurance integrated circuit for a print controller is provided. The IC has a memory, a system clock having a ring oscillator for generating a clock signal, clock trim circuitry for trimming the clock signal generated by the system clock and a processor. The processor is arranged to, in response to receiving an external signal, determine the number of cycles of the clock or external signal during a predetermined number of cycles of the external or clock signal, respectively and to output the determined number of cycles to an external circuit, and, in response to receiving a trim value based on the determined number of cycles from the external circuit, store the trim value in the memory and control the clock trim circuitry to trim the frequency of the clock signal generated by the ring oscillator using the trim value.

Abstract: A method of digital phase calibration is disclosed. An input signal is sampled using a clock. The sample points of the sampled signal are changed by a scaler. A phase calibration is performed by adjusting the phase of the scaler to obtain an optimum phase for the scaler.

Abstract: A meter device for measuring electrical energy is provided. The meter device includes circuitry for measuring at least one parameter of electrical energy provided to the meter device. A storage device is provided for storing at least one calibration factor for compensating for errors associated with at least one of at least one current transformer (CT) and at least one potential transformer (PT) that operates on the electrical energy provided to the meter device. At least one processor is provided for processing the at least one calibration factor for adjusting the measuring for compensating for the errors when measuring the electrical energy.

Abstract: A method is disclosed to calibrate a system receiving an input signal and generating an output signal. The method provides an input signal, and generates an output signal. The method establishes a sampling rate comprising a reference frequency, samples the input signal at said sampling rate, and samples the output signal at the sampling rate. The method then forms a measured input signal waveform, forms a measured output signal waveform, determines at (P) harmonics of the reference frequency the real components and the imaginary components of the measured input signal waveform, forms a filtered input signal waveform, determines at (P) harmonics of the reference frequency the real components and imaginary components of the measured output signal waveform, and forms a filtered output signal waveform.

Abstract: A method and apparatus for determining jitter and pulse width from clock signal comparisons provides a low cost and production-integrable mechanism for measuring a clock signal with a reference clock, both of unknown frequency. The measured clock signal is sampled at transitions of a reference clock and the sampled values are collected in a histogram according to a folding of the samples around a timebase which is either swept to detect a minimum jitter for the folded data or is obtained from direct frequency analysis for the sample set. The histogram for the correct estimated period is statistically analyzed to yield the pulse width, which is the difference between the peaks of the probability density function and jitter, which corresponds to width of the density function peaks. Frequency drift is corrected by adjusting the timebase used to fold the data across the sample set.

Abstract: A boundary scan register circuit and a method of characterization testing. The boundary scan register circuit, including: a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch; means for isolating the boundary scan cells into one or more boundary scan segments, each boundary scan segment containing a different set of the boundary scan cells; and means for characterizing signal propagation through each boundary scan segment.

Abstract: An apparatus for measuring the time delay between adjacent clock edges includes target and delay signal paths, a variable delay module in said delay signal path, the delay cell having a delay bias input, and a phase detector having respective inputs coupled to the target and delay signal paths. The variable delay module is operable to delay a first clock signal on the delay path so that a bias input signal presented to the delay bias input, when a bias input signal is present, corresponds to the time delay between the first clock signal and a second clock signal on the target signal path.

Abstract: A system, apparatus and method for performing differential return loss measurements and other measurements as a function of frequency uses a digital storage oscilloscope (DSO) having spectral analysis functions. A waveform generator generates a differential test signal in the form of a series of pulses where each pulse includes spectral components associated with each of a plurality of frequencies of interest. A test fixture presents the differential test waveform to a load including at least one of a device under test (DUT), a short circuit, an open circuit and a balanced load. A signal acquisition device differentially measures the test waveform during each of the load conditions. The signal acquisition device computes an error correction parameter using measurements made during the short circuit, open circuit and balanced load conditions. The correction parameter tends to offset signal acquisition errors within measurements made during the DUT load condition.

Abstract: Method and apparatus are described for compensating for a linear time scale change in a received signal, so as to correctly rescale the frame sequence of the received signal. Firstly, an initial estimate of the sequence of symbols is extracted from the received signal. Successive estimates of correctly time scaled sequences of the symbols are then generated by interpolating the values of the initial estimates.

Abstract: A resolver-to-digital converting apparatus calculates a resolver rotational angle from two-phase sampling values that are the result of sampling two-phase output signals, which are obtained from a single-phase-excited, two-phase output resolver, at peak timings of a waveform. The apparatus includes a determination unit for determining whether each of the two-phase sampling values has deviated from a prescribed path of rotation by more than a predetermined amount when the two-phase sampling values are represented by orthogonal coordinates; a correction processing unit, responsive to a determination that the predetermined amount has been exceeded, for applying a correction to the two-phase sampling values using an equation of a tangent to the path of rotation at a point on the path of rotation at which the previous resolver rotational angle was obtained; and an angle calculation unit for obtaining a resolver rotational angle at the corrected two-phase sampling values obtained by correction processing.

Abstract: The present invention provides a fast testing system and method for optical transceiver, which integrates multiple testing machines in the testing environment for the optical transceiver, so that the user can employ the testing system for optical transceiver for rapid and simultaneous measurement of multiple products, and further improving the production efficiency. Moreover, with a combination of optical channel selector with a set of digital communication analyzer and spectrum analyzer, a plurality of products to be tested can be switched for parametric inspection, and by combining a tree coupler to synchronously transmit the measurement signals of the standard sample to the product to be tested in a multi-port transmission to further measure the bit error ratio. Thus, the product analysis report for the user is in real-time, so as to effectively improve the competitiveness of the industry.

Abstract: A radio frequency ID tag, very small in size and with an onboard antenna, is manufactured, tested and applied cost-efficiently. The transmit frequency for the tag is set during manufacture approximately, within a selected range, in a gross tuning step. A second tuning step fine tunes each tag by RF communication to set values of capacitance, resistance, etc., and this can be at the point of application of the tags. Other aspects include burning a randomly-selected value in the RF ID chip during manufacture to impose a random time delay for tag response (rather than having a random generator on the chip itself); structural testing of a large number of tags on a wafer using on-wafer interconnects and a special onboard sequencer test die; and production of the tag so as to be tunable to different frequency ranges.

Abstract: A semiconductor integrated circuit includes a first delay circuit generating a first delay clock; a second delay circuit generating a second delay clock; a first register registering a value of a first delay of the first delay clock; a second register registering a value of a second delay of the second delay clock; a clock supplying circuit supplying a clock signal to the first and second delay circuits; a phase comparator detecting a phase difference between the first and second delay clocks; and a built-in test circuit configured to control the first and second registers so that the value of the first delay can be registered in the first register and the value of the second delay can be registered in the second register.

Abstract: A flexible process optimizer for recording and analyzing various parameters to improve the efficiency of a production process. The flexible process optimizer acquires and conditions signals from a variety of transducers mounted on a production machine. Through qualitative and quantitative data analysis, specific aspects are of the production process which need improvement are identified. The qualitative evaluation looks at the presence, absence, or duration of certain features of the production cycle as revealed by the sensor data. The quantitative evaluation of data involves the computation of certain data attributes. By providing useful data acquisition and data analysis tools, necessary adjustments are made to the required parameters of the production process to provide improved efficiency. The results of the changes are immediately verifiable using the flexible process optimizer.

Abstract: A signal processing device is provided that includes a modulation unit that produces an amplitude element as well as a phase element from components that are applied thereto. A correction device is also provided, in which at least one of the components is supplied and is compared with an ideal nominal value. This is used to produce a correction factor, which is multiplied by the component which has been compared with the nominal value. The correction factor determined is used to correct any offset or distortion of the components produced by analog circuits.

Abstract: In order to further develop a system (100) and a method for calibrating the clock frequency of at least one clock generator unit (38), in particular oscillator unit, that is assigned to at least one transmitting/receiving module (30), wherein—the transmitting/receiving module (30) communicates with at least one microcontroller unit (10) over at least one data line (20) and—the clock generator unit (38) is assigned at least one calibration unit (36), in such a manner that with significantly reduced system costs the clock frequency of the clock generator unit (38) can be calibrated with very high accuracy, it is proposed that—in order to calibrate the clock frequency of the clock generator unit (38) at least one calibration unit (36) is assigned to the clock generator unit 38), —the calibration unit (36) can be set in binary terms by means of at least one command signal (COM) via the data line (20), —the clock generator unit (38) is assigned at least one binary counter (34) that is clocked by the clock generato

Abstract: A phase difference between a first periodic signal, and a sample signal corresponding to a second periodic signal and having a predetermined signal resolution M is calculated in a phase comparing method. The sample signal is obtained by sampling the second periodic signal at a sampling frequency fs for one signal cycle of the second periodic signal when a frequency of the second periodic signal is not greater than an allowable sampling signal frequency fab equal to fs/M or by conducting at least one of sampling the second periodic signal at fs for more than one signal cycle of the second periodic signal, and generating interpolated values for the sample signal after sampling the second periodic signal at fs in accordance with whether or not M/N yields a remainder and whether or not N is a prime number when the frequency of the second periodic signal is greater than and is N times fab.

Abstract: A method for extending dynamic range and a test system with extended dynamic range compensate for a compression effect on measured data caused by a receiver channel of the test system being compressed. The measured data is magnitude and phase data for one of a device under test and a signal under test that is measured using the test system. The method comprises characterizing a first channel of the test system for first channel compression responses to magnitude and phase, characterizing a second channel of the test system for second channel compression response to magnitude and phase, and compensating to correct for the effect of compression on the measured data. The test system comprises a receiver channel, and a computer program stored in memory that implements the method. Test systems with a plurality of receiver channels may be characterized in pairs.

Abstract: Disclosed is a method of controlling an asymmetric waveform generated as a combination of two sinusoidal waves having a frequency that differs by a factor of two. A method according to the instant invention includes a step of sampling a generated asymmetric waveform to obtain a set of data points, the set of data points being indicative of the generated asymmetric waveform. The sampled data points are arranged in an order according to magnitude, and then compared to template data relating to a desired asymmetric waveform. In dependence upon the comparison, a correction to the generated asymmetric waveform is determined.

Abstract: Systems and methods for pulse stretching architectures for phase alignment of multi-frequency clocks for high speed data acquisitions are disclosed. A high speed data acquisition system includes a transmitter and a receiver. The receiver includes a multi-frequency clock generator that generates a plurality of clock signals, a pattern check module that detects a test pattern received from the transmitter and outputs a stretch command signal, and a stretch pulse generator that receives the stretch command signal and provides a stretch pulse signal that aligns the phases of the plurality of clock signals generated by the multi-frequency clock generator. Methods for initializing and shifting multi-phase clock signals to optimize error performance of a high speed data acquisition system are also provided.

Abstract: In one embodiment, a request to perform a calibration process for automated test equipment (ATE) is received. The request is associated with a calibration parameter set. After receiving the request, one or more signatures for calibration data corresponding to the calibration parameter set are derived, and a determination is made as to whether calibration data corresponding to the signature(s) has already been generated. Thereafter, an incremental set of calibration data is generated, with the generated calibration data i) corresponding to the signature(s), but ii) not having already been generated. In another embodiment, a request to perform a calibration process for ATE is received, and the request is associated with specified test setups. An incremental set of calibration data corresponding to the specified test setups is then generated.

Abstract: An analog debugging block of an integrated circuit includes a multiplexor, a buffer, and a voltage-controlled oscillator. An analog voltage signal-of-interest is selectively passed through the multiplexor to the buffer. The buffer outputs an analog control voltage dependent on the selected analog voltage signal-of-interest. The analog control voltage serves as an input to the voltage-controlled oscillator and is used to control a frequency of a digital output signal generated from the voltage-controlled oscillator. The digital output signal from the voltage-controlled oscillator is driven off-chip, whereupon a frequency of the digital output signal is determined and compared against a collection of known frequencies that correspond to particular known voltages of the analog voltage signal-of-interest, thereby resulting in a determination of the value of the selected analog voltage signal-of-interest.