Having Multiple Filtering Stages Patents (Class 702/197)
  • Patent number: 6415247
    Abstract: A system identification device is provided capable of performing a sequential updating process and preventing the quantity of operation from becoming too complex. The system identification device includes a first delay for delay of y2 (n), a matrix generator, a plurality of matrix calculators, a second delay, a third delay and a matrix separator for identifying an unknown system.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: July 2, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Kimura, Hideaki Sasaki, Hiroshi Ochi
  • Patent number: 6122605
    Abstract: A closed loop feedback control system operates to maintain a process variable at or near a process variable setpoint. A digital filter is implemented with the controller to filter the process variable signal input to the controller. The filter includes both an amplitude filter to clip signal spikes and glitches and low pass filter to remove higher order, noise related frequencies from the signal, that could adversely affect computational speed of the controller.
    Type: Grant
    Filed: August 18, 1998
    Date of Patent: September 19, 2000
    Assignee: Johnson Controls Technology Company
    Inventors: Kirk H. Drees, Nebil Ben-Aissa, John E. Seem
  • Patent number: 6094626
    Abstract: A method and system for the identification of genetic information from a polynucleotide sequence is described. Genetic information from a raw polynucleotide sequence is identified by assigning values to nucleotide base changes along the raw polynucleotide sequence and processing these values. Particularly, a distribution of the values of the base changes is generated and the variance from a random distribution of this distribution is calculated by determining the root mean square variance of the distribution. The types of genetic information that can be identified using this system and method include the presence of a protein encoding region, or gene; the number of genes in a given overall polynucleotide sequence; the reading frame for the gene sequence; and tRNA and rRNA sites.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: July 25, 2000
    Assignee: Vanderbilt University
    Inventors: Thomas W. Kephart, Robert W. Cutler
  • Patent number: 5943642
    Abstract: A method of designing a subband digital filter bank having first and second analysis filters with a 2-band linear phase satisfies a perfect reconstruction (PR) condition and has transfer functions H0(z) and H1(z) separated into first and second polyphase components Hi0(z) and Hi1(z). The method includes designing H0(z) which is odd-symmetric or antisymmetric and has a degree of 2m+1, converting the PR condition into a matrix form, obtaining H11(z) according to the matrix obtaining H10(z) using H11(z), obtaining H1(z) from H10(z) and H11(z), and obtaining a general second transfer function H1'(z) using H0(z) and H1(z). The filter characteristic of the second analysis filter is adjusted by adjusting x1, and the symmetry or antisymmetry thereof is determined by K.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: August 24, 1999
    Assignee: SamSung Electronics Co., Ltd.
    Inventor: Han-Mook Choi
  • Patent number: 5925093
    Abstract: A sampling frequency converting apparatus according to present invention is such an apparatus in which, when a first digital signal of a sampling frequency Fsi is converted into a second digital signal of an arbitrary sampling frequency Fso by using a digital filter, the ratio between the sampling frequency Fsi and the sampling frequency Fso is obtained and this input/output sampling frequency ratio is utilized as a control amount for the sampling frequency conversion. The sampling frequency converting apparatus includes a buffer memory for temporarily storing the first digital signal, an operating unit for performing an interpolation processing with respect to the input/output sampling frequency ratio at every regular time and a calculating unit which calculates a read address of the buffer memory on the basis of the input/output sampling frequency ratio interpolated by the operating unit.
    Type: Grant
    Filed: October 7, 1997
    Date of Patent: July 20, 1999
    Assignee: Sony Corporation
    Inventor: Nobuyuki Yasuda