Abstract: Methods, apparatus, systems and articles of manufacture to create malware detection rules are disclosed. An example apparatus includes a rule generator to generate an augmented rule set based on a first training data set. A matrix generator is to create a matrix using the augmented rule set and a second training data set. A rule regulator to apply regularization to the augmented rule set based on the matrix to remove any number of rules from the augmented rule set, the rule regulator to create a reduced rule set. A reduced rule set checker to validate the reduced rule set.

Abstract: Systems, apparatuses, and methods for implementing a hybrid asynchronous gray counter with a non-gray zone detector are described. A circuit includes an asynchronous gray counter coupled to control logic. The control logic programs the asynchronous gray counter to operate in different modes to perform various functions associated with a high-performance phase-locked loop (PLL). In a first mode, the asynchronous gray counter serves as a frequency detector to count oscillator cycles within a reference clock cycle. In a second mode, the asynchronous gray counter serves as a coarse phase detector to detect a phase error between a feedback clock and a reference clock. In a third mode, the asynchronous gray counter serves as a multi-modulus divider to divide an oscillator clock down to create a feedback clock. Using a single asynchronous gray counter for three separate functions reduces power consumption and area utilization.

Abstract: A method and apparatus for photon, ion or particle counting described that provides seven orders of magnitude of linear dynamic range (LDR) for a single detector. By explicitly considering the log-normal probability distribution in voltage transients as a function of the number of photons, ions or particles present, the binomial distribution of observed counts for a given threshold, the mean number of photons, ions or particles can be determined well beyond the conventional limit.

Abstract: The present invention relates einen energy-self-sufficient multiturn rotary encoder for detecting a number of complete 360° revolutions of an encoder shaft, rotating about a rotational axis and to which an excitation magnet is mounted in a rotationally fixed manner for generating an external magnetic field, as well as for determining an absolute rotational angle indicating a fine-resolved position within one 360° revolution of the encoder shaft, wherein the multiturn rotary encoder for energy-self sufficiently detecting the number of the complete 360° revolutions of the encoder shaft several functional blocks comprises. Further, a corresponding method is taught.

Abstract: A frequency calibration apparatus, applied to a phase locked loop (PLL), includes a frequency detecting module and a search module. The frequency detecting module includes a first counter, a second counter and a comparing unit. During a monitoring period, the first counter and the second counter respectively generates a first count and a second count. The comparing unit compares the first count with the second count to generate a comparison result indicating at least three situations. The search module selects a frequency curve in response to the comparison result, and calibrates configuration of a voltage controlled oscillator (VCO) according to the frequency curve.

Abstract: A semiconductor device capable of determining plural transfer speeds with a small-scale circuit, and an information processing system having the semiconductor device are provided. The semiconductor device has a frequency determining circuit that receives a data signal on which plural transfer speeds can be set and that determines a transfer speed of the data signal. The frequency determining circuit latches the data signal at each of plural timings continuing with a predetermined interval, detects how many times a data switching occurs consecutively, based on the latched plural data, and determines the transfer speed of the data signal from the result of the detection.

Abstract: Provided are a circuit control system and method for dynamically adjusting voltage and frequency. The circuit control system herein includes: a lookup table module configured to store a combined table of voltage-frequency corresponding relation curves of a target circuit under one or more working conditions; a converting module configured to make conversion between a working voltage and a working frequency of the target circuit according to the lookup table module; and a combined adjusting module configured to combinedly adjust the working frequency and the working voltage of the target circuit. With a high degree of automation, the circuit control system herein is safe and reliable for adjusting the working voltage and the working frequency of the target circuit, thereby achieving the effects of adjustment and optimization.

Abstract: A monitoring circuit for monitoring the performance of a phase locked loop having a divider therein, the divider comprising at least a first counter, the monitoring circuit comprising at least one memory element for capturing a value of the first counter after a predetermined time from a system event in the operation of the phase locked loop, a variability calculator for comparing a value of the counter with a preceding value of the counter to calculate a variation, and a circuit responsive to the estimate of variation for outputting a status signal.

Abstract: In one embodiment, the present invention is a method and apparatus for detecting malware infection. One embodiment of a method for detecting a malware infection at a local host in a network, includes monitoring communications between the local host and one or more entities external to the network, generating a dialog warning if the communications include a transaction indicative of a malware infection, declaring a malware infection if, within a predefined period of time, the dialog warnings includes at least one dialog warning indicating a transaction initiated at the local host and at least one dialog warning indicating an additional transaction indicative of a malware infection, and outputting an infection profile for the local host.

Abstract: An on-chip timing slack monitor that measures timing slack at the end of a critical path includes a master-slave flip-flop having a tap on the Q output of the master and a logic module coupled to the flip-flop for producing a pulse whose width is a function of the slack. A pulse width shrinking delay line removes glitches on the flip-flop output and, in combination with a digital integrator and counter, also performs a time to digital conversion operation for determining a value for timing path slack. The determined value is used by a decision module for yield analysis. The monitor can discriminate a glitch from a slack pulse at the flip-flop output for any width of glitch up to one-half of a clock cycle.

Abstract: A method and system for using Equivalent Time Sampling to improve the effective sampling rate of sensor data, and using the improved-resolution data for diagnosis and control. Data samples from existing sensors are provided, where the sampling rate of the existing sensors is not sufficient to accurately characterize the parameters being measured. High-resolution data sets are reconstructed using Equivalent Time Sampling. High-resolution input data sets are used in a system model to simulate the performance of the system being measured. Results from the system model, and high-resolution output data sets from Equivalent Time Sampling, are provided to an estimator, which provides accurate estimation of measured quantities and estimation of quantities not measured. Output from the estimator is used for fault diagnosis and control of the system being measured.

Abstract: A frequency measurement device includes: a counter section that counts a supplied pulse stream signal to be measured at a predetermined time interval and outputs a stream of count values corresponding to the frequency of the signal to be measured; and a low-pass filter section that performs a filtering process on the stream of count values, the low-pass filter section including moving average filters in multiple stages, and an output of at least one moving average filter among the moving average filters in multiple stages is downsampled.

Abstract: An absolute high resolution linear segment or revolution counter as a one-chip-solution with self sustained, economical intermediate solutions, preferably as absolute magnetic multi turn, having a Wiegand element for counting the revolutions or segments, respectively and for the energy supply of the counter and memory as well as processing electronics, whereby the additional sensor for the fine resolution and a ?-controller are part of the overall IC is disclosed.

Abstract: An absolute high resolution linear segment or revolution counter as a one-chip-solution with self sustained, economical intermediate solutions, preferably as absolute magnetic multi turn, having a Wiegand element for counting the revolutions or segments, respectively and for the energy supply of the counter and memory as well as processing electronics, whereby the additional sensor for the fine resolution and a ?-controller are part of the overall IC is disclosed.

Abstract: There is presented a detailed electronic method for simulation of a firefly, other insects, or organisms producing bioluminescence and with light radiation functions similar to a real firefly, other insects, or organisms producing bioluminescence. An illuminated artificial firefly, other insects, or organisms producing bioluminescence can be placed on trees and shrubs in landscape, or at home to produce radiation, at night time, and blinking a gradually decaying light. More particularly it relates to a decorative type of device in the form of a firefly, other insects, or organisms producing bioluminescence and with light radiation functions similar to a real firefly, other insects, or organisms producing bioluminescence. The light is simulated by an electronics program that is a part of compact device with the form of a real firefly, other insects, or organisms producing bioluminescence.

Abstract: An AC measurement circuit includes a rectifier for receiving an AC signal; a peak detection circuit; and a voltage divider, interconnected with an output of the rectifier, and the input of the peak detection circuit to provide the peak detection circuit with a voltage value equal to a fraction of the AC signal. An analog to digital converter, has its analog input interconnected with an output of the peak detection circuit, for providing a digital output corresponding to its analog input. A summing circuit sums n samples of the digital output. The voltage divider is configured so that the summing circuit calculates an average measurement of the AC signal by summing n samples and without floating point division.

Abstract: A tracing apparatus for tracing operational information that is output from a plurality of processing units in relation to data processing operations, the tracing apparatus comprising for each of the processing units: a counting unit configured to obtain and output a counter value for the corresponding processing unit, the counter value obtained by counting clock signals that are input to the processing unit at an operating frequency thereof; a counter value conversion unit configured to obtain and output a converted counter value for the corresponding processing unit, the converted counter value obtained by converting the counter value based on the assumption that the processing unit has a given reference operating frequency; and an adding unit configured to acquire an operational information set from the corresponding processing unit, and to add the converted counter value to the operational information set.

Abstract: An X-ray detection signal processing apparatus of the present invention is such that after a signal from a preamplifier has been converted into a digital signal at a high speed by means of a high speed analog-to-digital converter (1), a process for removing influences brought about by a component that has been decayed by a differential time constant in the preamplifier is performed on a digital basis in a digital signal processing block (2). An event detecting unit (3) within the digital signal processing block (2), smoothen the signal from the high speed analog-to-digital converter (1) for a predetermined shaping time with the use of a filter function for high speed shaping, detects as an event information the timing at which the smoothened signal exceeds a predetermined threshold and attains the maximum value, and add such event information to the signal from the high speed analog-to-digital converter (1).

Abstract: A frequency counter obtains a cycle number of a clock of a target signal by a reference signal and a clock mask synchronous with the target signal, calculates a frequency of the target signal based on the cycle number, corrects the frequency according to a plurality of phase shift signals generated based on the reference signal, and minimizes an error of the calculated frequency by increasing the quantity of the phase shift signals, so as to enhance the accuracy of the calculated frequency of the target signal, speed up measurement, and reduce required circuit areas.

Abstract: Aspects of the disclosure provide a network device. The network device includes a first port coupled to a first device to communicate with the first device, and a clock wander compensation module. The first port recovers a first clock based on first signals received from the first device. The clock wander compensation module includes a global counter configured to count system clock cycles based on a system clock of the network device, and a first port counter configured to count first clock cycles based on the recovered first clock. Further, the first port transmits a first pause frame to the first device based on the global counter and the first port counter.

Abstract: The semiconductor integrated circuit includes a first oscillator, a second oscillator (PLL), a third oscillator (ring oscillator), a selector that switches, in turn, based on a clock of the third oscillator, and outputs a clock of the first oscillator or a clock of the second oscillator, and a determination circuit that counts up or counts down the clock output from the selector, based on the clock of the third oscillator, determines the correspondence of the clock output from the selector and the clock of the third oscillator, based on a result of the counting up or the counting down, and determines whether either of the clock output from the selector or the clock of the third oscillator occur an abnormal oscillation.

Abstract: Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, in conjunction with the one or more variable-delay time-base generators, provides the effect of over-clocking without the need to over-clock. Related methods provide such effective over-clocking. In embodiments of parametric analysis systems, test point sampling elements and analysis circuitry are clocked as a function of the output of the one or more variable-delay time-base generators to provide various parametric analysis functionality. Related methods address this functionality.

Abstract: A technique capable of determining a frequency of a data signal having a mixture of short and long pulse widths is provided. In a frequency determining circuit for determining a frequency from different data signals having a plurality of frequencies, the frequency determining circuit includes a circuit which acquires the different data signals having the plurality of frequencies and determines the frequency based on the number of counts of the signal having the pulse width shorter than the predetermined pulse width. For example, the signal having the pulse width shorter than the predetermined pulse width is detected, and the number of pulses of the detected signal is counted. By previously making correspondence of the frequency with the number of counts of the pulse, the frequency can be determined based on the number of counts.

Abstract: A system and method for synchronizing otherwise independent oscillators private to I2C Bus slave devices. An I2C Bus master device can issue two new general call commands, CALIBRATE and ZERO COUNTERS. The I2C Bus slave devices respond to the CALIBRATE command by counting the number of cycles its local, private oscillator makes through during the communication transfer period of the CALIBRATE command on the I2C Bus. All such I2C Bus slave devices measure the same communication transfer period on the I2C Bus, so the differences in the digital measurements obtained by each of them are proportional to their respective oscillator frequencies. The digital measurements are privately used by each I2C Bus slave device to calculate appropriate oscillator prescale factors, and to automatically load the values that will harmonize the final product frequencies of all of the local oscillators on all of the I2C Bus slave devices in the system.

Abstract: A self correcting device includes a first flip-flop to receive data and coupled to a clock input; one or more delayed flip-flops used to detect delay variations; a multiplexer coupled to the output of the first flip-flop and the delayed flip-flops, a metastability detector and error check controller to control the multiplexer to select one flip-flop output; and an adaptive voltage swing link coupled to the multiplexer output to generate a voltage swing on the link based on a selected clock skew.

Abstract: A method and apparatus is provided for setting time positions of measurement gates on a signal under test. Signal transition data is calculated by a processor for multiple signal transitions. Measurement gate start and end positions are set relative to the multiple signal transitions based on the received signal transition data.

Abstract: A method determines a transient response of a sample. The method includes providing a measured magnitude of the Fourier transform of a complex electric field temporal profile of a pulse sequence comprising a first pulse indicative of the transient response of the sample and a second pulse. The method further includes providing an estimated phase term of the Fourier transform of the complex electric field temporal profile of the pulse sequence. The method further includes multiplying the measured magnitude and the estimated phase term to generate an estimated Fourier transform of the complex electric field temporal profile of the pulse sequence. The method further includes calculating an inverse Fourier transform of the estimated Fourier transform, wherein the inverse Fourier transform is a function of time. The method further includes calculating an estimated complex electric field temporal profile of the pulse sequence by applying at least one constraint to the inverse Fourier transform.

Abstract: A method utilizes an optical image processing system. The method includes providing a measured magnitude of the Fourier transform of a complex transmission function of an object or optical image. The method further includes providing an estimated phase term of the Fourier transform of the complex transmission function. The method further includes multiplying the measured magnitude and the estimated phase term to generate an estimated Fourier transform of the complex transmission function. The method further includes calculating an inverse Fourier transform of the estimated Fourier transform, wherein the inverse Fourier transform is a spatial function. The method further includes calculating an estimated complex transmission function by applying at least one constraint to the inverse Fourier transform.

Abstract: A wireless communications apparatus that it is useable as a spectrum analyzer and as a wireless receiver. The wireless communications apparatus has a radio circuit that is configured to receive EM radiation. Signal processing logic receives signals from the radio circuit based on the EM radiation. The signal processing logic has a receiver operational mode that processes the signals in accordance with a communication protocol and outputs data encoded in the signals to a host processor. The signal processing logic has a spectrum analyzer operational mode that generates frequency domain data and passes the frequency domain data to the host processor. The frequency domain data describe strength versus frequency of the EM radiation. The host processes the data in accordance with the configuration currently in use. Therefore, the wireless communications apparatus operates as a receiver in one operational mode and as a real-time spectrum analyzer in another operational mode.

Abstract: A system for testing a fan interface on a motherboard is provided. A fan simulator receives a PWM signal from a fan interface of the motherboard, converts the PWM signal to a TACH signal and outputs the TACH signal to a computer via a fan connector. A difference between the actual rotation speed from the TACH signal and a preset desired rotation speed of the fan simulator is determined and analyzed by comparing the difference with a preset allowable error margin.

Abstract: The present invention relates to a method and apparatus for measuring a frequency or a phase of a measuring signal, wherein the frequency (fg) or the phase (?g) are estimated by approximating the relationship between a collecting clock (c) and a gating clock (g) based on a non-linear step-shaped function. Thereby, the estimation error can be improved with almost negligible complexity increase in signal processing.

Abstract: Various techniques are described for high resolution time measurement using a programmable device, such as an FPGA. The timing may be triggered by any event, depending on the applications of use. Once triggering has occurred, a START pulse begins propagating through the FPGA. The pulse is able to propagate through the FPGA in a staggered manner traversing multiple FPGA columns to maximize the amount of time delay that may be achieved while minimizing the overall array size, and thus minimizing the resource utilization, of the FPGA. The FPGA timing delay is calibrated by measuring for the linear and non-linear differences in delay time of each unit circuit forming the staggered delay line path for the timing circuit. The FPGA achieves nanosecond and sub-nanosecond time resolutions and is used in applications such as various time of flight systems.

Abstract: A detecting apparatus detects the degree of correlation between first events and second events repeatedly occurring in an observed apparatus includes an acquiring unit that acquires second event count values each indicating the number of second events occurring during each first period between each first event and the first event next thereto. A measuring unit measures an observed number of each second event count value derived from the number of times the second event count value is observed. A calculating unit calculates the degree of correlation between the first events and the second events based on the observed number of each second event count value.

Abstract: A method of checking the operating characteristics of an electronic unit (1) fitted on a wheel (2) of a vehicle (3) and adapted to transmit, to a central processing unit (7), data frames representative of operating parameters of the wheel according to a procedure for transmitting streams (A) of frames (a) consisting in ordering n successive transmissions of each data frame. This checking method consists in analyzing, on the transmission of each stream of data frames, the number m of data frames actually acquired by the central processing unit (7), so as to deduce from the successive analyses a reception ratio Tr representative of the ratios ?m/?n, and in ordering the transmission, by the central processing unit (7), of a preventive indication when the reception ratio Tr becomes less than a predetermined reception threshold.

Abstract: A system and method for synchronizing otherwise independent oscillators private to I2C Bus slave devices. An I2C Bus master device is capable of issuing two new general call commands, MEASURE PULSE and RESET PRESCALE. The I2C Bus slave devices respond to the MEASURE PULSE command by returning a digital count related to the number of ticks its local, private oscillator cycles through during a signal pulse on the I2C Bus. All such I2C Bus slave devices measure the same signal pulse on the I2C Bus, so the differences in the digital measurements returned during the MEASURE PULSE command are proportional to their respective oscillator frequencies. The various digital measurements returned are used to calculate appropriate oscillator prescale factors that will harmonize the final product frequencies of all of the local oscillators on all of the I2C Bus slave devices in the system.

Abstract: A frequency measurement device includes: a counter section that counts a supplied pulse stream signal to be measured at a predetermined time interval and outputs a stream of count values corresponding to the frequency of the signal to be measured; and a low-pass filter section that performs a filtering process on the stream of count values, the low-pass filter section including moving average filters in multiple stages, and an output of at least one moving average filter among the moving average filters in multiple stages is downsampled.

Abstract: A test circuit includes a first reset pulse generator configured to generate a first reset pulse when a test mode is performed or when power is up, a test mode maintenance signal generator configured to provide a test mode maintenance signal activated in response to a predetermined consecutive test information data, the activation of the test mode maintenance signal being controlled by the first reset pulse, a second reset pulse generator configured to generate a second reset pulse when the test information data is received as a predetermined test mode reset data or when power is up, and a test mode selection signal generator configured to receive the test information data provided from the test mode maintenance signal generator and the test mode maintenance signal and to generate a specific test mode selection signal, the activation of the specific test mode selection signal being controlled by the second reset pulse.

Abstract: An analog signal measurement system and a gamma ray detector with targeted automated gamma spectroscopy for gamma radiation surveillance system are disclosed. The analog signal measurement system has dynamically programmable lower and upper level discriminators for measuring an analog signal thereagainst, and logic devices for receiving input from the discriminators to generate digital signals. The gamma ray detector comprises a gamma ray detector for converting a gamma ray photon into an analog pulse, and a single channel analyzer or the analog signal measurement system.

Abstract: A test circuit includes a first reset pulse generator configured to generate a first reset pulse when a test mode is performed or when power is up, a test mode maintenance signal generator configured to provide a test mode maintenance signal activated in response to a predetermined consecutive test information data, the activation of the test mode maintenance signal being controlled by the first reset pulse, a second reset pulse generator configured to generate a second reset pulse when the test information data is received as a predetermined test mode reset data or when power is up, and a test mode selection signal generator configured to receive the test information data provided from the test mode maintenance signal generator and the test mode maintenance signal and to generate a specific test mode selection signal, the activation of the specific test mode selection signal being controlled by the second reset pulse.

Abstract: A method and apparatus for detecting forward/reverse speeds of a continuously variable transmission for vehicles determines whether a vehicle is in a forward speed state or in a reverse speed state by using one speed detector having two sensors. The method for detecting forward/reverse speeds of the continuously variable transmission for vehicles includes detecting first and second rotational speeds of an output shaft modulating the first and second rotational speeds of the output shaft into a pulse width modulation signal, comparing the pulse width of the pulse width modulation signal with predetermined values, and determining whether a vehicle is in a forward speed state or in a reverse speed state.

Abstract: An Edge-Aligned Ratio Counter (EARC) that includes at least one processor coupled to at least one counter circuit is provided for determining a ratio between two clock signals by receiving a first and a second value in response to a first clock signal and generating a control signal under control of the loaded value by counting the pulses of the first clock signal and a second clock signal and captures the count of each clock signal in response to the control signal and determining a ratio between a frequency of the first clock signal and a frequency of the second clock signal using the differences of the captured counts taken at two different occurrences of the control signal.

Abstract: Systems and methods are provided for acquiring seismic data using a wireless network and a number of individual data acquisition modules that are configured to collect seismic data and forward data to a central recording and control system. In one implementation, a number of remote modules (301) are arranged in lines. Base station modules (302) receive information from the lines and relay the information to a central control and recording system (303). Radio links operating on multiple frequencies (F1-F12) are used by the modules (301). For improved data transfer rate, radio links from a remote module (301) leap past the nearest remote module to the next module closer to the base station.

Abstract: A method for spectral analysis of a signal (s1(t)) in several frequency bands with different frequency resolution adapts the two spectra of the signal (s1(t)) from adjacent frequency bands relative to one another in the transitional range of the two frequency bands. The associated device contains a unit for discrete convolution (3), which implements a smoothing of the discrete power spectra (|S1(k)|2) of the discrete signal (s1(k)) from adjacent frequency bands in the transitional range of the two frequency bands.

Abstract: A D/U ratio is measured for desired and undesired signals in a wireless video transmission system at a shared channel frequency based on a received signal at a geographic location in proximity to regions within respective service areas for the desired and undesired signals. A video tuner demodulates the received signal to generate a baseband video signal. A leveling circuit normalizes the baseband signal. A video processor identifies horizontal sync pulses within the baseband signal, generates a sampled signal comprising the horizontal sync pulses, and removes components of the desired signal from the sampled signal to generate an undesired signal component. A D/U analyzer determines a Fourier transform having a plurality of bins in response to the undesired signal component, identifies at least one of the bins having a spectral peak corresponding to an undesired signal, and calculates the D/U ratio in response to a magnitude of the identified peak.

Abstract: A battery device includes a battery cell including a cell terminal, a case that houses the battery cell, a battery terminal provided to the case and electrically connected to the cell terminal, and a control section that is housed in the case and allows and inhibits charge and discharge of the battery cell, wherein the control section includes a detection section that detects an output voltage value of the cell terminal at an interval, and assuming that the latest output voltage value detected by the detection section is V1, and the output voltage value detected by the detection section immediately before the latest output voltage value V1 is V0, the control section allows charge and discharge of the battery cell if |?V| (?V=V1?V0) is smaller than a reference value, and to inhibit charge and discharge of the battery cell if |?V| is equal to and greater than the reference value.

Abstract: A tunable delay line is calibrated to maintain the delay of the delay line at a desired value or within a desired range of values. In some aspects a signal is passed through a delay line multiple times so that the cumulative delay of the signal through the delay line (e.g., as indicated by a count) may be calculated over a period of time. The count is compared with an expected count and, based on this comparison, the delay of the delay line is adjusted as necessary. In some aspects the signal may comprise a digital signal. In some aspects a delay through a delay line may be calculated based on analysis of amplitude changes in a signal caused by a phase shift imparted on the signal by the delay line. In some aspects a delay line is incorporated into a transmitted reference system to generate and/or process transmitted reference signals.

Abstract: In a semiconductor integrated circuit, a counter counts the number of high-speed clock signals that have been generated in a predetermined number of clock cycles of a low-speed clock signal. In synchronization with the low-speed clock signal, the semiconductor integrated circuit compares the counter value and a predetermined value, and judges whether the frequency of the high-speed clock signal has reaches a predetermined frequency. Since variations in the frequency become smaller as the oscillation of a high-speed oscillator stabilizes, the semiconductor integrated circuit detects that the oscillation is stable when the semiconductor integrated circuit has judged affirmatively a plurality of times.

Abstract: A motor control system and method are provided for detecting current ripple in a commutated DC motor and further determining position and speed of the motor based on the detected ripple current. Ripples in the motor current are detected and a ripple frequency is calculated based on the time between successive ripples. A ripple count between successive frequencies is determined and the ripple count is compared to a threshold value, and an estimated ripple frequency is determined from a motor model when the ripple count exceeds the threshold value. A corrected ripple count is calculated from a ratio of the calculated ripple frequency and the estimated ripple frequency, and motor position and motor speed are determined based on the corrected ripple count.

Abstract: Disclosed herein is a method and apparatus used to the measure duty cycle of a clocking waveform utilizing minimal hardware and achieving high accuracy. This invention utilizes digital sampling of the signal to be measured at a rate that can be significantly lower then the clocking frequency of the signal to be measured. It accomplishes broad-band, multi-frequency use by using a time-varying frequency for the sampling clock to make sure that the sampling clock is asynchronous with the frequency of the clocking signal to be measured. The average ratio of the sampled ones (or zeros) as compared to the total number of samples is then computed to derive the measurement of duty cycle.

Abstract: A method processes an optical image. The method includes providing a measured magnitude of the Fourier transform of a two-dimensional complex transmission function. The method further includes providing an estimated phase term of the Fourier transform of the two-dimensional complex transmission function. The method further includes multiplying the measured magnitude and the estimated phase term to generate an estimated Fourier transform of the two-dimensional complex transmission function. The method further includes calculating an inverse Fourier transform of the estimated Fourier transform, wherein the inverse Fourier transform is a spatial function. The method further includes calculating an estimated two-dimensional complex transmission function by applying at least one constraint to the inverse Fourier transform.