Abstract: A computing machine capable of performing multiple operations using a universal computing unit is provided. The universal computing unit maps an input signal to an output signal. The mapping is initiated using an instruction that includes the input signal, a weight matrix, and an activation function. Using the instruction, the universal computing unit may perform multiple operations using the same hardware configuration. The computation that is performed by the universal computing unit is determined by the weight matrix and activation function used. Accordingly, the universal computing unit does not require any programming to perform a type of computing operation because the type of operation is determined by the parameters of the instruction, specifically, the weight matrix and the activation function.

Abstract: A chaotic signal generator includes a set of elements connected together for generating chaotic signals. The connection scheme may correspond to the circuit generally referred to as Chua's circuit, particularly when implemented as a cellular neural network. Interposed in the connection scheme is at least one switch, such as a MOS transistor. Opening and closing of the switch causes variation in the chaotic dynamics of the generated signals. A command signal applied to the switch may correspond to a modulating signal for transmission on a channel, such as a high noise channel. The modulating signal may be a binary signal, and the command signal may be a switching signal having a frequency that increases or decreases depending on the logic level of the binary signal.

Abstract: In a first aspect, a pipelined hardware implementation of a neural network circuit includes an input stage, two or more processing stages and an output stage. Each processing stage includes one or more processing units. Each processing unit includes storage for weighted values, a plurality of multipliers for multiplying input values by weighted values, an adder for adding products outputted from product multipliers, a function circuit for applying a non-linear function to the sum outputted by the adder, and a register for storing the output of the function circuit.

Abstract: A method and apparatus for color matching are provided, in which paint recipe neural networks are utilized. The color of a standard is expressed as color values. The neural network includes an input layer having nodes for receiving input data related to paint bases. Weighted connections connect to the nodes of the input layer and have coefficients for weighting the input data. An output layer having nodes are either directly or indirectly connected to the weighted connections and generates output data related to color values. The data to the input layer and the data from the output layer are interrelated through the neural network's nonlinear relationship. The paint color matching neural network can be used for, but not limited to, color formula correction, matching from scratch, effect pigment identification, selection of targets for color tools, searching existing formulas for the closest match, identification of formula mistakes, development of color tolerances and enhancing conversion routines.

Abstract: A circuit implementing a non-integer order dynamic system includes a neural network that receives at least one input signal and generates therefrom at least one output signal. The input and output signals are related to each by a non-integer order integro-differential relationship through the coefficients of the neural network. A plurality of such circuits, implementing respective non-integer order controllers can be interconnected in an arrangement wherein any of the integral or differential blocks included in one of these circuits generates a signal which is fed to any of the integral or differential blocks of another circuit in the system.

Abstract: A neural network includes a programmable template matching network and a winner take all network. The programmable template matching network can be programmed with different templates. The WTA network has an output which can be reconfigured and the scale of the WTA network can expanded.

Abstract: An associative artificial neuron and method of forming output signals of an associative artificial neuron includes receiving a number of auxiliary input signals; forming from the auxiliary input signals a sum weighted by coefficients and applying a non-linear function to the weighted sum to generate a non-linear signal. The neuron and method further include receiving a main input signal and forming, based on the main signal and the non-linear signal, the function S OR V, which is used to generate a main output signal, and at lest one of three logical functions S AND V, NOT S AND V, and S AND NOT V. The at least one logical function is used to generate an additional output signal for the associative artificial neuron.

Abstract: A neural network integrated circuit comprises many neuron circuits each with a distance resister that is compared in a competition for the closest-hit with all the other neurons. Such closest-hit comparison is conducted bit-by-bit over the many bit positions of a distance measure in binary format each time after the neurons fire. A single-wire AND-bus interconnects every neuron in a whole system. Each neuron drives the single-wire AND-bus with an open-collector buffer. All neurons press the single-wire AND-bus with their respective distance measures in successive cycles, starting with the most significant bit. For example, a fourteen-bit binary distance word requires fourteen comparison cycles. Any neuron that sees a “0” on the single-wire AND-bus when its own corresponding bit in its distance measure is a “1”, automatically drops from the competition. By the time the least significant bit cycle is run, a single closest distance will have been determined.

Abstract: The present invention relates to the field of computer science and can be used for neural network emulation and digital signal processing. Increasing of the neural processor performance is achieved using the ability to change word lengths of results in program mode. The neural processor includes six registers, a shift register, a AND gate, two FIFOs, a switch, a multiplexer, two saturation units, a calculation unit and a adder circuit to execute operations over vectors of programmable word length data. Increasing of the saturation unit performance is achieved using the ability to process vector of input operands with programmable word length at a time. Increasing of the adder circuit performance is achieved using ability to sum two vectors of input operands of programmable word lengths.

Abstract: A technique for machine learning, such as supervised artificial neural network learning includes receiving data and checking the dimensionality of the read data and reducing the dimensionality to enhance machine learning performance using Principal Component Analysis methodology. The technique further includes specifying the neural network architecture and initializing weights to establish a connection between read data including the reduced dimensionality and the predicted values. The technique also includes performing supervised machine learning using the specified neural network architecture, initialized weights, and the read data including the reduced dimensionality to predict values. Predicted values are then compared to a normalized system error threshold value and the initialized weights are revised based on the outcome of the comparison to generate a learnt neural network having a reduced error in weight space.

Abstract: A number of consecutive samples in unit distance code (here Gray code) are effectively stacked and supplied to respective sum and threshold devices 20 corresponding to each bit position, to determine the bulk property or “generic result” of the consecutive samples. This filtered output is converted back to binary and analogue if required. The digital filter may be used in any of the above applications to “clean” data.

Abstract: A neuron circuit including means for synaptic modification is described. The circuit emulates the electrical behaviors of the neuron membrane, dendrite, and synapse, using principles based on the actual biology. In one embodiment, the circuit is implemented as an analog very large scale integrated (VLSI) circuit which utilizes CMOS integrated circuit technology. The analog VLSI circuit includes a synapse circuit having a circuit portion which models a mechanism for the modification of the synaptic conductance.

Abstract: Detection is implemented by a multiplier, a lookup table or other apparatus with two inputs, one of which typically receives an input signal from a sensor, and the other a reference or weighting factor W stored or generated locally. The detected value is added to the contents of a memory location A after the previous contents of memory locations A have been modified by a loss or gain factor Q. Memory location A is one of several such memory locations in a shared memory simultaneously accessible by an external user. In a neural engine the memory locations represent neurons. For each cycle of operation of the neural engine a new value of W, Q and A are provided.

Abstract: The improved neuron is connected to input buses which transport input data and control signals. It basically consists of a computation block, a register block, an evaluation block and a daisy chain block. All these blocks, except the computation block substantially have a symmetric construction. Registers are used to store data: the local norm and context, the distance, the AIF value and the category. The improved neuron further needs some R/W memory capacity which may be placed either in the neuron or outside. The evaluation circuit is connected to an output bus to generate global signals thereon. The daisy chain block allows to chain the improved neuron with others to form an artificial neural network (ANN). The improved neuron may work either as a single neuron (single mode) or as two independent neurons (dual mode). In the latter case, the computation block, which is common to the two dual neurons, must operate sequentially to service one neuron after the other.

Abstract: A neuron circuit that can be served as a building block for a neural network implemented in an integrated circuit is disclosed. The neuron circuit includes a synapse circuit block and a neuron body circuit block. The synapse circuit block has three transistors, and the body of one of the three transistors is controlled by a weighted input. The neuron body circuit block includes a current mirror circuit, a summing circuit, and an invertor circuit. The neuron body circuit is coupled to the synapse circuit block to generate an output pulse.

Abstract: The invention pertains to a method and corrector (IC6) for correcting an error in a parallel analog-to-digital conversion. Such a correctable error is caused by uncertainties in the reading of the states of parallel comparing elements (IC1, IC2, IC3, IC4) in the converter, said uncertainties being brought about by nonideality, such as non-simultaneous state latching. This error is corrected using a nonlinear cellular neural network preferably such that the real level of the phenomenon compared by means of comparing elements (IC1, IC2, IC3, IC4) is estimated by estimating the states corresponding to correct reading of the comparing elements (IC1, IC2, IC3, IC4) read temporally or otherwise erroneously.

Abstract: An artificial intelligence system is provided which makes use of a dual subroutine to adapt weights. Elastic Fuzzy Logic (“ELF”) System is provided in which classical neural network learning techniques are combined with fuzzy logic techniques in order to accomplish artificial intelligence tasks such as pattern recognition, expert cloning and trajectory control. The system may be implemented in a computer provided with multiplier means and storage means for storing a vector of weights to be used as multiplier factors in an apparatus for fuzzy control.

Abstract: Image processing for multimedia workstations is a computationally intensive task requiring special purpose hardware to meet the high speed requirements associated with the task. One type of specialized hardware that meets the computation high speed requirements is the mesh connected computer. Such a computer becomes a massively parallel machine when an array of computers interconnected by a network are replicated in a machine. The nearest neighbor mesh computer consists of an N×N square array of Processor Elements(PEs) where each PE is connected to the North, South, East and West PEs only. The diagonal folded mesh array processor, which is called Oracle, allows the matrix transformation operation to be accomplished in one cycle by simple interchange of the data elements in the dual symmetric processor elements.

Abstract: A method, system and computer-readable medium for controlling a control subsystem of a vehicle. The control subsystem includes at least one propulsion, aerodynamic, or other control effector. The system also includes sensors for sensing vehicle position and motions and operating conditions, a control input device for generating control signals, and a generator for generating desired vehicle forces/moments from the sensed vehicle position and motions and operating conditions, and the generated control input signals based on predefined vehicle compensation and control laws. Also included is a neural network controller for generating control subsystem commands for the at least one propulsion, aerodynamic, or other control effector based on the generated desired forces/moments, wherein said neural network controller was trained based on pregenerated vehicle control distribution data. The neural network controller is also trained to compensate for one or more failed control effectors.

Abstract: Disclosed is a digital neural node according to the invention. The digital neural node, electrically coupled to n information processing units (n is an integer larger than 1), includes n data access devices. Each data access device has an input port, a first output port, a second output port, a third output port, . . . and an (n−1)th output port, and is electrically coupled to a uniquely corresponding information processing unit through the input port and to the other information processing units through the first output port, the second output port, the third output port, . . . and the (n−1)th output port, respectively. In accordance with the inventive digital neural node structure, each information processing unit can write digital data in a uniquely corresponding data access device, and the other information processing units can read the digital data at the same time.

Abstract: Assignment of attributes to elements subject to constraints is achieved using a system that has a systematic engine and a nonsystematic engine. The systematic engine includes a schedule developer for producing partial proposed assignments, a pruning processor for determining violations of discrepancy limits by a partial proposed assignment, and a bound selector for relaxing discrepancy limits as needed. The non-systematic engine includes a schedule packer for modifying assignments proposed by the systematic engine and an evaluator for comparing the modified assignments with the constraints.

Abstract: A neuroprocessor architecture employs a combination of bit-serial and serial-parallel techniques for implementing the neurons of the neuroprocessor. The neuroprocessor architecture includes a neural module containing a pool of neurons, a global controller, a sigmoid activation ROM look-up-table, a plurality of neuron state registers, and a synaptic weight RAM. The neuroprocessor reduces the number of neurons required to perform the task by time multiplexing groups of neurons from a fixed pool of neurons to achieve the successive hidden layers of a recurrent network topology.

Abstract: A resource scheduler for scheduling railway train resources over a track system with a high degree of optimization. The scheduler is implemented in an expert system that employs simulated annealing techniques to approximate the optimum solution.

Abstract: An artificial neuron, which may be implemented either in hardware or software, has only one significant processing element in the form of a multiplier. Inputs are first fed through gating functions to produce gated inputs. These gated inputs are then multiplied together to produce a product which is multiplied by a weight to produce the neuron output.

Abstract: The threshold value logic has a non-inverting circuit path (S) that and an inverting circuit path (S') are connected to at least one comparative weighting subcircuit (BC, BS). The non-inverting circuit path and the inverting circuit path preferably are of identical construction and each contain at least one neuron transistor (NT1, NT1'). The corresponding neuron transistor gates in the non-inverting circuit path and in the inverting circuit path are driven inversely with respect to one another.

Abstract: This invention provides learning methods in binary systems by modifying the connected states of the circuit among each basic binary gate in binary combined logical and sequential circuits composed with basic binary gates such as AND, OR, NOT, NAND, NOR and EXOR gates. As the pseudo-neuron theory and the pseudo-potential energy theory are skillfully introduced, it is possible to attain specified learning effects during a very short learning period. Further, as implementation of the learning methods into the conventional computer and other digital equipment is simple, it is expected to be used widely in wide application, for example, such as in image processing, voice processing or natural word processing.

Abstract: The invention relates to a device for designing a neural network, in which to determine the number of neurons (21 . . . 24) in the intermediate layer, the domain of the input signal (X1, X2) in question is subdivided into a predefinable number of subdomains, and in the case of a multiplicity n of input signals (X1, X2), the n-dimensional value space of the n input signals is subdivided in conformance with the subdomains in question into n-dimensional partial spaces, and the supporting values (xi, yi) of the training data are assigned to the subdomains or partial spaces, and the subdomains or partial spaces having the most supporting values are selected, and in which case, for each selected subdomain or partial space, provision is made for a neuron in the intermediate layer preceding the output layer. The device according to the invention can be advantageously used for designing neural networks where the training data are unevenly distributed.

Abstract: A digital artificial neural network (ANN) reduces memory requirements by storing sample transfer function representing output values for multiple nodes. Each nodes receives an input value representing the information to be processed by the network. Additionally, the node determines threshold values indicative of boundaries for application of the sample transfer function for the node. From the input value received, the node generates an intermediate value. Based on the threshold values and the intermediate value, the node determines an output value in accordance with the sample transfer function.

Abstract: An electronic device for performing convolution operations comprises shift registers for receiving binary input values representative of an original matrix, synapses for storing weights correlated with a mask matrix, and neurons for outputting a binary result dependent on the sum of the binary values weighted by the synapses. Each synapse has a conductance correlated with the weight stored and dependent upon the binary input value. Each neuron generates the binary result in dependence on the total conductance of the corresponding synapses.

Abstract: A method and apparatus for an electronic artificial neural network, which serves as an associative memory that has a complete set of N-dimensional Hadamard vectors as stored states, suitable for large N that are powers of 2. The neural net has nonlinear synapses, each of which processes signals from two neurons. These synapses can be implemented by simple passive circuits comprised of eight resistors and four diodes. The connections in the neural net are specified through a subset of a group that is defined over the integers from 1 to N. The subset is chosen such that the connections can be implemented in VLSI or wafer scale integration. An extension of the Hadamard memory causes the memory to provide new Hadamard vectors when these are needed for the purpose of Hebb learning.

Abstract: A nonrecurrent version of the Neural Network Binary Code Recognizer is disclosed. This Nonrecurrent Binary Code Recognizer, which decodes an input vector of n analog components into a decoded binary word of n bits, comprises an analog-to-digital converter, an inverter circuit, a digital summing circuit and a comparator circuit.

Abstract: A neural network apparatus includes a neural network including at least two neuron layers each having a plurality of neurons and at least one synapse layer having a plurality of synapses each arranged between the neuron layers, each synapse storing a weight value between the neurons and multiplying the weight value with an output value from each of the neurons in the previous-stage neuron layer to output a product to the next-stage neuron layer, a section for causing an error signal between an output from the neural network and a desired output to back-propagate from an output-side neuron layer to an input-side neuron layer of the neural network, a learning control section for updating the weight value in the synapse on the basis of the error signal and the output value from the previous-stage neuron, and a selecting section for selecting a synapse whose weight value is to be updated by the learning control section when the learning control section is to update the weight values of a predetermined number of s

Abstract: A dynamical system analyser (10) incorporates a computer (22) to perform a singular value decomposition of a time series of signals from a nonlinear (possibly chaotic) dynamical system (14). Relatively low-noise singular vectors from the decomposition are loaded into a finite impulse response filter (34). The time series is formed into Takens' vectors each of which is projected onto each of the singular vectors by the filter (34). Each Takens' vector thereby provides the co-ordinates of a respective point on a trajectory of the system (14) in a phase space. A heuristic processor (44) is used to transform delayed co-ordinates by QR decomposition and least squares fitting so that they are fitted to non-delayed co-ordinates. The heuristic processor (44) generates a mathematical model to implement this transformation, which predicts future system states on the basis of respective current states. A trial system is employed to generate like co-ordinates for transformation in the heuristic processor (44).

Abstract: A digital neural network architecture including a forward cascade of layers of neurons, having one input channel and one output channel, for forward processing of data examples that include many data packets. Backward cascade of layers of neurons, having one input channel and one output channel, for backward propagation learning of errors of the processed data examples. Each packet being of a given size. The forward cascade is adapted to be fed, through the input channel, with a succession of data examples and to deliver a succession of partially and fully processed data examples each consisting of a plurality of packets. The fully processed data examples are delivered through the one output channel. Each one of the layers is adapted to receive as input in its input channel a first number of data packets per time unit and to deliver as output in its output channel a second number of data packets per time unit.

Abstract: A neuron MOSFET based module for use in the design and layout of binary logic circuits. In a first embodiment, the module is composed of four neuron MOSFETs arranged symmetrically to form a unit which may be combined with other such units to form more complex circuits. The MOSFETs are either n-channel or p-channel transistors. Each MOSFET has an associated floating gate and coupling region which can be selectively connected to the adjacent transistors in the module. Inputs to the module may be capacitively coupled to one or more of the coupling regions through an overlaying gate structure or by an appropriate set of doped substrate regions. Variations to the basic module structure include an embodiment formed from three neuron MOSFETs and the use of both n-channel and p-channel devices in the same module.

Abstract: A neural processor includes neural calculation apparatus (30, NQ, RQ) which normalize an input data X with respect to another input data Y. It performs a division of X by Y in order to determine a quotient Q. The calculation apparatus are programmed to calculate (30) by iteration, a series of contributions .DELTA.Q.sub.i which are used (NQ, RQ) to update a partial quotient QP which becomes the quotient Q at the end of calculation. The calculation can be performed on an arbitrary arithmetic base which determines the number of neurons utilized and also the accuracy of calculation. It is also possible to utilize a partial remainder RP. Several programming modes are presented.

Abstract: A heuristic processor incorporates a digital arithmetic unit arranged to compute the squared norm of each member of a training data set with respect to each member of a set of centers, and to transform the squared norms in accordance with a nonlinear function to produce training &phgr; vectors. A systolic array arranged for QR decomposition and least mean squares processing forms combinations of the elements of each &phgr; vector to provide a fit to corresponding training answers. The form of combination is then employed with like-transformed to provide estimates of unknown result. The processor is applicable to provide estimated results for problems which are nonlinear and for which explicit mathematical formalisms are unknown.