Multiplication Or Division Patents (Class 708/103)

Patent number: 10339998Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.Type: GrantFiled: March 27, 2018Date of Patent: July 2, 2019Assignee: Micron Technology, Inc.Inventors: Katsuhiro Kitagawa, Kazuhiro Kurihara, Kohei Nakamura, Akira Yamashita

Patent number: 10042606Abstract: The present embodiments relate to circuitry that efficiently performs floatingpoint arithmetic operations and fixedpoint arithmetic operations. Such circuitry may be implemented in specialized processing blocks. If desired, the specialized processing blocks may include configurable interconnect circuitry to support a variety of different use modes. For example, the specialized processing block may efficiently perform a fixedpoint or floatingpoint addition operation or a portion thereof, a fixedpoint or floatingpoint multiplication operation or a portion thereof, a fixedpoint or floatingpoint multiplyadd operation or a portion thereof, just to name a few. In some embodiments, two or more specialized processing blocks may be arranged in a cascade chain and perform together more complex operations such as a recursive mode dot product of two vectors of floatingpoint numbers or a Radix2 Butterfly circuit, just to name a few.Type: GrantFiled: March 7, 2017Date of Patent: August 7, 2018Assignee: ALTERA CORPORATIONInventor: Martin Langhammer

Patent number: 9360915Abstract: Systems, methods, and other embodiments associated with controlling a clocking rate of a processor clock are described. According to one embodiment, an apparatus includes a register, a selector, and a clock gate. The register stores a set of bits arranged in a clocking pattern. In response to receiving an edge of a first clock signal, the selector selects a bit of the set of bits in the register. With each edge of the first clock signal, the selector selects a next bit in the clocking pattern. The clock gate implements a conjunction of the selected bit and the edge. The clock gate then outputs the conjunction of the selected bit and the edge as a second clock signal.Type: GrantFiled: April 25, 2013Date of Patent: June 7, 2016Assignee: MARVELL INTERNATIONAL LTD.Inventor: Kim Schuttenberg

Patent number: 9189581Abstract: Methods and apparatuses are described for proving equivalence between two or more circuit designs that include one or more division circuits and/or one or more squareroot circuits. Some embodiments analyze the circuit designs to determine an input relationship between the inputs of two division (or squareroot) circuits. Next, the embodiments determine an output relationship between the outputs of two division (or squareroot) circuits based on the input relationship. The embodiments then prove equivalence between the circuit designs by using the input and output relationships.Type: GrantFiled: October 31, 2012Date of Patent: November 17, 2015Assignee: SYNOPSYS, INC.Inventors: Himanshu Jain, Carl P. Pixley

Patent number: 9065628Abstract: A clock generating circuit is operated in a closedloop state to generate an output clock signal that is frequencylocked with respect to an oscillatory input signal. Upon detecting a frequency transition in the input signal, the clock generating circuit is switched from the closedloop operating state to an openloop operating state to enable the output clock signal to oscillate at a freerunning frequency. A ratio between input signal frequency and the freerunning frequency of the output clock signal is determined and used to adjust a frequencylock range of the clock generating circuit. The clock generating circuit is then switched from the openloop operating state to the closedloop operating state to frequencylock the output clock signal with respect to input signal.Type: GrantFiled: October 17, 2014Date of Patent: June 23, 2015Assignee: Rambus Inc.Inventors: Yue Lu, Jared L. Zerbe

Patent number: 8762436Abstract: A method is provided for synthesizing signal frequencies using low resolution rational division. A reference frequency value and synthesized frequency value are accepted. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (n) and an integer value denominator (d) are determined, with n/d=I(N/D)=I+N/D=(I+1)?(D?N)/D), and where N/D<1. An accumulator creates a sum of (D?N) and a count from a previous cycle, and creates a difference between the sum and the denominator. The sum is compared with the denominator, and a first carry bit is generated. The complement of the first carry bit is added to a first binary sequence, and the first binary sequence is used to generate a kbit quotient. The kbit quotient is subtracted from (I+1) to generate a divisor.Type: GrantFiled: December 17, 2010Date of Patent: June 24, 2014Assignee: Applied Micro Circuits CorporationInventors: Viet Do, Simon Pang

Patent number: 8667038Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.Type: GrantFiled: August 4, 2008Date of Patent: March 4, 2014Assignee: NetLogic Microsystems, Inc.Inventor: Stefanos Sidiropoulos

Patent number: 8589258Abstract: An amount is divided into equal portions (n) in a manner which eliminates rounding errors or remainders and has repeatable results.Type: GrantFiled: September 14, 2006Date of Patent: November 19, 2013Assignee: Microsoft CorporationInventor: Howard Smith

Patent number: 8554815Abstract: A system and method are provided for synthesizing signal frequencies using a single reference clock and a primitive ratio of integers. The method accepts a plurality (k) of reference frequency values (fri), where 1?i?k, associated with a corresponding plurality of synthesized frequency values (foi). For each synthesized frequency value, a raw ratio of integers Nprawi and Dprawi is calculated, such that: f o i = Np raw i Dp raw i × f r i . A greatest common divisor (GCD) of Nprawi and Dprawi and a primitive ratio of integers Np i Dp i is found for each raw ratio of integers, such that: N p i = Np raw i GCD ? ( Np raw i , Dp raw i ) ; and , ? D p i = Dp raw i GCD ? ( Np raw i , Dp raw i ) .Type: GrantFiled: November 18, 2009Date of Patent: October 8, 2013Assignee: Applied Micro Circuits CorporationInventors: Viet Linh Do, Simon Pang

Patent number: 8521792Abstract: The present invention discloses a rate multiplication method for counting a sequence of original pulse signals and outputting a target pulse signal. In this method a comparison data and original pulse signal sequence is received. The original pulse signal sequence is counted in order to obtain a pulse count. Comparing the pulse count and the comparison data. If the pulse count is equal to the comparison data, a corresponding original pulse signal is outputted as the target pulse signal. Reset and recount the pulse count, and obtain which repeatedly. In this present invention the pulse count and the pulse interval between the target pulse signals can be determined freely according to a rate.Type: GrantFiled: February 16, 2009Date of Patent: August 27, 2013Assignee: VIA Technologies, Inc.Inventor: ChuanWei Liu

Patent number: 8280934Abstract: Systems and methods for producing a frequency divider output signal having a period substantially equal to three times a period of a reference input signal, comprising configuring each of three storage elements to receive a first input, a second input, and a reference input signal, and to provide a storage element output, obtaining a frequency divider output signal from at least one storage element output, and using the storage element output from each of the three storage elements as an input to another one of the three storage elements, where a phase difference between the output of the first storage element and the output of the second storage element is substantially equal to 60°.Type: GrantFiled: August 20, 2007Date of Patent: October 2, 2012Assignee: Mediatek, Inc.Inventors: Alyosha C. Molnar, Rahul Magoon

Patent number: 8201018Abstract: Embodiments include methods, apparatus, and systems for controlling of sparing in a storage system. In one embodiment, a method compares a first amount of time to complete sparing of data from a failed disk in a storage system with a second amount of time to complete a user request to the storage system in order to determine when to create a copy of the data from the failed disk.Type: GrantFiled: September 18, 2007Date of Patent: June 12, 2012Assignee: HewlettPackard Development Company, L.P.Inventors: Guillermo Navarro, Milos Manic, David K. Umberger

Patent number: 7937424Abstract: An alldigital frequency conversion apparatus is provided that achieves frequency conversion using a simple phase detector and integer and fractional phase feedback information from a digital oscillator output. In an embodiment, a target phase accumulator unit generates a target phase signal to the phase detector unit. The target phase accumulator unit receives inputs from a reference signal input, and a target phase input value. The digital phase detector unit receives the reference signal, a current phase feedback input signal, and the target phase input signal. The phase detector unit outputs a frequency setting signal to a frequency value generator unit. The detector output is based on the difference between the current phase and the target phase. A frequency value generator unit is configured to output a frequency value signal to a digital oscillator unit that generates a corresponding digital output signal that is directly fed back to the current phase feedback input of the phase detector unit.Type: GrantFiled: May 11, 2006Date of Patent: May 3, 2011Assignee: Tamiras Per Pte. Ltd.Inventor: Stanislav Grushin

Publication number: 20090150466Abstract: The present invention discloses a rate multiplication method for counting a sequence of original pulse signals and outputting a target pulse signal. In this method a comparison data and original pulse signal sequence is received. The original pulse signal sequence is counted in order to obtain a pulse count. Comparing the pulse count and the comparison data. If the pulse count is equal to the comparison data, a corresponding original pulse signal is outputted as the target pulse signal. Reset and recount the pulse count, and obtain which repeatedly. In this present invention the pulse count and the pulse interval between the target pulse signals can be determined freely according to a rate.Type: ApplicationFiled: February 16, 2009Publication date: June 11, 2009Applicant: VIA TECHNOLOGIES, INC.Inventor: ChuanWei Liu

Patent number: 7512644Abstract: The present invention discloses a rate multiplication method for counting a sequence of original pulse signals and outputting a target pulse signal. In this method a comparison data and original pulse signal sequence is received. The original pulse signal sequence is counted in order to obtain a pulse count. Comparing the pulse count and the comparison data. If the pulse count is equal to the comparison data, a corresponding original pulse signal is outputted as the target pulse signal. Reset and recount the pulse count, and obtain which repeatedly. In this present invention the pulse count and the pulse interval between the target pulse signals can be determined freely according to a rate.Type: GrantFiled: November 8, 2004Date of Patent: March 31, 2009Assignee: VIA Technologies, Inc.Inventor: ChuanWei Liu

Publication number: 20090022260Abstract: A binary frequency divider includes a counter paced by an input signal, means for comparing a counting value with first and second threshold values and supplying first and second control signals synchronized with variation edges of a first type of the input signal. The divider includes means for supplying at least one third control signal shifted by a halfperiod of the input signal in relation to one of the first or second control signals, and control means for generating the output signal using control signals chosen according to the value of at least one least significant bit of the division setpoint. Application is mainly but not exclusively to UHF transponders.Type: ApplicationFiled: June 18, 2008Publication date: January 22, 2009Applicant: STMicroelectronics S.A.Inventors: Christophe Moreaux, Ahmed Kari, David Naura, Pierre Rizzo

Patent number: 7457836Abstract: The invention is directed to a biquad filter circuit configured with sigmadelta devices that operate as binary rate multipliers (BRMs). Unlike conventional biquad filter circuits, the invention provides a biquad filter configured with a singlebit BRM. In another embodiment, the invention further provides a biquad filter configured with multiplebit BRMs.Type: GrantFiled: March 26, 2007Date of Patent: November 25, 2008Assignee: ESS Technology, Inc.Inventor: Andrew Martin Mallinson

Patent number: 7454450Abstract: A mixedsignal system for performing Taylor series function approximations is disclosed. The mixedsignal system includes a digitaltoanalog converter (DAC), multiple resistortoresistor (R2R) ladders, various digital registers, a digital processor and an analog integrator. The digital processor calculates coefficients F, Fx, Fy, Fxx, Fxy, Fyy of a Taylor series equation and calculates distance functions. The digital processor also includes a digital register for storing a magnitude scaling factor ?(x0,y0) of the Taylor series equation. The DAC control register uploads a lead term F(x0,y0) of the Taylor series equation from the digital processor to the DAC. The firstorder digital registers controls resistances of the R2R ladders. The secondorder digital registers uploads coefficients Fx, Fy, Fxx, Fxy, Fyy of the Taylor series equation from the digital processor to the DAC. The analog integrator adds outputs from the DAC and the R2R ladder to generate approximation results for the Taylor series equation.Type: GrantFiled: December 12, 2007Date of Patent: November 18, 2008Assignee: The Board of regents, The University of Texas SystemInventors: Brian Remy, Michael D. Bryant, Benito R. Fernandez, Shouli Yan

Patent number: 7395286Abstract: A dividebyN clock frequency divider producing N nonoverlapping clocks each with precise 1/N duty ratio is implemented by a counter, a token generator and Nbit shift register. Every N clock cycles, a pulse is generated as a token from a logical combination of signals from the counter. The pulse is passed along a shift register having balanced load capacitances under control of the clock edge, ensuring a precise 1/N duty ratio that is unaffected by load capacitances from the fault state detection and/or reset circuitry. In this manner, a higher operating frequency may be achieved with low power consumption.Type: GrantFiled: January 5, 2004Date of Patent: July 1, 2008Assignee: National Semiconductor CorporationInventors: Yongseon Koh, Jitendra Mohan

Patent number: 7366345Abstract: A method, an apparatus, and a computer program product render a multidimensional digital image using raytracing in a multidimensional space. Variables of a multidimensional digital differential analyzer (DDA) are set up using multiplications only. For each axis of the multidimensional space, a numerator holds the progress within a cell along that axis and a denominator describes a size condition causing the DDA to step to a next cell. For a vector, a denominator of the vector for an axis is equal to a delta for a vector component, excluding the component of said axis, for two dimensions; and a product of deltas for all vector components, excluding the component of said axis, for greater than two dimensions.Type: GrantFiled: February 13, 2004Date of Patent: April 29, 2008Assignee: International Business Machines CorporationInventor: Martijn Boekhorst

Patent number: 7343387Abstract: A system and method for configuring an automatic test system to produce a plurality of clocks from a reference clock includes a user interface and software. The user interface receives a plurality of inputs that specify desired frequencies of the plurality of clocks. In response to a command from the user interface, the software calculates values for dividers coupled to the reference clock, for deriving each of the desired frequencies from the reference clock. According to one embodiment, the desired frequencies form ratios that must be met to satisfy coherence. In calculating the divider values, the software minimizes frequency errors while precisely preserving the required ratios.Type: GrantFiled: February 26, 2002Date of Patent: March 11, 2008Assignee: Teradyne, Inc.Inventor: Gilbert R. Reese

Patent number: 7328229Abstract: The circuit of this invention performs clock division with dynamic divideby value change capability. This circuit provides low area and low latency. The clock divider is conventional except for the logic that handles the dynamic divideby value change. When the divideby value is changed by the user, such as through software, the changed value is recorded in a register but does not affect the divider immediately. Once the changed divideby value is recorded, the divider clock output is allowed to continue till it reaches ‘low’ and is shut off. Then the recorded value is sent to the divider. The divider then generates a clock signal corresponding to the new divideby value. The clock gating is then disabled and the clock propagates. This implements glitch free clock switching. This implementation of clock selection or switching provides low area and low latency for switching.Type: GrantFiled: January 9, 2004Date of Patent: February 5, 2008Assignee: Texas Instruments IncorporatedInventor: Subash Chandar Govindarajan

Patent number: 7317294Abstract: A pulse generator and method thereof. The pulse generator may include a first switching unit receiving a plurality of receiving a plurality of time interval indicators and a first selection signal. The first switching unit may select one of the plurality of time interval indicators in accordance with the first selection signal and may output the selected time interval indicator. The pulse generator may further include a second switching unit receiving a plurality of pulse states and a second selection signal. The second switching unit may select one of the plurality of pulse states in accordance with the second selection signal and may output the selected pulse state for a first time interval, where the first time interval may be determined by the selected time interval indicator.Type: GrantFiled: January 10, 2006Date of Patent: January 8, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Ecksang Ko

Patent number: 7272620Abstract: A frequency divider has two or more storage elements connected in a loop. One of the outputs of each storage element is connected to one of the inputs of another storage element. Each storage element provides at least one output signal having a period equal to the period of a reference input signal multiplied by the number of interconnected storage elements. The reference input signal may be, for example, a local oscillator (“LO”) signal. In the case where the reference input signal has a 50% duty cycle, the output signals will also have a 50% duty cycle. Furthermore, in the case where a total of three storage elements are connected in a loop, the outputs of two of the three storage elements can be combined to provide a signal having substantially no third order harmonics.Type: GrantFiled: March 30, 2001Date of Patent: September 18, 2007Assignee: Skyworks Solutions, Inc.Inventors: Alyosha C. Molnar, Rahul Magoon

Publication number: 20070203964Abstract: A multiplier has a multiplication array in which partial products are generated by performing multiplication between a multiplier and a multiplicand, and a partial product control circuit which generates an enable signal for activating an effective region in the multiplication array corresponding to effective figures of the multiplier and the multiplicand. The effective figures depend on the format of the multiplier and the multiplicand. The partial product control circuit controls the status of the enable signal according to a multiplication command designating the format. The multiplication array is constituted by a dynamic circuit. The dynamic circuit in an initial stage of the multiplication array has a switch which is turned on/off by the enable signal. When the enable signal is ineffective, the switch is turned off and a discharging operation in the dynamic circuit is stopped.Type: ApplicationFiled: February 23, 2007Publication date: August 30, 2007Applicant: NEC CORPORATIONInventor: Takashi Osada

Patent number: 7225092Abstract: An apparatus, a method, and a computer program are provided to measure the duty cycle of a clocking signal in a processor. Traditionally, variations in the duty cycles of clocks within microprocessors have been of considerable concern. By employing frequency dividers and AND gates, the duty cycles of clocks can be precisely measured and adjusted accordingly to account for variation that might occur. The measurements and adjustments, therefore, can improve the operation of a microprocessor or any other clocked semiconductor.Type: GrantFiled: October 21, 2004Date of Patent: May 29, 2007Assignee: International Business Machines CorporationInventors: David W. Boerstler, Eskinder Hailu, Kazuhiko Miki

Patent number: 7197522Abstract: The invention is directed to a biquad filter circuit configured with sigmadelta devices that operate as binary rate multipliers (BRMs). Unlike conventional biquad filter circuits, the invention provides a biquad filter configured with a singlebit BRM. In another embodiment, the invention further provides a biquad filter configured with multiplebit BRMs.Type: GrantFiled: June 2, 2003Date of Patent: March 27, 2007Assignee: ESS Technology, Inc.Inventor: Andrew Martin Mallinson

Patent number: 7124154Abstract: A low speed clock divider that behaves like a high speed clock divider is provided. The clock divider includes a softwareconfigurable lowspeed component for waveform generation and a highspeed component linked to the lowspeed component, the highspeed component providing an output signal by serializing a waveform received from the lowspeed component.Type: GrantFiled: November 18, 2002Date of Patent: October 17, 2006Assignee: Intel CorporationInventor: Niklas Linkewitsch

Patent number: 7124153Abstract: An alldigital frequency conversion apparatus is provided that achieves frequency conversion using a simple phase detector and integer and fractional phase feedback information from a digital oscillator output. In an embodiment, a target phase accumulator unit generates a target phase signal to the phase detector unit. The target phase accumulator unit receives inputs from a reference signal input, and a target phase input value. The digital phase detector unit receives the reference signal, a current phase feedback input signal, and the target phase input signal. The phase detector unit outputs a frequency setting signal to a frequency value generator unit. The detector output is based on the difference between the current phase and the target phase. A frequency value generator unit is configured to output a frequency value signal to a digital oscillator unit that generates a corresponding digital output signal that is directly fed back to the current phase feedback input of the phase detector unit.Type: GrantFiled: March 18, 2002Date of Patent: October 17, 2006Assignee: Genesis Microchip Inc.Inventor: Stanislav Grushin

Patent number: 7103622Abstract: A method and apparatus for reducing unwanted harmonics in direct digital synthesizer (DDS) output. The method comprises the steps of providing a set of k phaseshifted clock signals, examining, in succession, each DDS accumulator state, and determining whether the DDS accumulator state has a defined transitionstate. For each DDS accumulator state having a defined transitionstate, an interpolation is performed based upon the value of the preceding DDS accumulator state, an element of the set of phaseshifted clock signals is selected based upon the interpolation, and the most significant bit (MSB) is repositioned using the selected element of the phaseshifted clock signals. The apparatus comprises means for providing a set of k phaseshifted clock signals, means for examining, in succession, each DDS accumulator state, and means for determining whether the DDS accumulator state has a defined transitionstate.Type: GrantFiled: October 8, 2002Date of Patent: September 5, 2006Assignee: Analog Devices, Inc.Inventor: Hans Tucholski

Patent number: 7072920Abstract: A general method is provided to achieve frequency conversion in an alldigital frequency conversion device that produces an output signal having a selectable phase and frequency that is substantially synchronous with the input signal to be converted. A multiplicity of timeshifted signals is generated, and appropriate ones are selected to set and reset an output signal. An apparatus, computing system, and software product that implement the present invention are also provided.Type: GrantFiled: March 18, 2002Date of Patent: July 4, 2006Assignee: Genesis Microchip Inc.Inventor: Stanislav Grushin

Patent number: 7027597Abstract: A precomputation and dualpass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption protocol. Two passes of Montgomery's method are used for a modular operation that is associated with the encryption protocol along with precomputation of a constant based on a modulus. The modular operation may be a modular multiplication or a modular exponentiation. Modular arithmetic may be performed using the residue number system (RNS) and two RNS bases with conversions between the two RNS bases. A minimal number of register files are used for the computations along with an array of multiplier circuits and an array of modular reduction circuits. The approach described allows for high throughput for large encryption keys with a relatively small number of logical gates.Type: GrantFiled: September 18, 2001Date of Patent: April 11, 2006Assignee: Cisco Technologies, Inc.Inventors: Mihailo M. Stojancic, Mahesh S. Maddury, Kenneth J. Tomei

Patent number: 7027598Abstract: A precomputation and dualpass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption protocol. Two passes of Montgomery's method are used for a modular operation that is associated with the encryption protocol along with precomputation of a constant based on a modulus. The modular operation may be a modular multiplication or a modular exponentiation. Modular arithmetic may be performed using the residue number system (RNS) and two RNS bases with conversions between the two RNS bases. A minimal number of register files are used for the computations along with an array of multiplier circuits and an array of modular reduction circuits. The approach described allows for high throughput for large encryption keys with a relatively small number of logical gates.Type: GrantFiled: September 19, 2001Date of Patent: April 11, 2006Assignee: Cisco Technology, Inc.Inventors: Mihailo M. Stojancic, Mahesh S. Maddury, Kenneth J. Tomei

Patent number: 6978016Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design which includes a series of nearly identical processing elements linked together in a chained fashion. As a result of the twophase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.Type: GrantFiled: December 19, 2000Date of Patent: December 20, 2005Assignee: International Business Machines CorporationInventors: ChinLong Chen, Vincenzo Condorelli, Camil Fayad

Patent number: 6956793Abstract: A frequency divider circuit uses a base counter to frequency divide a clock signal with period T by an integer value N and employs a cyclic rotational select circuit to select among multiple equally phase shifted signals of a multiple phase clock to generate a fractional term P/k where P is variable from 0 to k?1. The counter counts an output clock that corresponds to the output of a multiplexer selecting from among the multiple clock phases. Depending on the desired fractional term, after N counts of the output clock phases of the multiple phase clock are selected glitch free by rotationally selecting a first phase, and skipping either 0, 1, 2 . . . up to k?1 sequential phases to generate fractional terms 0, 1/k, 2/k, 3/k . . . k?1/k, respectively, thus providing frequency division corresponding to N+P/k where P may be varied from 0 to k?1.Type: GrantFiled: November 20, 2003Date of Patent: October 18, 2005Assignee: International Business Machines CorporationInventor: Hung C. Ngo

Patent number: 6839728Abstract: Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.Type: GrantFiled: June 22, 1999Date of Patent: January 4, 2005Assignee: PTS CorporationInventors: Nikos P. Pitsianis, Gerald G. Pechanek, Ricardo E. Rodriguez

Patent number: 6807552Abstract: A noninteger fractional divider is disclosed. According to the present invention, the noninteger fractional divider comprises means for dividing a reference clock signal having a period ‘P’ by a noninteger ratio ‘K’. In a preferred embodiment, the divider comprises means for receiving a plurality ‘N’ of clock signals issued from the reference clock signal and wherein each clock signal is equally phase shifted by a ‘P/N’ delay one over the other. Selection means are coupled to the receiving means for selecting a first and a second clock signals between the plurality ‘N’ of clock signals. The selected clock signals are such that the phase shift delay between the two selected clock signals is representative of the noninteger value of the ratio ‘K’. The selected clock signals are combined into combining means to generate a clock signal being phase shifted by the noninteger part of the noninteger ratio.Type: GrantFiled: August 23, 2001Date of Patent: October 19, 2004Assignee: International Business Machines CorporationInventors: Francis Bredin, Bertrand Gabillard

Patent number: 6725245Abstract: A high speed programmable counter architecture is disclosed. In accordance with an embodiment of the present invention, the high speed programmable counter includes an n bit high speed prescaler and an m bit low speed counter. An input signal can be divided by any value equal to or greater than j*2n. The modulus of division can be provided to the programmable counter in binary form directly, without requiring complex calculations or decoding circuitry. The present invention allows high speed programmable counters to be provided that are capable of dividing by much smaller numbers than conventional counters, including numbers less than 2n*(2n−1), wherein n is equal to the number of bits in a high speed prescaler.Type: GrantFiled: May 3, 2002Date of Patent: April 20, 2004Assignee: P.C. Peripherals, IncInventor: Nicholas J. Bucska

Patent number: 6661298Abstract: A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable region. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency.Type: GrantFiled: May 21, 2002Date of Patent: December 9, 2003Assignee: The National University of SingaporeInventors: Kin Mun Lye, Jurianto Joe

Publication number: 20030208513Abstract: A high speed programmable counter architecture is disclosed. In accordance with an embodiment of the present invention, the high speed programmable counter includes an n bit high speed prescaler and an m bit low speed counter. An input signal can be divided by any value equal to or greater than j*2n. The modulus of division can be provided to the programmable counter in binary form directly, without requiring complex calculations or decoding circuitry. The present invention allows high speed programmable counters to be provided that are capable of dividing by much smaller numbers than conventional counters, including numbers less than 2n*(2n−1), wherein n is equal to the number of bits in a high speed prescaler.Type: ApplicationFiled: May 3, 2002Publication date: November 6, 2003Inventor: Nicholas J. Bucska

Patent number: 6529052Abstract: An electronic device which includes a periodic signal generator (12) and a frequency multiplier circuit (14) for multiplying the frequency of the periodic signal. The multiplier circuit is formed on the basis of an EXCLUSIVEOR gate (20), which receives the periodic signal, and a frequency divider circuit (22) connected between the output and an input of the gate. From this divider circuit it is possible to derive in a very simple way quadrature signals, which makes it feasible to perform a modulation of the type known as “zero demodulation”. The multiplier circuit can operate in accordance with CML technology (Current Mode Logic).Type: GrantFiled: May 2, 2001Date of Patent: March 4, 2003Assignee: Koninklijke Philips Electronics N.V.Inventor: Zhenhua Wang

Patent number: 6441656Abstract: A method for dividing a high frequency clock signal for analysis of all clock edges has been developed. The method includes receiving a high frequency clock signal and dividing it up into multiple phases that represent respective edges of the clock signal. The initial phases are generated by the divider with each subsequent phase lagging its preceding phase by one clock cycle. Additional subsequent phases are generated by inverting corresponding initial phases.Type: GrantFiled: July 31, 2001Date of Patent: August 27, 2002Assignee: Sun Microsystems, Inc.Inventors: Gin S. Yee, Drew G. Doblar

Publication number: 20020116423Abstract: A noninteger fractional divider is disclosed. According to the present invention, the noninteger fractional divider comprises means for dividing a reference clock signal having a period ‘P’ by a noninteger ratio ‘K’. In a preferred embodiment, the divider comprises means for receiving a plurality ‘N’ of clock signals issued from the reference clock signal and wherein each clock signal is equally phase shifted by a ‘P/N’ delay one over the other. Selection means are coupled to the receiving means for selecting a first and a second clock signals between the plurality ‘N’ of clock signals. The selected clock signals are such that the phase shift delay between the two selected clock signals is representative of the noninteger value of the ratio ‘K’. The selected clock signals are combined into combining means to generate a clock signal being phase shifted by the noninteger part of the noninteger ratio.Type: ApplicationFiled: August 23, 2001Publication date: August 22, 2002Applicant: International Business Machines CorporationInventors: Francis Bredin, Bertrand Gabillard

Publication number: 20020116422Abstract: A convolution method and apparatus of time domain convolving an input signal with a second signal is disclosed comprising the steps of; dividing the second signal into a series of segments; determining a magnitude envelope for each of the segments; scaling the signal values within each segments relative to the envelope to produce corresponding segment scaled signal values; multiplying the segment scaled values by a corresponding input signal value to produce corresponding segment output values; scaling the segment output values by a segment scale factor to produce corresponding scaled segment outputs; and adding the scaled segment output to produce a time domain output.Type: ApplicationFiled: June 22, 2001Publication date: August 22, 2002Applicant: Lake Technology LimitedInventor: David Stanley McGrath

Patent number: 6407596Abstract: An electronic circuit generates additional clock edges from a reference clock signal utilizing switchcapacitor techniques. The electronic circuit includes a first capacitance circuit and a second capacitance circuit separated by a switch. During a first time period, the switch is open and the first capacitance circuit is charged. During a second time period, the switch is closed and at least a portion of the charge stored in the first capacitance circuit is transferred to the second capacitance circuit. The amount of charge transferred depends upon the relative sizes of the capacitance circuits. During another time period, the second capacitance circuit is discharged until its associated potential reaches a threshold level corresponding to a threshold set by a level detector. Upon reaching the threshold level, the level detector outputs a logic signal. A high frequency clock signal is produced by combining the logic signal with the reference clock signal.Type: GrantFiled: April 3, 2001Date of Patent: June 18, 2002Assignee: National Semiconductor CorporationInventors: Robert Callaghan Taft, Chris William Papalias

Patent number: 6356123Abstract: A noninteger frequency divider that is capable of dividing an original clock frequency by a noninteger number into a desired target clock frequency. By this noninteger frequency divider, a phaseshifting circuit is first used to convert the original clock frequency into a predetermined number of phaseshifted versions of the original clock frequency with a predetermined phase difference. Then, a plurality of edgetriggered clock signal generators are used to generate a plurality of edgetriggered signals whose rising and falling edges are synchronized with the original clock frequency and its phaseshifted versions. Finally, a synthesis circuit is used to synthesize the edgetriggered signals into an output signal serving as the intended target clock frequency.Type: GrantFiled: August 11, 2000Date of Patent: March 12, 2002Assignee: Via Technologies, Inc.Inventors: ShanShan Lee, Jyhfong Lin

Patent number: 6351756Abstract: The present invention provides a multiplying circuit comprising: an oscillation control circuit for alternately activating first and second oscillation control signals for every clocks of an input clock signal; a first pulse signal generator circuit connected to the oscillation control circuit for receiving the first oscillation control signal so that the first pulse signal generator circuit generates a first multiplied clock signal having a higher frequency than the input clock signal only when the first oscillation control signal is in an activated state; a second pulse signal generator circuit connected to the oscillation control circuit for receiving the second oscillation control signal so that the second pulse signal generator circuit generates a second multiplied clock signal having a higher frequency than the input clock signal only when the second oscillation control signal is in an activated state; and an output circuit connected to the first and second pulse signal generator circuits for receivingType: GrantFiled: April 28, 1999Date of Patent: February 26, 2002Assignee: NEC CorporationInventor: Itsurou Taniyoshi

Patent number: 6346833Abstract: A frequency multiplier circuit outputs a desired frequency, wherein a frequency of a reference clock is divided by 4 by a frequency divider, the frequency of a unit clock is divided by 2 by another frequency divider and the output of these dividers are provided to an AND gate. A variable frequency divider divides the frequency of an output from the AND gate by n. An upcounter counts the number of pulses of the output from the variable frequency divider. Another variable frequency divider divides the frequency of the unit clock by the number of pulses to output a signal having a frequency of the reference clock multiplied by n.Type: GrantFiled: August 18, 2000Date of Patent: February 12, 2002Assignee: OKI Electric Industry Co., Ltd.Inventor: Ryuta Kuroki

Patent number: 6249235Abstract: The invention provides a sampling frequency conversion apparatus which converts a sampling frequency to another frequency using another oscillator employed in the system as the source oscillator. A fractional frequency divider divides an output of the source oscillator by a noninteger. By using outputs of the source oscillator and the divider individually as sampling clocks, an input signal is first sampled by a first sampling circuit and then an output of the first sampling circuit is sampled again by a second sampling circuit to convert the sampling frequency. The fractional frequency divider divides the clock signal of a higher one of the frequencies to produce the clock signal of a lower one of the frequencies, and the dividing ratio of the fractional frequency divider for the production of the clock signal is varied periodically to effect division of a frequency ratio having a fractional value when averaged over a time period.Type: GrantFiled: March 23, 2000Date of Patent: June 19, 2001Assignee: NEC CorporationInventor: Motoya Iwasaki

Patent number: 6112217Abstract: A method and an apparatus for generating clock signals is described, by which a period of time can be subdivided into a desired number of essentially equallength segments. The method and the apparatus are distinguished in that the clock signals are generated based on the outcomes of a repeated subtraction of a first value from a second value. The first value depends on the number of segments into which the period of time to be subdivided is to be subdivided, and the second value depends on the duration of the period of time to be subdivided.Type: GrantFiled: July 24, 1998Date of Patent: August 29, 2000Assignee: Siemens AktiengesellschaftInventors: Peter Rohm, Patrick Leteinturier